5698be672b
feat(mspi): support 120MHz flash and psram for esp32c61
2026-03-13 16:27:17 +08:00
453660968b
feat(mspi): supported psram & flash 120MHz timing tuning
2026-03-13 11:12:45 +08:00
fef58c3c20
Merge branch 'fix/min_rev_usage_v5.5' into 'release/v5.5'
...
fix: fix wrong REV_MIN usage for security, bt, efuse (v5.5)
See merge request espressif/esp-idf!45652
2026-03-07 15:40:42 +08:00
1e60df4c8c
fix(tee): fix failed to configure flash on C6 v0.1 and above when REV_MIN_0 configured
2026-03-06 19:49:06 +08:00
1187afe516
feat(esp_hw_support): hold MSPI pins in pd_top lightsleep
2026-02-10 16:19:36 +08:00
39d107fd24
fix(bootloader): fix bootloader bad spi pin drv config and clear all wpu/wpd by default
2026-02-10 16:18:36 +08:00
6c000e04f6
change(flash): improve bootloader_flash_read log
2026-01-22 02:12:55 +08:00
3d2dda8e72
fix(bootloader_flash): invalidate FLASH_READ_VADDR before read
...
Fixed address to match corresponding mmu_hal_map_region call.
FLASH_MMAP_VADDR was invalidated by mistake in commit
ea38a2e9a4
2025-12-03 10:00:57 +01:00
e54ebe08a4
fix(esp_tee): Handle the SPI1 WB mode incompatibility in TEE flash APIs on ESP32-C5
...
- When `esp_flash_read()` is invoked from REE, it internally enables WB mode
via `spi_flash_ll_wb_mode_enable()`. However, the ROM flash APIs used by TEE
do not support WB mode, resulting in failures when TEE attempts to access
flash after this call.
- This commit adds a workaround in the TEE flash layer by saving WB mode state,
temporarily disabling it for ROM API calls, and restoring it afterward.
2025-10-27 11:17:06 +05:30
695f8e46d6
Merge branch 'fix/make_bootloader_flash_size_correct_v5.5' into 'release/v5.5'
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fix(bootloader_flash): Make bootloader flash size accurate , etc. (backport v5.5)
See merge request espressif/esp-idf!41706
2025-10-20 14:21:40 +08:00
ea36c4f609
Merge branch 'feature/esp_tee_c5_v5.5' into 'release/v5.5'
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feat(esp_tee): Initial support for ESP32-C5 and related changes (v5.5)
See merge request espressif/esp-idf!42357
2025-10-16 09:39:23 +05:30
018d7c5c79
fix(bootloader_flash): Make bootloader flash size accurate
2025-10-14 17:45:29 +08:00
73d0dadd6b
fix(esp_tee): Correct flash operation bound checks to handle all overlap cases
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- Ensure bound checks correctly handle all scenarios, including
when a requested operation's (SPI0/1) range fully contains the
TEE-protected region.
- Disable delegation of INTWDT timeout and Cache error interrupts as they reset
the device after the panic handler
2025-10-14 10:12:28 +05:30
e6d4eec507
feat(p4): p4 rev3 real chip support
2025-10-13 15:25:23 +08:00
2e7a9174fc
Merge branch 'feature/esp_tee_h2_v5.5' into 'release/v5.5'
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feat(esp_tee): Support for ESP32-H2 (v5.5)
See merge request espressif/esp-idf!39311
2025-06-16 12:04:22 +05:30
b977a13796
test(psram): re-enable 80M psram tests on C5 ECO2
2025-05-26 11:32:24 +08:00
fafc25b8b9
feat(mspi): supported psram 80MHz timing tuning
2025-05-22 14:42:42 +08:00
27496e47f0
feat(esp_tee): Support for ESP32-H2 - the rest of the components
2025-05-21 10:06:17 +05:30
6c4271d4bb
feat(esp32h4): disable unsupported build
2025-03-28 14:41:29 +08:00
64ff6ec274
Merge branch 'fix/mutex_between_oct_flash_and_flash_rom_impl' into 'master'
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flash: mutex between oct flash and flash rom impl
See merge request espressif/esp-idf!37760
2025-03-21 14:51:08 +08:00
45ba78940f
feat(esp32h4): finnal introduce hello world
2025-03-19 18:48:41 +08:00
cbcee1625f
refactor(flash): rename SOC_SPI_MEM_SUPPORT_OPI_MODE to SOC_SPI_MEM_SUPPORT_FLASH_OPI_MOD
2025-03-19 14:01:22 +08:00
222b1ddbab
fix(driver_gpio): remove gpio_hal_iomux_func_sel
2025-02-19 17:17:51 +08:00
870a1846b1
Merge branch 'feature/esp_tee_flash_prot_spi1' into 'master'
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feat(esp_tee): Add support for flash memory isolation and protection (SPI1)
Closes IDF-10481, IDF-10083, and IDF-8915
See merge request espressif/esp-idf!36454
2025-02-12 18:35:49 +08:00
c23714f775
feat(esp_tee): Add support for flash memory isolation and protection (SPI1)
2025-02-11 12:30:05 +05:30
6f83f39dce
feat(esp32h4): introduce target esp32h4(stage 1)
2025-02-08 17:07:44 +08:00
3aba0ff704
Merge branch 'refactor/mspi_ll' into 'master'
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mspi: rename mspi_timing_tuning_ll.h to mspi_ll.h
Closes IDF-11918
See merge request espressif/esp-idf!36039
2025-01-08 16:29:28 +08:00
14b5db0e87
refactor(mspi): rename to mspi_ll.h
2025-01-07 16:16:06 +08:00
1499c65754
feat(esp_tee): Add support for flash memory isolation and protection (SPI0)
2025-01-03 11:44:01 +05:30
25731d0c1e
feat(esp32h21): finnal introduce hello world support
2024-12-30 20:14:40 +08:00
d448c4ed05
feat(spi_flash): Add 32M flash support on esp32c5
2024-12-25 16:06:43 +08:00
6528ab5971
refactor(mspi): refactor mspi clock src settings
2024-12-11 14:46:07 +08:00
2b1c27feb4
Merge branch 'feat/custom_flash_component' into 'master'
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feature(spi_flash): New customized flash drivers framework, including bootloader📡
Closes IDFGH-8624
See merge request espressif/esp-idf!32774
2024-12-04 18:05:58 +08:00
af31ec11f1
feat(spi_flash): New customise flash drivers framework, including bootloader
2024-12-02 17:48:40 +08:00
54c3f1bae4
feat(esp_tee): Support for ESP-TEE - bootloader_support component
2024-12-02 12:20:03 +05:30
5237876213
flash: fix qio 2nd bootloader cannot boot issue
2024-11-28 14:53:20 +08:00
64bbb53b8f
feat(esp32h21): introduce target esp32h21(stage 1)
2024-11-12 15:42:27 +08:00
afa46c06a8
feat(bootloader): add support to use MMU page size from app binary
...
For the SoCs that support configurable MMU page size, it is possible
that the bootloader and application are built with different MMU page
size configuration. This mismatch is not supported at the moment and
application verification fails (at bootup or during OTA update).
Configuring MMU page size helps to optimize the flash space by having
smaller alignment and padding (secure) requirements. Please note that
the MMU page size is tied with the flash size configuration at the
moment (`ESPTOOLPY_FLASHSIZE_XMB`).
This MR ensures that application verification happens using the MMU page
size configured in its binary header. Thus, bootloader and application
can now have different MMU page sizes and different combinations shall
be supported.
2024-11-05 20:37:18 +05:30
ad6f491459
patch(spi_flash): cleanup XMC flash chip usage according to new information
2024-10-18 10:26:26 +08:00
75e2d77b26
feat(spi_flash): Add new xmc chip id
2024-09-23 19:06:23 +08:00
9c81fe6114
fix(mspi): fixed mspi clock wrong on ram loadable app on c61, enable tests on c5 c61
2024-09-10 11:12:03 +08:00
42cf1d8867
fix(mspi): fixed mspi clock wrong on ram loadable app on c5
2024-09-10 11:12:02 +08:00
6933ba39bc
fix(system): fixed ram loadable app on p4
2024-09-09 10:31:48 +08:00
19c6e77a31
fix(mspi): collect mspi iomux pin macro from iomux_reg.h to spi_pins.h
2024-09-03 13:55:00 +08:00
a04bedc4ce
Merge branch 'bugfix/assert_ndebug' into 'master'
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feat(newlib): add option to disable eval of expression in assert() when NDEBUG set
Closes IDFGH-479 and IDFGH-8692
See merge request espressif/esp-idf!32887
2024-08-26 15:42:31 +08:00
0d140f38ea
fix(system): fixed warnings related to ununsed var if asserts disabled
2024-08-26 10:25:04 +08:00
fad2c740b1
feature(spi_flash): Promote the c61 mspi clock frequency from 40 to 80M
2024-08-22 10:58:50 +08:00
bc80476411
fix(mspi): Refactor mspi ll/soc for c5 and c61
2024-08-15 15:08:56 +08:00
9de3e737cf
feat(spiram): Add spiram support on esp32c5
2024-07-04 19:29:04 +08:00
40f3bc2e57
feat(clk): Add basic clock support for esp32c5 mp
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- Support SOC ROOT clock source switch
- Support CPU frequency change
- Support RTC SLOW clock source switch
- Support RTC SLOW clock + RC FAST calibration
- Remove FPGA build
2024-06-26 14:26:34 +08:00
Song Ruo Jing
armando
Jiang Jiang Jian
Xiao Xufeng
wuzhenghui
Samuel Obuch
Laukik Hase
morris
Mahavir Jain
C.S.M
Aditya Patwardhan
Chen Jichang
wanckl
gaoxu
Marius Vikhammer