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Merge branch 'fix/min_rev_usage_v5.5' into 'release/v5.5'

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fix: fix wrong REV_MIN usage for security, bt, efuse (v5.5)

See merge request espressif/esp-idf!45652
This commit is contained in:
Jiang Jiang Jian
2026-03-07 15:40:42 +08:00
parent 55e18b64b4 d5ecb0b27f
commit fef58c3c20
4 changed files with 21 additions and 19 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+17 -15
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@@ -232,19 +232,20 @@ static uint32_t current_read_mapping = UINT32_MAX;
*/
static void rom_read_api_workaround(void)
{
#if CONFIG_ESP32C6_REV_MIN_0
extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
#if CONFIG_ESP32C6_REV_MIN_FULL == 0
if (efuse_hal_chip_revision() == 0) {
extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
static bool is_first_call = true;
if (is_first_call) {
uint32_t dummy_val = UINT32_MAX;
uint32_t dest_addr = ESP_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_MAX_LEN;
esp_rom_spiflash_write(dest_addr, &dummy_val, sizeof(dummy_val));
is_first_call = false;
}
static bool is_first_call = true;
if (is_first_call) {
uint32_t dummy_val = UINT32_MAX;
uint32_t dest_addr = ESP_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_MAX_LEN;
esp_rom_spiflash_write(dest_addr, &dummy_val, sizeof(dummy_val));
is_first_call = false;
}
uint32_t freqdiv = 0;
uint32_t freqdiv = 0;
#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
freqdiv = 1;
@@ -265,10 +266,11 @@ static void rom_read_api_workaround(void)
read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
#endif
esp_rom_spiflash_config_clk(freqdiv, 1);
spi_dummy_len_fix(1, freqdiv);
esp_rom_spiflash_config_readmode(read_mode);
spi_common_set_dummy_output(read_mode);
esp_rom_spiflash_config_clk(freqdiv, 1);
spi_dummy_len_fix(1, freqdiv);
esp_rom_spiflash_config_readmode(read_mode);
spi_common_set_dummy_output(read_mode);
}
#endif
}
components/bt/include/esp32c3/include/esp_bt.h
+2 -2
View File
@@ -175,11 +175,11 @@ typedef void (* esp_bt_hci_tl_callback_t) (void *arg, uint8_t status);
#define BT_CTRL_AGC_RECORRECT_NEW 1
#else
//Check if chip target is ESP32-C3 101
#if CONFIG_ESP32C3_REV_MIN_101
#if CONFIG_ESP32C3_REV_MIN_FULL >= 101
#define BT_CTRL_AGC_RECORRECT_NEW 1
#else
#define BT_CTRL_AGC_RECORRECT_NEW 0
#endif // CONFIG_ESP32C3_REV_MIN_101
#endif // CONFIG_ESP32C3_REV_MIN_FULL >= 101
#endif // CONFIG_IDF_TARGET_ESP32S3
#else
components/esp_psram/include/esp_private/esp_psram_mspi.h
+1 -1
View File
@@ -15,7 +15,7 @@
extern "C" {
#endif
#define ESP_PSRAM_MSPI_MB_WORKAROUND (CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL < 102) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL < 101)
#define ESP_PSRAM_MSPI_MB_WORKAROUND ((CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL < 102) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL < 101))
/**
* @brief Initialize PSRAM MSPI memory barrier
components/esp_rom/patches/esp_rom_sys.c
+1 -1
View File
@@ -157,5 +157,5 @@ void __attribute__((constructor)) ets_ops_set_rom_patches(void)
ets_ops_table_ptr = &ets_ops_patch_table_ptr;
}
#endif // CONFIG_ESP32C5_REV_MIN_100 || CONFIG_ESP32C61_REV_MIN_100
#endif // CONFIG_ESP32C5_REV_MIN_FULL <= 100 || CONFIG_ESP32C61_REV_MIN_FULL <= 100
#endif // ESP_ROM_DELAY_US_PATCH && CONFIG_SECURE_ENABLE_TEE && !NON_OS_BUILD