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961 Commits

Author SHA1 Message Date
morris 36a6bfe3a6 feat(soc): make flash encryption depends on SOC_FLASH_ENC_SUPPORTED 2026-01-14 16:04:28 +08:00
morris dad6e2b020 Merge branch 'feat/support_clk_tree_on_h4mp' into 'master' 
feat(clk): support clk tree on h4mp

Closes IDF-13632

See merge request espressif/esp-idf!43962
 2026-01-07 15:21:04 +08:00
morris 796e85f0f6 refactor(tests): add missing sdkconfig files in the driver test 2026-01-04 22:36:04 +08:00
Song Ruo Jing 215c9993bf fix(clk): update H4 to use 64MHz clock for mspi 
And add pll clock ref count
 2026-01-04 14:07:01 +08:00
armando f8135a43cb fix(cache): fixed cache sync ops concurrent call issue 
Closes https://github.com/espressif/esp-idf/issues/18023
 2025-12-24 01:12:47 +00:00
morris 29560e6102 refactor(gdma): skip the null buffer in mount pre-check 2025-12-22 22:02:28 +08:00
wuzhenghui 353075ca30 change(esp_hw_support): reject sleep request if task stack in PSRAM 2025-12-19 10:27:28 +08:00
Xiao Xufeng 230ee88d99 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes 
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
 2025-12-16 17:42:44 +08:00
Mahavir Jain c4fda6cb2f fix(spi_flash): limit CPU clock to 160MHz for encrypted flash writes 2025-12-16 17:41:25 +08:00
morris 291554cd09 refactor(global): remove completed todos in the codebase 2025-12-15 22:40:15 +08:00
Wan Lei a633083633 Merge branch 'fix/spi_clean_soc_caps' into 'master' 
refactor(driver_spi): clean spi soc caps

See merge request espressif/esp-idf!44083
 2025-12-15 20:48:21 +08:00
C.S.M 07519fac25 fix(spi_flash): Cleanup jira tickets 2025-12-12 17:53:01 +08:00
C.S.M e3eaee53e2 Merge branch 'ci/esp32s31_build_ena' into 'master' 
ci(esp32s31): Add ci build test for esp32s31

See merge request espressif/esp-idf!44045
 2025-12-12 14:59:42 +08:00
Wan Lei d6f02d5c8c Merge branch 'feat/split_esp_hal_spi_component' into 'master' 
feat(driver_spi): split spi hal component

Closes IDF-14094

See merge request espressif/esp-idf!43890
 2025-12-12 12:06:31 +08:00
wanckl 13e1ae57e1 refactor(driver_spi): clean spi soc caps 2025-12-12 11:29:42 +08:00
C.S.M f405e51784 ci(esp32s31): Add ci build test for esp32s31 2025-12-11 15:17:15 +08:00
wanckl 6449181ce0 feat(driver_spi): split spi hal component 2025-12-11 15:00:18 +08:00
He Binglin 7a4acd64c7 Merge branch 'feature/support_lightsleep_flash_dpd_mode' into 'master' 
feat: Support set flash to deep power down mode in lightsleep

Closes PM-619 and IDF-7359

See merge request espressif/esp-idf!25578
 2025-12-10 15:48:55 +08:00
hebinglin e29c2c9a36 feat(spi_flash): add flash deep power down support in spi flash 2025-12-09 17:19:01 +08:00
armando 1bebcab852 fix(ci): fixed spi_flash bld ci 2025-12-08 10:54:55 +08:00
Adam Múdry cb98f7b5ef Merge branch 'feat/spi_flash_bdl_support' into 'master' 
feat(bdl): Add support for spi_flash

Closes IDF-12752

See merge request espressif/esp-idf!42127
 2025-12-05 10:29:39 +01:00
Adam Múdry cf95a64365 feat(bdl): Add support for spi_flash 2025-12-04 16:16:28 +01:00
C.S.M 690dfd8c79 Merge branch 'feat/introduce_esp32s31_hello_world' into 'master' 
feat(esp32s31): Introduce esp32s31 hello world 🛸

See merge request espressif/esp-idf!43761
 2025-12-03 13:36:01 +08:00
C.S.M 0c4cf75c35 feat(esp32s31): Introduce esp32s31 hello world 2025-12-02 10:44:16 +08:00
C.S.M 986481f616 Merge branch 'ci/freertos_header' into 'master' 
ci(header_check): Add check for public header should not include freertos

Closes IDF-10013

See merge request espressif/esp-idf!43219
 2025-12-02 10:42:26 +08:00
C.S.M d5054072eb ci(header_check): Add check for public header should not include freertos 2025-11-28 19:15:17 +08:00
Song Ruo Jing 1862fdec74 refactor(gpio): split GPIO HAL into separate component 
cleaned up some includes in GPIO peripheral files
 2025-11-26 15:35:07 +08:00
C.S.M 958a4bffc8 feat(esp32s31): Add soc register from t~z and manually headers 2025-11-20 11:58:03 +08:00
C.S.M 961bd0cf78 Merge branch 'feat/introduce_esp32s31' into 'master' 
feat(esp32s31): Introduce new target esp32s31

See merge request espressif/esp-idf!43316
 2025-11-18 15:55:16 +08:00
morris aa1fd9c611 refactor: avoid function calls inside MIN/MAX macros 2025-11-17 22:17:54 +08:00
C.S.M a90c93541c feat(esp32s31): Introduce new target esp32s31 2025-11-17 14:48:55 +08:00
radek.tandler fffef09b50 fix(spi-flash): Fixed missing flash write check of non 4-byte aligned data 2025-10-30 12:20:32 +08:00
radek.tandler c16f82b367 fix(spi-flash): Fixed wrong offset calculation in s_verify_write log message 2025-10-30 11:38:40 +08:00
Armando (Dou Yiwen) 12aebb36d0 Merge branch 'feat/c5_flash_psram_timing_tuning_120m' into 'master' 
mspi: supported psram & flash 120MHz timing tuning

See merge request espressif/esp-idf!42508
 2025-10-29 06:12:32 +00:00
C.S.M 6659af07c8 Merge branch 'fix/soft_resume' into 'master' 
fix(spi_flash): Fix software resume wrong config name in flash init

See merge request espressif/esp-idf!42697
 2025-10-28 11:17:22 +08:00
armando 755ee49b72 feat(mspi): supported psram & flash 120MHz timing tuning 2025-10-28 09:52:36 +08:00
Marius Vikhammer cd741e995f test(system): restructured system build test test-apps 2025-10-27 09:25:07 +08:00
C.S.M af0187ebaf fix(spi_flash): Fix software resume wrong config name in flash init 2025-10-24 10:35:40 +08:00
C.S.M c81cf3bdf6 refactor(spi_flash): Remove spi_flash rom driver patch config option 2025-10-22 10:37:19 +08:00
morris e8de5b5a95 refactor(gptimer): clean up SOC capabilities for GPTIMER and Timer Group 
- Remove GPTIMER and TIMG related definitions from soc_caps_full.h files
- Move timer peripheral definitions to appropriate HAL layer files
- Update references across components to use proper HAL abstractions
- Consolidate timer group and GPTIMER capabilities organization
- Ensure consistent timer configuration across all ESP32 variants

This refactoring improves the separation of concerns between SOC
capabilities and HAL implementations for timer-related functionality.
 2025-10-14 11:44:38 +08:00
morris cd41b6a640 refactor: remove unnecessary driver dependencies from build rules 2025-10-11 14:02:29 +08:00
Peter Dragun 800f141f94 Merge branch 'feat/esptool_v5' into 'master' 
Update esptool to v5: replace deprecated commands, documentation updates and cleanup

Closes IDF-12564

See merge request espressif/esp-idf!41176
 2025-10-01 14:36:26 +08:00
Peter Dragun e3198fff3c feat: Update esptool to v5 2025-09-30 15:28:55 +02:00
Chen Chen a4710cc206 refactor(driver): remove redundant driver dependencies 
now the driver component only contains legacy code for i2c, twai and
touch sensor
 2025-09-30 15:47:45 +08:00
C.S.M a417158514 Merge branch 'feat/mspi_suspend_p4_eco5' into 'master' 
feat(spi_flash): Support flash suspend on esp32p4 resivion 3

Closes IDF-13511

See merge request espressif/esp-idf!42104
 2025-09-30 15:14:09 +08:00
C.S.M f022b67486 feat(spi_flash): Support flash suspend on esp32p4 resivion 3 2025-09-28 16:25:28 +08:00
C.S.M b145ede835 refactor(mspi): Make mspi hal layer independent 2025-09-26 14:57:54 +08:00
Konstantin Kondrashov b7da740f12 Merge branch 'feature/log_v2_optimization' into 'master' 
feat(log): Optimize idf components for binary logging

Closes IDF-12775

See merge request espressif/esp-idf!40289
 2025-09-19 14:45:43 +08:00
Konstantin Kondrashov 16d73cdab3 feat(log): Adds ESP_LOG_ATTR macro to control section placement 2025-09-15 15:59:52 +03:00
Konstantin Kondrashov dcf486359e feat(log): Optimize log tag init for bin logging 2025-09-15 15:59:52 +03:00