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esp-idf/components/efuse/esp32h4/esp_efuse_table.csv
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Konstantin Kondrashov 8701705ec3 feat(efuse): Update efuse table for ESP32-H4
2026-04-01 16:15:45 +03:00

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1# field_name, | efuse_block, | bit_start, | bit_count, |comment #
2# | (EFUSE_BLK0 | (0..255) | (1-256) | #
3# | EFUSE_BLK1 | | | #
4# | ...) | | | #
5##########################################################################
6# !!!!!!!!!!! #
7# this will generate new source files, next rebuild all the sources.
8# !!!!!!!!!!! #
9# This file was generated by regtools.py based on the efuses.yaml file with the version: 6c3ca4b9e6c9ee71a1a0627fa77a905a
10WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
11WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
12WR_DIS.KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DISABLE_DEPLOY_MODE
13WR_DIS.KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_RND_SWITCH_CYCLE
14WR_DIS.KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 1, 1, [] wr_dis of KM_DEPLOY_ONLY_ONCE
15WR_DIS.FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_USE_KEY_MANAGER_KEY
16WR_DIS.FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of FORCE_DISABLE_SW_INIT_KEY
17WR_DIS.KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 1, 1, [] wr_dis of KM_XTS_KEY_LENGTH_256
18WR_DIS.LOCK_KM_KEY, EFUSE_BLK0, 1, 1, [] wr_dis of LOCK_KM_KEY
19WR_DIS.DIS_USB_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB_JTAG
20WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
21WR_DIS.SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 2, 1, [] wr_dis of SPI_DOWNLOAD_MSPI_DIS
22WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_TWAI
23WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
24WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
25WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
26WR_DIS.PVT_GLITCH_EN, EFUSE_BLK0, 2, 1, [] wr_dis of PVT_GLITCH_EN
27WR_DIS.PVT_GLITCH_MODE, EFUSE_BLK0, 2, 1, [] wr_dis of PVT_GLITCH_MODE
28WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
29WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
30WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
31WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
32WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
33WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
34WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
35WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
36WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
37WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
38WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of SEC_DPA_LEVEL
39WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
40WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE
41WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME
42WR_DIS.SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 14, 1, [] wr_dis of SECURE_BOOT_SHA384_EN
43WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
44WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
45WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
46WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
47WR_DIS.DIS_DIRECT_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DIRECT_BOOT
48WR_DIS.DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_ROM_PRINT
49WR_DIS.DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE
50WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
51WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
52WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
53WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
54WR_DIS.HUK_GEN_STATE, EFUSE_BLK0, 19, 1, [] wr_dis of HUK_GEN_STATE
55WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
56WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
57WR_DIS.MAC_EXT, EFUSE_BLK0, 20, 1, [] wr_dis of MAC_EXT
58WR_DIS.PVT_LIMIT, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_LIMIT
59WR_DIS.PVT_CELL_SELECT, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_CELL_SELECT
60WR_DIS.PVT_PUMP_LIMIT, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_PUMP_LIMIT
61WR_DIS.PUMP_DRV, EFUSE_BLK0, 20, 1, [] wr_dis of PUMP_DRV
62WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 20, 1, [] wr_dis of WDT_DELAY_SEL
63WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 20, 1, [] wr_dis of HYS_EN_PAD
64WR_DIS.PVT_GLITCH_CHARGE_RESET, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_GLITCH_CHARGE_RESET
65WR_DIS.VDD_SPI_LDO_ADJUST, EFUSE_BLK0, 20, 1, [] wr_dis of VDD_SPI_LDO_ADJUST
66WR_DIS.FLASH_LDO_POWER_SEL, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_LDO_POWER_SEL
67WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
68WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
69WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
70WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
71WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
72WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
73WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
74WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
75WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
76WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
77WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP
78WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
79WR_DIS.PVT_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_DBIAS
80WR_DIS.ADJUST_1V2, EFUSE_BLK0, 20, 1, [] wr_dis of ADJUST_1V2
81WR_DIS.ADJUST_1V8, EFUSE_BLK0, 20, 1, [] wr_dis of ADJUST_1V8
82WR_DIS.ACTIVE_DCDC_1V25, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_DCDC_1V25
83WR_DIS.ACTIVE_DCDC_1V35, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_DCDC_1V35
84WR_DIS.SLP_DCDC, EFUSE_BLK0, 20, 1, [] wr_dis of SLP_DCDC
85WR_DIS.LSLP_HP_DRVB, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DRVB
86WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
87WR_DIS.TEMP_CALIB, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP_CALIB
88WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
89WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
90WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
91WR_DIS.DCDC_OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of DCDC_OCODE
92WR_DIS.VDD_3V4_DOUT, EFUSE_BLK0, 21, 1, [] wr_dis of VDD_3V4_DOUT
93WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
94WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
95WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
96WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
97WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
98WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
99WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
100WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
101WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
102WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
103WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
104WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
105WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
106WR_DIS.INITCODE_DIFF_1P8_3P3, EFUSE_BLK0, 21, 1, [] wr_dis of INITCODE_DIFF_1P8_3P3
107WR_DIS.HI_DOUT_DIFF_1P8_3P3, EFUSE_BLK0, 21, 1, [] wr_dis of HI_DOUT_DIFF_1P8_3P3
108WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
109WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
110WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
111WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
112WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
113WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
114WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
115WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
116WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
117WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
118WR_DIS.USB_OTG_FS_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_OTG_FS_EXCHG_PINS
119WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 30, 1, [] wr_dis of USB_PHY_SEL
120WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
121RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
122RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
123RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
124RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
125RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
126RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
127RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
128RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
129DIS_USB_JTAG, EFUSE_BLK0, 39, 1, [] Represents whether the function of usb switch to jtag is disabled or enabled. 1: disabled 0: enabled
130DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 41, 1, [] Represents whether the function that forces chip into download mode is disabled or enabled. 1: disabled 0: enabled
131SPI_DOWNLOAD_MSPI_DIS, EFUSE_BLK0, 42, 1, [] Represents whether SPI0 controller during boot_mode_download is disabled or enabled. 1: disabled 0: enabled
132DIS_TWAI, EFUSE_BLK0, 43, 1, [] Represents whether TWAI function is disabled or enabled. 1: disabled 0: enabled
133JTAG_SEL_ENABLE, EFUSE_BLK0, 44, 1, [] Represents whether the selection between usb_to_jtag and pad_to_jtag through strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0 is enabled or disabled. 1: enabled 0: disabled
134DIS_PAD_JTAG, EFUSE_BLK0, 45, 1, [] Represents whether JTAG is disabled in the hard way(permanently). 1: disabled 0: enabled
135DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 46, 1, [] Represents whether flash encrypt function is disabled or enabled(except in SPI boot mode). 1: disabled 0: enabled
136PVT_GLITCH_EN, EFUSE_BLK0, 50, 1, [] Represents whether to enable PVT power glitch monitor function.1:Enable. 0:Disable
137PVT_GLITCH_MODE, EFUSE_BLK0, 52, 2, [] Use to configure glitch mode
138DIS_CORE1, EFUSE_BLK0, 54, 1, [] Represents whether the CPU-Core1 is disabled. 1: Disabled. 0: Not disable
139SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 58, 1, [] Revoke 1st secure boot key
140SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 59, 1, [] Revoke 2nd secure boot key
141SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 60, 1, [] Revoke 3rd secure boot key
142KEY_PURPOSE_0, EFUSE_BLK0, 64, 5, [KEY0_PURPOSE] Represents the purpose of Key0
143KEY_PURPOSE_1, EFUSE_BLK0, 69, 5, [KEY1_PURPOSE] Represents the purpose of Key1
144KEY_PURPOSE_2, EFUSE_BLK0, 74, 5, [KEY2_PURPOSE] Represents the purpose of Key2
145KEY_PURPOSE_3, EFUSE_BLK0, 79, 5, [KEY3_PURPOSE] Represents the purpose of Key3
146KEY_PURPOSE_4, EFUSE_BLK0, 84, 5, [KEY4_PURPOSE] Represents the purpose of Key4
147KEY_PURPOSE_5, EFUSE_BLK0, 89, 5, [KEY5_PURPOSE] Represents the purpose of Key5
148SEC_DPA_LEVEL, EFUSE_BLK0, 94, 2, [] Represents the spa secure level by configuring the clock random divide mode
149XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 96, 2, [] Represents the pseudo round level of xts-aes anti-dpa attack. 3: High. 2: Moderate 1. Low 0: Disabled
150XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 98, 1, [] Represents whether xts-aes anti-dpa attack clock is enabled. 1. Enable. 0: Disable.
151ECC_FORCE_CONST_TIME, EFUSE_BLK0, 99, 1, [] Represents whether to force ecc to use const-time calculation mode. 1: Enable. 0: Disable
152SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 100, 1, [] Represents if the chip supports Secure Boot using SHA-384
153SECURE_BOOT_EN, EFUSE_BLK0, 101, 1, [] Represents whether secure boot is enabled or disabled. 1: enabled 0: disabled
154SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 102, 1, [] Represents whether revoking aggressive secure boot is enabled or disabled. 1: enabled. 0: disabled
155KM_DISABLE_DEPLOY_MODE, EFUSE_BLK0, 103, 5, [] Represents whether the new key deployment of key manager is disabled. Bit0: Represents whether the new ECDSA key deployment is disabled0: Enabled1: DisabledBit1: Represents whether the new XTS-AES (flash and PSRAM) key deployment is disabled0: Enabled1: DisabledBit2: Represents whether the new HMAC key deployment is disabled0: Enabled1: DisabledBit3: Represents whether the new DS key deployment is disabled0: Enabled1: Disabled
156KM_RND_SWITCH_CYCLE, EFUSE_BLK0, 108, 2, [] Represents the cycle at which the Key Manager switches random numbers.0: Controlled by the \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For more information; please refer to Chapter \ref{mod:keymng} \textit{\nameref{mod:keymng}}1: 8 Key Manager clock cycles2: 16 Key Manager clock cycles3: 32 Key Manager clock cycles
157KM_DEPLOY_ONLY_ONCE, EFUSE_BLK0, 110, 5, [] Represents whether the corresponding key can be deployed only once.Bit0: Represents whether the ECDSA key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit1: Represents whether the XTS-AES (flash and PSRAM) key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit2: Represents whether the HMAC key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only onceBit3: Represents whether the DS key can be deployed only once0: The key can be deployed multiple times1: The key can be deployed only once
158FORCE_USE_KEY_MANAGER_KEY, EFUSE_BLK0, 115, 5, [] Represents whether the corresponding key must come from Key Manager. Bit0: Represents whether the ECDSA key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit1: Represents whether the XTS-AES (flash and PSRAM) key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit2: Represents whether the HMAC key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key ManagerBit3: Represents whether the DS key must come from Key Manager.0: The key does not need to come from Key Manager1: The key must come from Key Manager
159FORCE_DISABLE_SW_INIT_KEY, EFUSE_BLK0, 120, 1, [] Represents whether to disable the use of the initialization key written by software and instead force use efuse\_init\_key.0: Enable1: Disable
160KM_XTS_KEY_LENGTH_256, EFUSE_BLK0, 121, 1, [] Represents which key flash encryption uses.0: XTS-AES-256 key1: XTS-AES-128 key
161LOCK_KM_KEY, EFUSE_BLK0, 122, 1, [] Represents whether the keys in the Key Manager are locked after deployment.0: Not locked1: Locked
162FLASH_TPUW, EFUSE_BLK0, 123, 3, [] Represents the flash waiting time after power-up; in unit of ms. When the value less than 15; the waiting time is the programmed value. Otherwise; the waiting time is 2 times the programmed value
163DIS_DOWNLOAD_MODE, EFUSE_BLK0, 127, 1, [] Represents whether Download mode is disabled or enabled. 1: disabled 0: enabled
164DIS_DIRECT_BOOT, EFUSE_BLK0, 128, 1, [] Represents whether direct boot mode is disabled or enabled. 1: disabled 0: enabled
165DIS_USB_SERIAL_JTAG_ROM_PRINT, EFUSE_BLK0, 129, 1, [] Represents whether print from USB-Serial-JTAG is disabled or enabled. 1: disabled 0: enabled
166DIS_USB_SERIAL_JTAG_DOWNLOAD_MODE, EFUSE_BLK0, 130, 1, [] Represents whether the USB-Serial-JTAG download function is disabled or enabled. 1: Disable 0: Enable
167ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 131, 1, [] Represents whether security download is enabled or disabled. 1: enabled 0: disabled
168UART_PRINT_CONTROL, EFUSE_BLK0, 132, 2, [] Represents the type of UART printing. 00: force enable printing 01: enable printing when GPIO8 is reset at low level 10: enable printing when GPIO8 is reset at high level 11: force disable printing
169FORCE_SEND_RESUME, EFUSE_BLK0, 134, 1, [] Represents whether ROM code is forced to send a resume command during SPI boot. 1: forced 0:not forced
170SECURE_VERSION, EFUSE_BLK0, 135, 16, [] Represents the version used by ESP-IDF anti-rollback feature
171HUK_GEN_STATE, EFUSE_BLK0, 151, 5, [] Represents whether the HUK generate mode is valid.Odd count of bits with a value of 1: InvalidEven count of bits with a value of 1: Valid
172FLASH_LDO_EFUSE_SEL, EFUSE_BLK0, 156, 1, [] Represents whether to select efuse control flash ldo default voltage. 1 : efuse 0 : strapping
173USB_EXCHG_PINS, EFUSE_BLK0, 168, 1, [] Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged. 1: exchanged 0: not exchanged
174USB_OTG_FS_EXCHG_PINS, EFUSE_BLK0, 169, 1, [] Represents whether the D+ and D- pins of USB_OTG_FS PHY is exchanged. 1: exchanged 0: not exchanged
175USB_PHY_SEL, EFUSE_BLK0, 170, 1, [] Represents whether to exchange the USB_SERIAL_JTAG PHY with USB_OTG_FS PHY. 1: exchanged. 0: not exchanged
176SOFT_DIS_JTAG, EFUSE_BLK0, 171, 3, [] Represents whether JTAG is disabled in soft way. Odd number: disabled Even number: enabled
177IO_LDO_ADJUST, EFUSE_BLK0, 174, 8, [] Represents configuration of IO LDO mode and voltage.
178IO_LDO_1P8, EFUSE_BLK0, 182, 1, [] Represents select IO LDO voltage to 1.8V or 3.3V. 1: 1.8V 0: 3.3V
179DCDC_CCM_EN, EFUSE_BLK0, 183, 1, [] Represents whether change DCDC to CCM mode
180MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
181, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
182, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
183, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
184, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
185, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
186MAC_EXT, EFUSE_BLK1, 56, 8, [] Stores the extended bits of MAC address
187, EFUSE_BLK1, 48, 8, [] Stores the extended bits of MAC address
188PVT_LIMIT, EFUSE_BLK1, 64, 16, [] Power glitch monitor threthold
189PVT_CELL_SELECT, EFUSE_BLK1, 80, 7, [] Power glitch monitor PVT cell select
190PVT_PUMP_LIMIT, EFUSE_BLK1, 87, 8, [] Use to configure voltage monitor limit for charge pump
191PUMP_DRV, EFUSE_BLK1, 96, 4, [] Use to configure charge pump voltage gain
192WDT_DELAY_SEL, EFUSE_BLK1, 100, 2, [] Represents the threshold level of the RTC watchdog STG0 timeout. 0: Original threshold configuration value of STG0 *2 1: Original threshold configuration value of STG0 *4 2: Original threshold configuration value of STG0 *8 3: Original threshold configuration value of STG0 *16
193HYS_EN_PAD, EFUSE_BLK1, 102, 1, [] Represents whether the hysteresis function of corresponding PAD is enabled. 1: enabled 0:disabled
194PVT_GLITCH_CHARGE_RESET, EFUSE_BLK1, 103, 1, [] Represents whether to trigger reset or charge pump when PVT power glitch happened.1:Trigger charge pump. 0:Trigger reset
195VDD_SPI_LDO_ADJUST, EFUSE_BLK1, 105, 8, [] Represents configuration of FLASH LDO mode and voltage.
196FLASH_LDO_POWER_SEL, EFUSE_BLK1, 113, 1, [] Represents which flash ldo be select: 1: FLASH LDO 1P2 0 : FLASH LDO 1P8
197WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] Minor chip version
198WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] Major chip version
199DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 120, 1, [] Disables check of wafer version major
200DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 1, [] Disables check of blk version major
201BLK_VERSION_MINOR, EFUSE_BLK1, 122, 3, [] BLK_VERSION_MINOR of BLOCK2
202BLK_VERSION_MAJOR, EFUSE_BLK1, 125, 2, [] BLK_VERSION_MAJOR of BLOCK2
203FLASH_CAP, EFUSE_BLK1, 127, 3, [] Flash capacity
204FLASH_VENDOR, EFUSE_BLK1, 130, 3, [] Flash vendor
205PSRAM_CAP, EFUSE_BLK1, 133, 3, [] Psram capacity
206PSRAM_VENDOR, EFUSE_BLK1, 136, 2, [] Psram vendor
207TEMP, EFUSE_BLK1, 138, 2, [] Temp (die embedded inside)
208PKG_VERSION, EFUSE_BLK1, 140, 3, [] Package version
209PVT_DBIAS, EFUSE_BLK1, 143, 5, [] PVT DBIAS
210ADJUST_1V2, EFUSE_BLK1, 148, 4, [] SPI LDO adjust of 1.2v
211ADJUST_1V8, EFUSE_BLK1, 152, 4, [] SPI LDO adjust of 1.8v
212ACTIVE_DCDC_1V25, EFUSE_BLK1, 156, 4, [] DCDC-DCDC DBIAS of 1.25v
213ACTIVE_DCDC_1V35, EFUSE_BLK1, 160, 4, [] DCDC-DCDC DBIAS of 1.35v
214SLP_DCDC, EFUSE_BLK1, 164, 5, [] DCDC DBIAS in sleep
215LSLP_HP_DRVB, EFUSE_BLK1, 169, 5, [] HP DRVB in light sleep
216DSLP_LP_DBIAS, EFUSE_BLK1, 174, 2, [] LP DBIAS in deep sleep
217TEMP_CALIB, EFUSE_BLK1, 176, 10, [] Temperature calibration data
218OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
219OCODE, EFUSE_BLK2, 128, 8, [] ADC OCode
220DCDC_OCODE, EFUSE_BLK2, 136, 8, [] DCDC OCode
221VDD_3V4_DOUT, EFUSE_BLK2, 144, 10, [] ADC dout of vdd 3.4v
222ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 154, 9, [] Average initcode of ADC1 atten0
223ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 163, 9, [] Average initcode of ADC1 atten1
224ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 172, 9, [] Average initcode of ADC1 atten2
225ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 181, 9, [] Average initcode of ADC1 atten3
226ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 190, 9, [] HI dout of ADC1 atten0
227ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 199, 9, [] HI dout of ADC1 atten1
228ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 208, 9, [] HI dout of ADC1 atten2
229ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 217, 9, [] HI dout of ADC1 atten3
230ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 226, 3, [] Gap between ADC1 CH0 and average initcode
231ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 3, [] Gap between ADC1 CH1 and average initcode
232ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 232, 3, [] Gap between ADC1 CH2 and average initcode
233ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 235, 3, [] Gap between ADC1 CH3 and average initcode
234ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 238, 3, [] Gap between ADC1 CH4 and average initcode
235INITCODE_DIFF_1P8_3P3, EFUSE_BLK2, 241, 5, [] Initcode diff between IO LDO 1.8v and 3.3v
236HI_DOUT_DIFF_1P8_3P3, EFUSE_BLK2, 246, 5, [] HI dout diff between IO LDO 1.8v and 3.3v
237USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
238USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
239KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
240KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
241KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
242KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
243KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
244KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
245SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
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