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Song Ruo Jing
34 lines
1.5 KiB
Markdown
34 lines
1.5 KiB
Markdown
# ESP Hardware Abstraction Layer for PPA Peripheral
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> [!NOTE]
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> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
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## Overview
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The `esp_hal_ppa` component provides a **Hardware Abstraction Layer** for the PPA (Pixel Processing Accelerator) peripheral across ESP-IDF supported targets that implement it.
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## Architecture
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The PPA HAL is structured in two main sub-layers:
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1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control the PPA peripheral (e.g., initialization, task submission, engine control, and synchronization).
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2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
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## Features
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- Engine initialization and reset helpers
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- Task/command configuration helpers (depending on target capabilities)
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- Interrupt and status helpers
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- Clock and power-management hooks (on supported chips)
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## Usage
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The HAL functions primarily serve ESP-IDF peripheral drivers such as `esp_driver_ppa`.
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Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
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## Dependencies
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- `soc`: Provides chip-specific register definitions
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- `hal`: Core hardware abstraction utilities and macros
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