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113 lines
2.8 KiB
C
113 lines
2.8 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/gpio_pins.h"
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#include "soc/soc_caps.h"
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#include "soc/gpio_sig_map.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if SOC_USB_OTG_SUPPORTED
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/* ---------------------------------- Types --------------------------------- */
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/**
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* @brief USB PHY Instance Type
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*/
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typedef enum {
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USB_PHY_INST_FSLS_INTERN_0 = (1 << 0),
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USB_PHY_INST_FSLS_INTERN_1 = (1 << 1),
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USB_PHY_INST_UTMI_0 = (1 << 2),
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USB_PHY_INST_EXTERN = (1 << 3),
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} usb_phy_inst_t;
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/**
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* @brief USB PHY FSLS Serial Interface Signals
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*
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* Structure to store the GPIO matrix signal indexes for a USB PHY FSLS Serial
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* interface's signals.
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*
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* @note Refer to section "2.2.1.13 FsLsSerialMode" of the UTMI+ for more
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* details regarding the FSLS Serial Interface.
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*/
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typedef struct {
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// Inputs
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int rx_dp;
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int rx_dm;
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int rx_rcv;
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// Outputs
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int suspend_n;
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int tx_enable_n;
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int tx_dp;
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int tx_dm;
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int fs_edge_sel;
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} usb_fsls_serial_signal_conn_t;
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/**
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* @brief USB PHY UTMI OTG Interface Signal Index Type
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*
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* Structure to store the GPIO matrix signal indexes for a UTMI PHY interface's
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* OTG signals.
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*/
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typedef struct {
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// Inputs
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int iddig;
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int avalid;
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int bvalid;
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int vbusvalid;
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int sessend;
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// Outputs
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int idpullup;
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int dppulldown;
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int dmpulldown;
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int drvvbus;
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int chrgvbus;
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int dischrgvbus;
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} usb_otg_signal_conn_t;
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/**
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* @brief Internal USB PHY IO
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*
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* Structure to store the IO numbers for a particular internal USB PHY
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*/
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typedef struct {
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int dp;
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int dm;
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} usb_internal_phy_io_t;
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/**
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* @brief USB Controller Information
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*
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* Structure to store information for all USB-DWC instances
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*
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* For targets with multiple USB controllers, we support only fixed mapping of the PHYs.
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* This is a software limitation; the hardware supports swapping Controllers and PHYs.
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*/
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typedef struct {
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struct {
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const usb_fsls_serial_signal_conn_t * const fsls_signals; // Must be set if external PHY is supported by controller
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const usb_otg_signal_conn_t * const otg_signals;
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const usb_internal_phy_io_t * const internal_phy_io; // Must be set for internal FSLS PHY(s)
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const usb_phy_inst_t supported_phys; // Bitmap of supported PHYs by this controller
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const int irq;
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const int irq_2nd_cpu; // The USB-DWC can provide 2nd interrupt so each CPU can have its own interrupt line. Set to -1 if not supported
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} controllers [SOC_USB_OTG_PERIPH_NUM];
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} usb_dwc_info_t;
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extern const usb_dwc_info_t usb_dwc_info;
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#endif // SOC_USB_OTG_SUPPORTED
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#ifdef __cplusplus
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}
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#endif
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