Files
esp-idf/examples/system
Meet Patel 3cef5673ff Merge branch 'refactor/enable_fsm_and_riscv_ulp_simultaneously' into 'master'
refactor(ulp): Allow both ULP-FSM and ULP-RISCV to enable at build time

Closes IDFGH-11916

See merge request espressif/esp-idf!45751
2026-03-17 19:29:43 +05:30
..
2026-03-16 13:45:26 +08:00
2026-03-12 12:02:10 +01:00

Supported Targets ESP32 ESP32-C2 ESP32-C3 ESP32-C5 ESP32-C6 ESP32-C61 ESP32-H2 ESP32-H21 ESP32-H4 ESP32-P4 ESP32-S2 ESP32-S3 ESP32-S31

System Examples

Configuration and management of memory, interrupts, WDT (watchdog timer), OTA (over the air updates), deep sleep logging, and event loops.

See the README.md file in the upper level examples directory for more information about examples.