Files
esp-idf/examples/system
Meet Patel a3f167f1c4 refactor(ulp): Allow both ULP-FSM and ULP-RISCV to enable at build time
Updated kconfig option type and other supporting changes in build system
to allow enabling both ULP FSM and ULP RISCV simultaneously. Users can
choose at run time which one to initialize and use.
NOTE: Both ULP FSM and ULP RISCV can't be used simultaneously at run
time because they share some common hardware like RTC slow memory space.

Closes https://github.com/espressif/esp-idf/issues/12999
2026-03-15 14:01:30 +05:30
..
2026-03-12 12:02:11 +01:00
2026-03-12 12:02:10 +01:00

Supported Targets ESP32 ESP32-C2 ESP32-C3 ESP32-C5 ESP32-C6 ESP32-C61 ESP32-H2 ESP32-H21 ESP32-H4 ESP32-P4 ESP32-S2 ESP32-S3 ESP32-S31

System Examples

Configuration and management of memory, interrupts, WDT (watchdog timer), OTA (over the air updates), deep sleep logging, and event loops.

See the README.md file in the upper level examples directory for more information about examples.