examples: Build and pytest failure fixes for the submodule update

- Fixed the h2 pytest failure by adding the timedInteractionTimeoutMs in the activedataset command
  since spec mandates a timed interaction.
- Fixed the external platform build failure.

examples/common/blemesh_platform/platform/ESP32_custom/BUILD.gn

@@ -46,7 +46,6 @@ declare_args() {
   chip_max_discovered_ip_addresses = 5
   chip_use_secure_cert_dac_provider = false
   chip_use_esp32_ecdsa_peripheral = false
-  chip_enable_ethernet = false
   chip_enable_route_hook = false
   chip_memory_alloc_mode = "default"
 }

examples/common/external_platform/BUILD.gn

@@ -39,7 +39,6 @@ declare_args() {
   chip_config_software_version_number = 0
   chip_enable_chipoble = false
   chip_enable_ble_controller = false
-  chip_enable_ethernet = false
   chip_bt_nimble_enabled = false
   chip_bt_bluedroid_enabled = false
   chip_max_discovered_ip_addresses = 5

examples/light/sdkconfig.defaults

@@ -137,3 +137,6 @@ CONFIG_SUPPORT_ELECTRICAL_GRID_CONDITIONS_CLUSTER=n
 CONFIG_SUPPORT_COMMODITY_PRICE_CLUSTER=n
 CONFIG_SUPPORT_METER_IDENTIFICATION_CLUSTER=n
 CONFIG_SUPPORT_UNIT_LOCALIZATION_CLUSTER=n
+CONFIG_SUPPORT_COMMODITY_METERING_CLUSTER=n
+CONFIG_SUPPORT_COMMODITY_TARIFF_CLUSTER=n
+CONFIG_SUPPORT_PUSH_AV_STREAM_TRANSPORT_CLUSTER=n

examples/pytest_esp_matter_light.py

@@ -271,7 +271,7 @@ def test_matter_commissioning_h2(dut:Tuple[Dut, Dut]) -> None:
     if len(result) != 0:
       assert False
     time.sleep(2)
-    command = CHIP_TOOL_EXE + ' threadborderroutermanagement set-active-dataset-request hex:' + OT_DATASET_HEXSTR + ' 1 1'
+    command = CHIP_TOOL_EXE + ' threadborderroutermanagement set-active-dataset-request hex:' + OT_DATASET_HEXSTR + ' 1 1 --timedInteractionTimeoutMs 2000'
     out_str = subprocess.getoutput(command)
     print(out_str)
     result = re.findall(r'Run command failure', str(out_str))

tools/ci/extended_color_light_wifi_pics_code.txt

@@ -37,6 +37,8 @@ CADMIN.M.UserInterfaceDisplay=0
 CADMIN.M.AudioInterface=0
 MCORE.DT_SW_COMP=0
 MCORE.COM.BLE=1
+MCORE.COM.WIFI_2P4GHZ=1
+MCORE.COM.WIFI_5GHZ=0
 MCORE.COM.WIFI=1
 MCORE.COM.ETH=0
 MCORE.COM.THR=0
@@ -327,6 +329,88 @@ CNET.C.C08.Tx=0
 CNET.C.F00=0
 CNET.C.F01=0
 CNET.C.F02=0
+OPCREDS.S=1
+OPCREDS.C=0
+OPCREDS.S.A0000=1
+OPCREDS.S.A0001=1
+OPCREDS.S.A0002=1
+OPCREDS.S.A0003=1
+OPCREDS.S.A0004=1
+OPCREDS.S.A0005=1
+OPCREDS.S.C01.Tx=1
+OPCREDS.S.C03.Tx=1
+OPCREDS.S.C05.Tx=1
+OPCREDS.S.C08.Tx=1
+OPCREDS.S.C0e.Tx=1
+OPCREDS.S.C00.Rsp=1
+OPCREDS.S.C02.Rsp=1
+OPCREDS.S.C04.Rsp=1
+OPCREDS.S.C06.Rsp=1
+OPCREDS.S.C07.Rsp=1
+OPCREDS.S.C09.Rsp=1
+OPCREDS.S.C0a.Rsp=1
+OPCREDS.S.C0b.Rsp=1
+OPCREDS.S.C0c.Rsp=1
+OPCREDS.S.C0d.Rsp=1
+OPCREDS.C.A0000=0
+OPCREDS.C.A0001=0
+OPCREDS.C.A0002=0
+OPCREDS.C.A0003=0
+OPCREDS.C.A0004=0
+OPCREDS.C.A0005=0
+OPCREDS.C.C00.Tx=0
+OPCREDS.C.C02.Tx=0
+OPCREDS.C.C04.Tx=0
+OPCREDS.C.C06.Tx=0
+OPCREDS.C.C07.Tx=0
+OPCREDS.C.C09.Tx=0
+OPCREDS.C.C0a.Tx=0
+OPCREDS.C.C0b.Tx=0
+OPCREDS.C.C01.Rsp=0
+OPCREDS.C.C03.Rsp=0
+OPCREDS.C.C05.Rsp=0
+OPCREDS.C.C08.Rsp=0
+OTAP.S.M.DelayedActionTime=0
+OTAP.S.M.UserConsentNeeded=0
+OTAR.C.M.AnnounceOTAProvider=0
+OTAR.C.M.NotifyUpdateApplied=1
+I.S=1
+I.C=0
+I.S.A0000=1
+I.S.A0001=1
+I.S.C00.Rsp=1
+I.S.C40.Rsp=1
+I.C.C00.Tx=0
+I.C.C40.Tx=0
+LVL.S=1
+LVL.C=0
+LVL.S.A0000=1
+LVL.S.A0001=1
+LVL.S.A0002=1
+LVL.S.A0003=1
+LVL.S.A0004=0
+LVL.S.A0005=0
+LVL.S.A0006=0
+LVL.S.A000f=1
+LVL.S.A0010=0
+LVL.S.A0011=1
+LVL.S.A0012=0
+LVL.S.A0013=0
+LVL.S.A0014=0
+LVL.S.A4000=1
+LVL.S.C00.Rsp=1
+LVL.S.C01.Rsp=1
+LVL.S.C02.Rsp=1
+LVL.S.C03.Rsp=1
+LVL.S.C04.Rsp=1
+LVL.S.C05.Rsp=1
+LVL.S.C06.Rsp=1
+LVL.S.C07.Rsp=1
+LVL.S.C08.Rsp=0
+LVL.S.F00=1
+LVL.S.F01=1
+LVL.S.F02=0
+LVL.S.M.VarRate=0
 CC.S=1
 CC.C=0
 CC.S.A0000=0
@@ -501,43 +585,6 @@ G.C.C02.Tx=0
 G.C.C03.Tx=0
 G.C.C04.Tx=0
 G.C.C05.Tx=0
-I.S=1
-I.C=0
-I.S.A0000=1
-I.S.A0001=1
-I.S.C00.Rsp=1
-I.S.C40.Rsp=1
-I.C.C00.Tx=0
-I.C.C40.Tx=0
-LVL.S=1
-LVL.C=0
-LVL.S.A0000=1
-LVL.S.A0001=1
-LVL.S.A0002=1
-LVL.S.A0003=1
-LVL.S.A0004=0
-LVL.S.A0005=0
-LVL.S.A0006=0
-LVL.S.A000f=1
-LVL.S.A0010=0
-LVL.S.A0011=1
-LVL.S.A0012=0
-LVL.S.A0013=0
-LVL.S.A0014=0
-LVL.S.A4000=1
-LVL.S.C00.Rsp=1
-LVL.S.C01.Rsp=1
-LVL.S.C02.Rsp=1
-LVL.S.C03.Rsp=1
-LVL.S.C04.Rsp=1
-LVL.S.C05.Rsp=1
-LVL.S.C06.Rsp=1
-LVL.S.C07.Rsp=1
-LVL.S.C08.Rsp=0
-LVL.S.F00=1
-LVL.S.F01=1
-LVL.S.F02=0
-LVL.S.M.VarRate=0
 OO.S=1
 OO.C=0
 OO.S.A0000=1