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Merge branch 'fix/spi_master_set_idle_data_pin' into 'master'

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fix(driver_spi): spi master set idle level for all data pin

See merge request espressif/esp-idf!44831
This commit is contained in:
Wan Lei
2026-01-09 11:03:00 +08:00
parent 3a62fdba66 2261e92dd6
commit 1b82e01144
17 changed files with 111 additions and 82 deletions
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components/esp_driver_spi/include/esp_private/spi_common_internal.h
+3 -5
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2010-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,16 +9,14 @@
#pragma once
#include <esp_intr_alloc.h>
#include "esp_pm.h"
#include "driver/spi_common.h"
#include "hal/spi_types.h"
#include "hal/dma_types.h"
#include "soc/ext_mem_defs.h" //for SOC_NON_CACHEABLE_OFFSET
#include "esp_private/spi_dma.h"
#include "esp_pm.h"
#include "esp_private/spi_share_hw_ctrl.h"
#if SOC_GDMA_SUPPORTED
#include "esp_private/gdma.h"
#endif
#include "esp_private/spi_share_hw_ctrl.h"
#ifdef __cplusplus
extern "C"
components/esp_driver_spi/src/gpspi/spi_master.c
+1 -1
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@@ -337,7 +337,7 @@ static esp_err_t spi_master_init_driver(spi_host_device_t host_id)
}
spi_hal_init(&host->hal, host_id);
spi_hal_config_io_default_level(&host->hal, bus_attr->bus_cfg.data_io_default_level);
spi_hal_set_data_pin_idle_level(&host->hal, bus_attr->bus_cfg.data_io_default_level);
if (host_id != SPI1_HOST) {
//SPI1 attributes are already initialized at start up.
components/esp_hal_gpspi/esp32c2/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -246,13 +246,16 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**
components/esp_hal_gpspi/esp32c3/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -251,13 +251,16 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**
components/esp_hal_gpspi/esp32c5/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -900,13 +900,16 @@ static inline void spi_ll_master_set_cs_setup(spi_dev_t *hw, uint8_t setup)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/*------------------------------------------------------------------------------
components/esp_hal_gpspi/esp32c6/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -236,13 +236,16 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**
components/esp_hal_gpspi/esp32c61/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -262,13 +262,16 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**
components/esp_hal_gpspi/esp32h2/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -237,13 +237,16 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**
components/esp_hal_gpspi/esp32h21/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -225,13 +225,16 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**
components/esp_hal_gpspi/esp32h4/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -284,13 +284,16 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**
components/esp_hal_gpspi/esp32p4/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -931,13 +931,16 @@ static inline void spi_ll_set_mosi_delay(spi_dev_t *hw, int delay_mode, int dela
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**
components/esp_hal_gpspi/esp32s2/include/hal/spi_ll.h
+5 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -270,13 +270,14 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
}
/**
components/esp_hal_gpspi/esp32s3/include/hal/spi_ll.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -262,13 +262,16 @@ static inline void spi_ll_slave_hd_init(spi_dev_t *hw)
}
/**
* Determine and unify the default level of mosi line when bus free
* Determine and unify the default level of data line when bus idle
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_set_mosi_free_level(spi_dev_t *hw, bool level)
static inline void spi_ll_set_data_pin_idle_level(spi_dev_t *hw, bool level)
{
hw->ctrl.d_pol = level; //set default level for MOSI only on IDLE state
hw->ctrl.d_pol = level;
hw->ctrl.q_pol = level;
hw->ctrl.wp_pol = level;
hw->ctrl.hold_pol = level;
}
/**
components/esp_hal_gpspi/include/hal/spi_hal.h
+2 -2
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@@ -163,12 +163,12 @@ typedef struct {
void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id);
/**
* Config default output IO level when don't have transaction
* Config default output data IO level when bus idle
*
* @param hal Context of the HAL layer.
* @param level IO level to config
*/
void spi_hal_config_io_default_level(spi_hal_context_t *hal, bool level);
void spi_hal_set_data_pin_idle_level(spi_hal_context_t *hal, bool level);
/**
* Deinit the peripheral (and the context if needed).
components/esp_hal_gpspi/spi_hal.c
+2 -2
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@@ -27,11 +27,11 @@ void spi_hal_init(spi_hal_context_t *hal, uint32_t host_id)
spi_ll_apply_config(hw);
}
void spi_hal_config_io_default_level(spi_hal_context_t *hal, bool level)
void spi_hal_set_data_pin_idle_level(spi_hal_context_t *hal, bool level)
{
#if SPI_LL_MOSI_FREE_LEVEL
// Config default output data line level when don't have transaction
spi_ll_set_mosi_free_level(hal->hw, level);
spi_ll_set_data_pin_idle_level(hal->hw, level);
spi_ll_apply_config(hal->hw);
#endif
}
components/esp_hal_i2s/esp32c5/include/hal/i2s_ll.h
+14 -14
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -792,6 +792,19 @@ static inline void i2s_ll_tx_enable_pdm(i2s_dev_t *hw, bool pcm2pdm_en)
hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = pcm2pdm_en;
}
/**
* @brief Enable I2S RX PDM mode
*
* @param hw Peripheral I2S hardware instance address.
* @param pdm2pcm_en Set true to enable RX PDM to PCM filter
*/
static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm2pcm_en)
{
(void)pdm2pcm_en;
hw->rx_conf.rx_pdm_en = true;
hw->rx_conf.rx_tdm_en = false;
}
/**
* @brief Set I2S TX PDM prescale
*
@@ -951,19 +964,6 @@ static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw)
return hw->tx_pcm2pdm_conf1.tx_pdm_fs;
}
/**
* @brief Enable RX PDM mode.
*
* @param hw Peripheral I2S hardware instance address.
* @param pdm_enable Set true to RX enable PDM mode (ignored)
*/
static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm_enable)
{
(void)pdm_enable;
hw->rx_conf.rx_pdm_en = 0;
hw->rx_conf.rx_tdm_en = 1;
}
/**
* @brief Configura TX a/u-law decompress or compress
*
components/esp_hal_i2s/esp32c61/include/hal/i2s_ll.h
+14 -14
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -793,6 +793,19 @@ static inline void i2s_ll_tx_enable_pdm(i2s_dev_t *hw, bool pcm2pdm_en)
hw->tx_pcm2pdm_conf.pcm2pdm_conv_en = pcm2pdm_en;
}
/**
* @brief Enable I2S RX PDM mode
*
* @param hw Peripheral I2S hardware instance address.
* @param pdm2pcm_en Set true to enable RX PDM to PCM filter
*/
static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm2pcm_en)
{
(void)pdm2pcm_en;
hw->rx_conf.rx_pdm_en = true;
hw->rx_conf.rx_tdm_en = false;
}
/**
* @brief Set I2S TX PDM prescale
*
@@ -952,19 +965,6 @@ static inline uint32_t i2s_ll_tx_get_pdm_fs(i2s_dev_t *hw)
return hw->tx_pcm2pdm_conf1.tx_pdm_fs;
}
/**
* @brief Enable RX PDM mode.
*
* @param hw Peripheral I2S hardware instance address.
* @param pdm2pcm Set true to RX enable PDM mode (ignored)
*/
static inline void i2s_ll_rx_enable_pdm(i2s_dev_t *hw, bool pdm2pcm)
{
(void)pdm2pcm;
hw->rx_conf.rx_pdm_en = 0;
hw->rx_conf.rx_tdm_en = 1;
}
/**
* @brief Configura TX a/u-law decompress or compress
*