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Merge branch 'feat/dedic_gpio_s31' into 'master'

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feat(gpio): support dedicated gpio for s31

Closes IDF-14782

See merge request espressif/esp-idf!45093
This commit is contained in:
morris
2026-01-16 11:11:22 +08:00
parent 9cfad4f566 a8ef2b0c0c
commit 5fe2a941f5
9 changed files with 142 additions and 9 deletions
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components/esp_driver_gpio/test_apps/gpio_extensions/README.md
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| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
components/esp_hal_gpio/esp32s31/dedic_gpio_periph.c
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/gpio_sig_map.h"
#include "hal/dedic_gpio_periph.h"
const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
.irq = -1,
.cores = {
[0] = {
.in_sig_per_channel = {
[0] = CORE_GPIO_IN_PAD_IN0_IDX,
[1] = CORE_GPIO_IN_PAD_IN1_IDX,
[2] = CORE_GPIO_IN_PAD_IN2_IDX,
[3] = CORE_GPIO_IN_PAD_IN3_IDX,
[4] = CORE_GPIO_IN_PAD_IN4_IDX,
[5] = CORE_GPIO_IN_PAD_IN5_IDX,
[6] = CORE_GPIO_IN_PAD_IN6_IDX,
[7] = CORE_GPIO_IN_PAD_IN7_IDX,
},
.out_sig_per_channel = {
[0] = CORE_GPIO_OUT_PAD_OUT0_IDX,
[1] = CORE_GPIO_OUT_PAD_OUT1_IDX,
[2] = CORE_GPIO_OUT_PAD_OUT2_IDX,
[3] = CORE_GPIO_OUT_PAD_OUT3_IDX,
[4] = CORE_GPIO_OUT_PAD_OUT4_IDX,
[5] = CORE_GPIO_OUT_PAD_OUT5_IDX,
[6] = CORE_GPIO_OUT_PAD_OUT6_IDX,
[7] = CORE_GPIO_OUT_PAD_OUT7_IDX,
}
},
[1] = {
.in_sig_per_channel = {
[0] = CORE_GPIO_IN_PAD_IN8_IDX,
[1] = CORE_GPIO_IN_PAD_IN9_IDX,
[2] = CORE_GPIO_IN_PAD_IN10_IDX,
[3] = CORE_GPIO_IN_PAD_IN11_IDX,
[4] = CORE_GPIO_IN_PAD_IN12_IDX,
[5] = CORE_GPIO_IN_PAD_IN13_IDX,
[6] = CORE_GPIO_IN_PAD_IN14_IDX,
[7] = CORE_GPIO_IN_PAD_IN15_IDX,
},
.out_sig_per_channel = {
[0] = CORE_GPIO_OUT_PAD_OUT8_IDX,
[1] = CORE_GPIO_OUT_PAD_OUT9_IDX,
[2] = CORE_GPIO_OUT_PAD_OUT10_IDX,
[3] = CORE_GPIO_OUT_PAD_OUT11_IDX,
[4] = CORE_GPIO_OUT_PAD_OUT12_IDX,
[5] = CORE_GPIO_OUT_PAD_OUT13_IDX,
[6] = CORE_GPIO_OUT_PAD_OUT14_IDX,
[7] = CORE_GPIO_OUT_PAD_OUT15_IDX,
}
},
},
};
components/esp_hal_gpio/esp32s31/include/hal/dedic_gpio_caps.h
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#define DEDIC_GPIO_CAPS_GET(_attr) _DEDIC_GPIO_ ## _attr
#define _DEDIC_GPIO_OUT_CHANS_PER_CPU 8 /*!< 8 outward channels on each CPU core */
#define _DEDIC_GPIO_IN_CHANS_PER_CPU 8 /*!< 8 inward channels on each CPU core */
/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
#define _DEDIC_GPIO_CPU_PERIPH_ALWAYS_ENABLE 1
components/esp_hal_gpio/esp32s31/include/hal/dedic_gpio_cpu_ll.h
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/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#include "riscv/csr.h"
/*fast gpio*/
#define CSR_GPIO_OEN_USER 0x803
#define CSR_GPIO_IN_USER 0x804
#define CSR_GPIO_OUT_USER 0x805
#ifdef __cplusplus
extern "C" {
#endif
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
{
// the OEN register is active low
RV_CLEAR_CSR(CSR_GPIO_OEN_USER, mask);
}
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
{
RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
}
__attribute__((always_inline))
static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
{
uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
return value;
}
__attribute__((always_inline))
static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
{
uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
return value;
}
__attribute__((always_inline))
static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
{
RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value));
}
#ifdef __cplusplus
}
#endif
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
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# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_DEDICATED_GPIO_SUPPORTED
bool
default y
config SOC_UART_SUPPORTED
bool
default y
components/soc/esp32s31/include/soc/soc_caps.h
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/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32S31] IDF-14741
// #define SOC_ANA_CMPR_SUPPORTED 1 // TODO: [ESP32S31] IDF-14787
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32S31] IDF-14782
#define SOC_DEDICATED_GPIO_SUPPORTED 1
#define SOC_UART_SUPPORTED 1 // TODO: [ESP32S31] IDF-14789
#define SOC_GDMA_SUPPORTED 1
// #define SOC_UHCI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14791
examples/peripherals/dedicated_gpio/soft_i2c/README.md
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| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
# Example: Software I2C Master via Dedicated/Fast GPIOs
examples/peripherals/dedicated_gpio/soft_spi/README.md
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| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | --------- |
# Example: SPI software emulation using dedicated/fast GPIOs
examples/peripherals/dedicated_gpio/soft_uart/README.md
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| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
# Example: UART software emulation using dedicated/fast GPIOs