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fix(esp_system): fix rom secure boot fast wake feature for c5/c6/h2/h21

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This commit is contained in:
wuzhenghui
2025-12-08 17:06:17 +08:00
parent bb1bf75a83
commit 67a62f45ce
15 changed files with 97 additions and 10 deletions
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components/bootloader/subproject/main/bootloader_start.c
+2
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@@ -4,8 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdbool.h>
#include "sdkconfig.h"
#include "esp_log.h"
#include "esp_rom_sys.h"
#include "esp_rom_caps.h"
#include "bootloader_init.h"
#include "bootloader_utility.h"
#include "bootloader_common.h"
components/bootloader_support/src/bootloader_common_loader.c
+9 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,6 +12,9 @@
#include "esp_rom_crc.h"
#include "esp_rom_gpio.h"
#include "esp_flash_partitions.h"
#if CONFIG_SECURE_BOOT
#include "esp_secure_boot.h"
#endif
#include "bootloader_flash.h"
#include "bootloader_common.h"
#include "soc/gpio_periph.h"
@@ -274,7 +277,12 @@ rtc_retain_mem_t* bootloader_common_get_rtc_retain_mem(void)
#define RETAIN_MEM_SIZE ALIGN_UP(sizeof(rtc_retain_mem_t), 8)
#define RTC_RETAIN_MEM_ADDR (SOC_RTC_DRAM_HIGH - RETAIN_MEM_SIZE)
#endif //ESP_ROM_HAS_LP_ROM
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR - ESP_SECURE_BOOT_DIGEST_LEN;
#else
static rtc_retain_mem_t *const s_bootloader_retain_mem = (rtc_retain_mem_t *)RTC_RETAIN_MEM_ADDR;
#endif
return s_bootloader_retain_mem;
#else
static __attribute__((section(".bootloader_data_rtc_mem"))) rtc_retain_mem_t s_bootloader_retain_mem;
components/esp_rom/esp32c5/Kconfig.soc_caps.in
+4
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@@ -122,3 +122,7 @@ config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
config ESP_ROM_DELAY_US_PATCH
bool
default y
config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
bool
default y
components/esp_rom/esp32c5/esp_rom_caps.h
+1
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@@ -36,3 +36,4 @@
#define ESP_ROM_CLIC_INT_THRESH_PATCH (1) // ROM version of esprv_intc_int_set_threshold incorrectly assumes lowest MINTTHRESH is 0x1F, should be 0xF
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_DELAY_US_PATCH (1) // ROM ets_delay_us needs patch for U-mode operation
#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
components/esp_rom/esp32c6/Kconfig.soc_caps.in
+4
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@@ -126,3 +126,7 @@ config ESP_ROM_NO_USB_SERIAL_OUTPUT_API
config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
bool
default y
config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
bool
default y
components/esp_rom/esp32c6/esp_rom_caps.h
+1
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@@ -37,3 +37,4 @@
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_NO_USB_SERIAL_OUTPUT_API (1) // ROM does not export the usb-serial-jtag write char function
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
components/esp_rom/esp32h2/Kconfig.soc_caps.in
+4
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@@ -118,3 +118,7 @@ config ESP_ROM_NO_USB_SERIAL_OUTPUT_API
config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
bool
default y
config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
bool
default y
components/esp_rom/esp32h2/esp_rom_caps.h
+1
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@@ -35,3 +35,4 @@
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_NO_USB_SERIAL_OUTPUT_API (1) // ROM does not export the usb-serial-jtag write char function
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
components/esp_rom/esp32h21/Kconfig.soc_caps.in
+4
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@@ -98,3 +98,7 @@ config ESP_ROM_HAS_OUTPUT_PUTC_FUNC
config ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY
bool
default y
config ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
bool
default y
components/esp_rom/esp32h21/esp_rom_caps.h
+1
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@@ -31,3 +31,4 @@
// #define ESP_ROM_SUPPORT_DEEP_SLEEP_WAKEUP_STUB (1) // ROM supports the HP core to jump to the RTC memory to execute stub code after waking up from deepsleep. //TODO: [ESP32H21] IDF-11515
#define ESP_ROM_HAS_OUTPUT_PUTC_FUNC (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
#define ESP_ROM_HAS_SUBOPTIMAL_NEWLIB_ON_MISALIGNED_MEMORY (1) // ROM mem/str functions are not optimized well for misaligned memory access.
#define ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP (1) // ROM supports the secure boot fast wakeup feature
components/esp_system/ld/ld.common
+9
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@@ -11,6 +11,13 @@
/* CPU instruction prefetch padding size for flash mmap scenario */
#define _esp_flash_mmap_prefetch_pad_size 16
/* Copy from esp_secure_boot.h */
#ifdef CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
/*
* PMP region granularity size
* Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones
@@ -70,6 +77,8 @@
has the required alignment */
#define ULP_ALIGNMENT_REQ_BYTES 256
#define RESERVE_RTC_MEM ALIGN_UP(ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC, ULP_ALIGNMENT_REQ_BYTES)
#elif CONFIG_SECURE_BOOT && CONFIG_ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC + ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC)
#endif
components/heap/port/esp32c5/memory_layout.c
+15 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +11,7 @@
#include "soc/soc.h"
#include "heap_memory_layout.h"
#include "esp_heap_caps.h"
#include "esp_rom_caps.h"
#if CONFIG_SECURE_ENABLE_TEE
#define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW)
@@ -73,6 +74,18 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
*/
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH)
#endif
const soc_memory_region_t soc_memory_regions[] = {
#if CONFIG_SPIRAM
{ SOC_EXTRAM_DATA_LOW, (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW), SOC_MEMORY_TYPE_SPIRAM, 0, false}, //SPI SRAM, if available
@@ -80,7 +93,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ SOC_DIRAM_DRAM_LOW, (APP_USABLE_DRAM_END - SOC_DIRAM_DRAM_LOW), SOC_MEMORY_TYPE_RAM, SOC_DIRAM_IRAM_LOW, false}, //D/IRAM, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM, can be used as trace memory (ROM reserved area)
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ SOC_RTC_DATA_LOW, (SOC_RTC_DATA_HIGH - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
{ SOC_RTC_DATA_LOW, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
#endif
};
components/heap/port/esp32c6/memory_layout.c
+14 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +11,7 @@
#include "soc/soc.h"
#include "heap_memory_layout.h"
#include "esp_heap_caps.h"
#include "esp_rom_caps.h"
#if CONFIG_SECURE_ENABLE_TEE
#define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW)
@@ -71,6 +72,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
*/
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH)
#endif
const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level0, can be used as trace memory
{ 0x40820000, 0x20000, SOC_MEMORY_TYPE_RAM, 0x40820000, false}, //D/IRAM level1, can be used as trace memory
@@ -78,7 +90,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ 0x40860000, (APP_USABLE_DRAM_END-0x40860000), SOC_MEMORY_TYPE_RAM, 0x40860000, false}, //D/IRAM level3, can be used as trace memory
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level3, can be used as trace memory (ROM reserved area)
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x4000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
{ 0x50000000, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW), SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
#endif
};
components/heap/port/esp32h2/memory_layout.c
+14 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,6 +11,7 @@
#include "soc/soc.h"
#include "heap_memory_layout.h"
#include "esp_heap_caps.h"
#include "esp_rom_caps.h"
#if CONFIG_SECURE_ENABLE_TEE
#define SRAM_DIRAM_TEE_ORG (SOC_DIRAM_IRAM_LOW)
@@ -69,6 +70,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
*/
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH)
#endif
const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level 0
{ 0x40810000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40810000, false}, //D/IRAM level 1
@@ -77,7 +89,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level 4
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level 4
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
{ 0x50000000, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW),SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
#endif
};
components/heap/port/esp32h21/memory_layout.c
+14 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,7 +11,7 @@
#include "soc/soc.h"
#include "heap_memory_layout.h"
#include "esp_heap_caps.h"
#include "esp_rom_caps.h"
/**
* @brief Memory type descriptors. These describe the capabilities of a type of memory in the SoC.
@@ -65,6 +65,17 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
*/
#define APP_USABLE_DRAM_END (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
#if CONFIG_SECURE_BOOT && ESP_ROM_SUPPORT_SECURE_BOOT_FAST_WAKEUP
#if CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS
#define ESP_SECURE_BOOT_DIGEST_LEN 48
#else /* !CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define ESP_SECURE_BOOT_DIGEST_LEN 32
#endif /* CONFIG_SECURE_BOOT_ECDSA_KEY_LEN_384_BITS */
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH - ESP_SECURE_BOOT_DIGEST_LEN)
#else
#define APP_USABLE_RTC_MEM_END (SOC_RTC_DATA_HIGH)
#endif
const soc_memory_region_t soc_memory_regions[] = {
{ 0x40800000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40800000, false}, //D/IRAM level 0
{ 0x40810000, 0x10000, SOC_MEMORY_TYPE_RAM, 0x40810000, false}, //D/IRAM level 1
@@ -73,7 +84,7 @@ const soc_memory_region_t soc_memory_regions[] = {
{ 0x40840000, APP_USABLE_DRAM_END-0x40840000, SOC_MEMORY_TYPE_RAM, 0x40840000, false}, //D/IRAM level 4
{ APP_USABLE_DRAM_END, (SOC_DIRAM_DRAM_HIGH-APP_USABLE_DRAM_END), SOC_MEMORY_TYPE_RAM, APP_USABLE_DRAM_END, true}, //D/IRAM level 4
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50000000, 0x1000, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
{ 0x50000000, (APP_USABLE_RTC_MEM_END - SOC_RTC_DATA_LOW),SOC_MEMORY_TYPE_RTCRAM, 0, false}, //Fast RTC memory
#endif
};