mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 11:03:11 +00:00
Merge branch 'feature/esp32s31_regi2c_support' into 'master'
feat(regi2c): add support for ESP32S31 Closes IDF-14680 See merge request espressif/esp-idf!46469
This commit is contained in:
Song Ruo Jing
@@ -23,9 +23,27 @@
|
||||
#include "soc/rtc_wdt_reg.h"
|
||||
#include "hal/rwdt_ll.h"
|
||||
#endif
|
||||
#include "soc/pmu_reg.h"
|
||||
#include "hal/regi2c_ctrl_ll.h"
|
||||
#include "hal/modem_lpcon_ll.h"
|
||||
|
||||
ESP_LOG_ATTR_TAG(TAG, "boot.esp32s31");
|
||||
|
||||
static inline void bootloader_hardware_init(void)
|
||||
{
|
||||
/* Disable RF pll by default */
|
||||
REG_SET_FIELD(PMU_RF_PWC_REG, PMU_XPD_RF_CIRCUIT, 0xFFFF);
|
||||
|
||||
modem_lpcon_ll_enable_bus_clock(true);
|
||||
|
||||
#if !CONFIG_IDF_ENV_FPGA || SOC_REGI2C_SUPPORTED
|
||||
/* Enable analog i2c master clock */
|
||||
_regi2c_ctrl_ll_master_enable_clock(true); // keep ana i2c mst clock always enabled in bootloader
|
||||
regi2c_ctrl_ll_master_force_enable_clock(true); // TODO: IDF-14678 Remove this?
|
||||
regi2c_ctrl_ll_master_configure_clock();
|
||||
#endif
|
||||
}
|
||||
|
||||
#if SOC_RTC_WDT_SUPPORTED
|
||||
static void bootloader_super_wdt_auto_feed(void)
|
||||
{
|
||||
@@ -39,7 +57,7 @@ esp_err_t bootloader_init(void)
|
||||
{
|
||||
esp_err_t ret = ESP_OK;
|
||||
|
||||
// bootloader_hardware_init(); // TODO: IDF-14696
|
||||
bootloader_hardware_init(); // TODO: IDF-14696
|
||||
#if SOC_RTC_WDT_SUPPORTED
|
||||
bootloader_super_wdt_auto_feed();
|
||||
#endif
|
||||
|
||||
@@ -10,20 +10,25 @@
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/pmu_reg.h"
|
||||
#include "modem/modem_lpcon_struct.h"
|
||||
#include "modem/modem_syscon_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define ANA_I2C_MST_CLK_HAS_ROOT_GATING 1 /*!< Any regi2c operation needs enable the analog i2c master clock first */
|
||||
|
||||
/**
|
||||
* @brief Enable analog I2C master clock
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_clock(bool en)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14680
|
||||
MODEM_LPCON.clk_conf.clk_i2c_mst_en = en;
|
||||
}
|
||||
|
||||
// LPPERI.clk_en is a shared register, so this function must be used in an atomic way
|
||||
// use a macro to wrap the function, force the caller to use it in a critical section
|
||||
// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
|
||||
#define regi2c_ctrl_ll_master_enable_clock(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_enable_clock(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
@@ -31,7 +36,7 @@ static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_enable_
|
||||
*/
|
||||
static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock_enabled(void)
|
||||
{
|
||||
return 0;// TODO: [ESP32S31] IDF-14680
|
||||
return MODEM_LPCON.clk_conf.clk_i2c_mst_en;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -39,18 +44,27 @@ static inline __attribute__((always_inline)) bool regi2c_ctrl_ll_master_is_clock
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void _regi2c_ctrl_ll_master_reset(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14680
|
||||
MODEM_LPCON.rst_conf.rst_i2c_mst = 1;
|
||||
MODEM_LPCON.rst_conf.rst_i2c_mst = 0;
|
||||
}
|
||||
|
||||
// LPPERI.reset_en is a shared register, so this function must be used in an atomic way
|
||||
#define regi2c_ctrl_ll_master_reset(...) (void)__DECLARE_RCC_RC_ATOMIC_ENV; _regi2c_ctrl_ll_master_reset(__VA_ARGS__)
|
||||
|
||||
/**
|
||||
* @brief Force enable analog I2C master clock
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_force_enable_clock(bool en)
|
||||
{
|
||||
MODEM_LPCON.clk_conf_force_on.clk_i2c_mst_fo = en;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure analog I2C master clock
|
||||
*/
|
||||
static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configure_clock(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14680
|
||||
MODEM_SYSCON.clk_conf.clk_i2c_mst_sel_160m = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -58,7 +72,9 @@ static inline __attribute__((always_inline)) void regi2c_ctrl_ll_master_configur
|
||||
*/
|
||||
static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14680
|
||||
// TODO: IDF-14632, IDF-14744
|
||||
SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C);
|
||||
SET_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_RSTB_PERIF_I2C);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -66,7 +82,8 @@ static inline void regi2c_ctrl_ll_i2c_sar_periph_enable(void)
|
||||
*/
|
||||
static inline void regi2c_ctrl_ll_i2c_sar_periph_disable(void)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14680
|
||||
// TODO: IDF-14632, IDF-14744
|
||||
CLEAR_PERI_REG_MASK(PMU_ANA_PERI_PWR_CTRL_REG, PMU_XPD_PERIF_I2C);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@@ -5,25 +5,153 @@
|
||||
*/
|
||||
#include "hal/regi2c_impl.h"
|
||||
#include "hal/assert.h"
|
||||
#include "modem/i2c_ana_mst_reg.h"
|
||||
#include "hal/regi2c_ctrl_ll.h"
|
||||
#include "hal/config.h"
|
||||
|
||||
/* SLAVE */
|
||||
#define REGI2C_BB (0X67)
|
||||
#define REGI2C_TXRF (0X6B)
|
||||
#define REGI2C_SDM (0X63)
|
||||
#define REGI2C_RFPLL (0X62)
|
||||
#define REGI2C_BIAS (0X6A)
|
||||
#define REGI2C_BBPLL (0x66)
|
||||
#define REGI2C_ULP (0x61)
|
||||
#define REGI2C_SAR_MASTER (0X10)
|
||||
#define REGI2C_SAR_SLAVE (0X11)
|
||||
#define REGI2C_PERIF (0X69)
|
||||
#define REGI2C_APLL (0X0C)
|
||||
#define REGI2C_CPLL (0X0A)
|
||||
#define REGI2C_MPLL (0X0B)
|
||||
#define REGI2C_DIG_REG (0X6D)
|
||||
/* SLAVE END */
|
||||
|
||||
static uint8_t regi2c_enable_block(uint8_t block)
|
||||
{
|
||||
#if !HAL_CONFIG(ENV_FPGA) // on FPGA, unable to manipulate modem registers, skip the check
|
||||
HAL_ASSERT(regi2c_ctrl_ll_master_is_clock_enabled());
|
||||
#endif
|
||||
|
||||
/* Before config I2C register, enable corresponding slave. */
|
||||
uint16_t bit_mask = 0;
|
||||
switch (block) {
|
||||
case REGI2C_BB:
|
||||
bit_mask = REGI2C_BB_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_TXRF:
|
||||
bit_mask = REGI2C_TXRF_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_SDM:
|
||||
bit_mask = REGI2C_SDM_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_RFPLL:
|
||||
bit_mask = REGI2C_RFPLL_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_BIAS:
|
||||
bit_mask = REGI2C_BIAS_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_BBPLL:
|
||||
bit_mask = REGI2C_BBPLL_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_ULP:
|
||||
bit_mask = REGI2C_ULP_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_SAR_MASTER:
|
||||
bit_mask = REGI2C_SAR_MASTER_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_SAR_SLAVE:
|
||||
bit_mask = REGI2C_SAR_SLAVE_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_PERIF:
|
||||
bit_mask = REGI2C_PERIF_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_APLL:
|
||||
bit_mask = REGI2C_APLL_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_CPLL:
|
||||
bit_mask = REGI2C_CPLL_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_MPLL:
|
||||
bit_mask = REGI2C_MPLL_BIT_MASK;
|
||||
break;
|
||||
case REGI2C_DIG_REG:
|
||||
bit_mask = REGI2C_DIG_REG_BIT_MASK;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
uint32_t i2c_sel = REG_GET_BIT(I2C_ANA_MST_ANA_CONF2_REG, bit_mask << REGI2C_CONF2_SLAVE_SEL_V);
|
||||
REG_WRITE(I2C_ANA_MST_ANA_CONF1_REG, ~(bit_mask << REGI2C_CONF1_SLAVE_SEL_V) & I2C_ANA_MST_ANA_CONF1_M);
|
||||
return (uint8_t)(i2c_sel ? 0 : 1);
|
||||
}
|
||||
|
||||
uint8_t _regi2c_impl_read(uint8_t block, uint8_t host_id, uint8_t reg_add)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14680
|
||||
return 0;
|
||||
(void)host_id;
|
||||
uint8_t i2c_sel = regi2c_enable_block(block);
|
||||
|
||||
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
|
||||
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
|
||||
| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
|
||||
REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
|
||||
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
|
||||
uint8_t ret = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint8_t _regi2c_impl_read_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14680
|
||||
return 0;
|
||||
HAL_ASSERT(msb - lsb < 8);
|
||||
uint8_t i2c_sel = regi2c_enable_block(block);
|
||||
|
||||
(void)host_id;
|
||||
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
|
||||
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
|
||||
| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
|
||||
REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
|
||||
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
|
||||
uint32_t data = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
|
||||
uint8_t ret = (uint8_t)((data >> lsb) & (~(0xFFFFFFFF << (msb - lsb + 1))));
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void _regi2c_impl_write(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14680
|
||||
(void)host_id;
|
||||
uint8_t i2c_sel = regi2c_enable_block(block);
|
||||
|
||||
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY)); // wait i2c idle
|
||||
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
|
||||
| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
|
||||
| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S) // 0: READ I2C register; 1: Write I2C register;
|
||||
| (((uint32_t)data & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
|
||||
REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
|
||||
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
|
||||
}
|
||||
|
||||
void _regi2c_impl_write_mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data)
|
||||
{
|
||||
// TODO: [ESP32S31] IDF-14680
|
||||
(void)host_id;
|
||||
HAL_ASSERT(msb - lsb < 8);
|
||||
uint8_t i2c_sel = regi2c_enable_block(block);
|
||||
|
||||
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
|
||||
/*Read the i2c bus register*/
|
||||
uint32_t temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
|
||||
| (reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S;
|
||||
REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
|
||||
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
|
||||
temp = REG_GET_FIELD(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_DATA);
|
||||
/*Write the i2c bus register*/
|
||||
temp &= ((~(0xFFFFFFFF << lsb)) | (0xFFFFFFFF << (msb + 1)));
|
||||
temp = (((uint32_t)data & (~(0xFFFFFFFF << (msb - lsb + 1)))) << lsb) | temp;
|
||||
temp = ((block & REGI2C_RTC_SLAVE_ID_V) << REGI2C_RTC_SLAVE_ID_S)
|
||||
| ((reg_add & REGI2C_RTC_ADDR_V) << REGI2C_RTC_ADDR_S)
|
||||
| ((0x1 & REGI2C_RTC_WR_CNTL_V) << REGI2C_RTC_WR_CNTL_S)
|
||||
| ((temp & REGI2C_RTC_DATA_V) << REGI2C_RTC_DATA_S);
|
||||
REG_WRITE(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), temp);
|
||||
while (REG_GET_BIT(I2C_ANA_MST_I2C_CTRL_REG(i2c_sel), REGI2C_RTC_BUSY));
|
||||
}
|
||||
|
||||
@@ -1,9 +1,5 @@
|
||||
components/esp_hal_regi2c/test_apps:
|
||||
enable:
|
||||
- if: INCLUDE_DEFAULT == 1
|
||||
disable:
|
||||
- if: IDF_TARGET in ["esp32s31"]
|
||||
temporary: true
|
||||
reason: not support yet # TODO: [ESP32S31] IDF-14680
|
||||
- if: SOC_REGI2C_SUPPORTED == 1
|
||||
depends_components:
|
||||
- esp_hal_regi2c
|
||||
|
||||
@@ -1,3 +1,3 @@
|
||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
|
||||
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
|
||||
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
|
||||
|
||||
|
||||
@@ -36,7 +36,7 @@ extern "C" {
|
||||
#define TEST_REG_MASK_MSB I2C_APLL_OC_DVDD_MSB
|
||||
#define TEST_REG_MASK_LSB I2C_APLL_OC_DVDD_LSB
|
||||
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4
|
||||
#elif CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32S31
|
||||
|
||||
#include "soc/regi2c_saradc.h"
|
||||
#define TEST_BLOCK I2C_SARADC
|
||||
|
||||
@@ -17,6 +17,7 @@
|
||||
#include "pmu_param.h"
|
||||
#include "esp_private/esp_pmu.h"
|
||||
#include "esp_hw_log.h"
|
||||
#include "hal/regi2c_ctrl_ll.h"
|
||||
|
||||
ESP_HW_LOG_ATTR_TAG(TAG, "pmu_init");
|
||||
|
||||
@@ -205,4 +206,6 @@ void pmu_init(void)
|
||||
pmu_hp_system_init_default(PMU_instance());
|
||||
pmu_lp_system_init_default(PMU_instance());
|
||||
pmu_power_domain_force_default(PMU_instance());
|
||||
|
||||
regi2c_ctrl_ll_i2c_sar_periph_enable(); // TODO: IDF-14733
|
||||
}
|
||||
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-S31 MODEM LPCON register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/hp_sys_clkrst_struct.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
__attribute__((always_inline))
|
||||
static inline void modem_lpcon_ll_enable_bus_clock(bool enable)
|
||||
{
|
||||
HP_SYS_CLKRST.modem_ctrl0.reg_modem_clk_en = enable;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -159,6 +159,10 @@ config SOC_CLK_TREE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MPU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -105,6 +105,7 @@
|
||||
#define SOC_BOD_SUPPORTED 1
|
||||
#define SOC_ULP_FSM_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_MPU_SUPPORTED 1
|
||||
#define SOC_WDT_SUPPORTED 1
|
||||
#define SOC_RTC_WDT_SUPPORTED 1
|
||||
|
||||
@@ -107,6 +107,10 @@ config SOC_CLK_TREE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ASSIST_DEBUG_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -49,6 +49,7 @@
|
||||
#define SOC_BOD_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_ASSIST_DEBUG_SUPPORTED 1
|
||||
#define SOC_WDT_SUPPORTED 1
|
||||
#define SOC_RTC_WDT_SUPPORTED 1
|
||||
|
||||
@@ -163,6 +163,10 @@ config SOC_CLK_TREE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ASSIST_DEBUG_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -66,6 +66,7 @@
|
||||
#define SOC_MEMPROT_SUPPORTED 1
|
||||
#define SOC_BOD_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_ASSIST_DEBUG_SUPPORTED 1
|
||||
#define SOC_WDT_SUPPORTED 1
|
||||
#define SOC_RTC_WDT_SUPPORTED 1
|
||||
|
||||
@@ -267,6 +267,10 @@ config SOC_MODEM_CLOCK_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_LIGHT_SLEEP_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -89,6 +89,7 @@
|
||||
#define SOC_KEY_MANAGER_SUPPORTED 1
|
||||
#define SOC_HUK_SUPPORTED 1
|
||||
#define SOC_MODEM_CLOCK_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_LIGHT_SLEEP_SUPPORTED 1
|
||||
#define SOC_DEEP_SLEEP_SUPPORTED 1
|
||||
#define SOC_PM_SUPPORTED 1
|
||||
|
||||
@@ -251,6 +251,10 @@ config SOC_MODEM_CLOCK_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -85,6 +85,7 @@
|
||||
#define SOC_LIGHT_SLEEP_SUPPORTED 1
|
||||
#define SOC_DEEP_SLEEP_SUPPORTED 1
|
||||
#define SOC_MODEM_CLOCK_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_PM_SUPPORTED 1
|
||||
#define SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED 1
|
||||
|
||||
|
||||
@@ -155,7 +155,7 @@ config SOC_MODEM_CLOCK_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REG_I2C_SUPPORTED
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
|
||||
@@ -62,7 +62,7 @@
|
||||
#define SOC_RTC_WDT_SUPPORTED 1
|
||||
#define SOC_SPI_FLASH_SUPPORTED 1
|
||||
#define SOC_MODEM_CLOCK_SUPPORTED 1
|
||||
#define SOC_REG_I2C_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_ETM_SUPPORTED 1
|
||||
#define SOC_SDIO_SLAVE_SUPPORTED 1
|
||||
#define SOC_PAU_SUPPORTED 1
|
||||
|
||||
@@ -247,6 +247,10 @@ config SOC_MODEM_CLOCK_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -100,6 +100,7 @@
|
||||
#define SOC_LIGHT_SLEEP_SUPPORTED 1
|
||||
#define SOC_DEEP_SLEEP_SUPPORTED 1
|
||||
#define SOC_MODEM_CLOCK_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_PM_SUPPORTED 1
|
||||
#define SOC_SPI_EXTERNAL_NOR_FLASH_SUPPORTED 1
|
||||
|
||||
|
||||
@@ -151,7 +151,7 @@ config SOC_MODEM_CLOCK_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REG_I2C_SUPPORTED
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
|
||||
@@ -72,7 +72,7 @@
|
||||
#define SOC_SPI_FLASH_SUPPORTED 1 //TODO: [ESP32H21] IDF-11526
|
||||
// #define SOC_RNG_SUPPORTED 1 //TODO: [ESP32H21] IDF-11503
|
||||
#define SOC_MODEM_CLOCK_SUPPORTED 1
|
||||
#define SOC_REG_I2C_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
// #define SOC_PHY_SUPPORTED 1
|
||||
#define SOC_PCNT_SUPPORTED 1
|
||||
#define SOC_MCPWM_SUPPORTED 1
|
||||
|
||||
@@ -151,7 +151,7 @@ config SOC_TOUCH_SENSOR_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REG_I2C_SUPPORTED
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
|
||||
@@ -81,7 +81,7 @@
|
||||
#define SOC_LP_AON_SUPPORTED 1
|
||||
#define SOC_TOUCH_SENSOR_SUPPORTED 1
|
||||
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
|
||||
#define SOC_REG_I2C_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
#define SOC_ASSIST_DEBUG_SUPPORTED 1
|
||||
#define SOC_WDT_SUPPORTED 1
|
||||
|
||||
@@ -323,6 +323,10 @@ config SOC_CLK_TREE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_ASSIST_DEBUG_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -103,6 +103,7 @@
|
||||
#define SOC_PSRAM_DMA_CAPABLE 1
|
||||
#define SOC_SDMMC_HOST_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_ASSIST_DEBUG_SUPPORTED 1
|
||||
#define SOC_DEBUG_PROBE_SUPPORTED 1
|
||||
#define SOC_WDT_SUPPORTED 1
|
||||
|
||||
@@ -195,6 +195,10 @@ config SOC_CLK_TREE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MPU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -91,6 +91,7 @@
|
||||
#define SOC_TOUCH_SENSOR_SUPPORTED 1
|
||||
#define SOC_BOD_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_MPU_SUPPORTED 1
|
||||
#define SOC_WDT_SUPPORTED 1
|
||||
#define SOC_RTC_WDT_SUPPORTED 1
|
||||
|
||||
@@ -227,6 +227,10 @@ config SOC_CLK_TREE_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MPU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -84,6 +84,7 @@
|
||||
#define SOC_TOUCH_SENSOR_SUPPORTED 1
|
||||
#define SOC_BOD_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
#define SOC_MPU_SUPPORTED 1
|
||||
#define SOC_WDT_SUPPORTED 1
|
||||
#define SOC_RTC_WDT_SUPPORTED 1
|
||||
|
||||
@@ -0,0 +1,296 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "modem/reg_base.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define I2C_ANA_MST_I2C0_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x0)
|
||||
/* I2C_ANA_MST_I2C0_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_BUSY (BIT(25))
|
||||
#define I2C_ANA_MST_I2C0_BUSY_M (BIT(25))
|
||||
#define I2C_ANA_MST_I2C0_BUSY_V 0x1
|
||||
#define I2C_ANA_MST_I2C0_BUSY_S 25
|
||||
/* I2C_ANA_MST_I2C0_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_CTRL 0x01FFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CTRL_M ((I2C_ANA_MST_I2C0_CTRL_V)<<(I2C_ANA_MST_I2C0_CTRL_S))
|
||||
#define I2C_ANA_MST_I2C0_CTRL_V 0x1FFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CTRL_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C1_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x4)
|
||||
/* I2C_ANA_MST_I2C1_BUSY : RO ;bitpos:[25] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_BUSY (BIT(25))
|
||||
#define I2C_ANA_MST_I2C1_BUSY_M (BIT(25))
|
||||
#define I2C_ANA_MST_I2C1_BUSY_V 0x1
|
||||
#define I2C_ANA_MST_I2C1_BUSY_S 25
|
||||
/* I2C_ANA_MST_I2C1_CTRL : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_CTRL 0x01FFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CTRL_M ((I2C_ANA_MST_I2C1_CTRL_V)<<(I2C_ANA_MST_I2C1_CTRL_S))
|
||||
#define I2C_ANA_MST_I2C1_CTRL_V 0x1FFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CTRL_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C_CTRL_REG(n) (I2C_ANA_MST_I2C0_CTRL_REG + n * 4) // 0: I2C_ANA_MST_I2C0_CTRL_REG; 1: I2C_ANA_MST_I2C1_CTRL_REG
|
||||
|
||||
#define REGI2C_RTC_BUSY (BIT(25))
|
||||
#define REGI2C_RTC_BUSY_M (BIT(25))
|
||||
#define REGI2C_RTC_BUSY_V 0x1
|
||||
#define REGI2C_RTC_BUSY_S 25
|
||||
|
||||
#define REGI2C_RTC_WR_CNTL (BIT(24))
|
||||
#define REGI2C_RTC_WR_CNTL_M (BIT(24))
|
||||
#define REGI2C_RTC_WR_CNTL_V 0x1
|
||||
#define REGI2C_RTC_WR_CNTL_S 24
|
||||
|
||||
#define REGI2C_RTC_DATA 0x000000FF
|
||||
#define REGI2C_RTC_DATA_M ((I2C_RTC_DATA_V)<<(I2C_RTC_DATA_S))
|
||||
#define REGI2C_RTC_DATA_V 0xFF
|
||||
#define REGI2C_RTC_DATA_S 16
|
||||
|
||||
#define REGI2C_RTC_ADDR 0x000000FF
|
||||
#define REGI2C_RTC_ADDR_M ((I2C_RTC_ADDR_V)<<(I2C_RTC_ADDR_S))
|
||||
#define REGI2C_RTC_ADDR_V 0xFF
|
||||
#define REGI2C_RTC_ADDR_S 8
|
||||
|
||||
#define REGI2C_RTC_SLAVE_ID 0x000000FF
|
||||
#define REGI2C_RTC_SLAVE_ID_M ((I2C_RTC_SLAVE_ID_V)<<(I2C_RTC_SLAVE_ID_S))
|
||||
#define REGI2C_RTC_SLAVE_ID_V 0xFF
|
||||
#define REGI2C_RTC_SLAVE_ID_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C0_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x8)
|
||||
/* I2C_ANA_MST_I2C0_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_STATUS 0x000000FF
|
||||
#define I2C_ANA_MST_I2C0_STATUS_M ((I2C_ANA_MST_I2C0_STATUS_V)<<(I2C_ANA_MST_I2C0_STATUS_S))
|
||||
#define I2C_ANA_MST_I2C0_STATUS_V 0xFF
|
||||
#define I2C_ANA_MST_I2C0_STATUS_S 24
|
||||
/* I2C_ANA_MST_I2C0_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_CONF 0x00FFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CONF_M ((I2C_ANA_MST_I2C0_CONF_V)<<(I2C_ANA_MST_I2C0_CONF_S))
|
||||
#define I2C_ANA_MST_I2C0_CONF_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_I2C0_CONF_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C1_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0xC)
|
||||
/* I2C_ANA_MST_I2C1_STATUS : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_STATUS 0x000000FF
|
||||
#define I2C_ANA_MST_I2C1_STATUS_M ((I2C_ANA_MST_I2C1_STATUS_V)<<(I2C_ANA_MST_I2C1_STATUS_S))
|
||||
#define I2C_ANA_MST_I2C1_STATUS_V 0xFF
|
||||
#define I2C_ANA_MST_I2C1_STATUS_S 24
|
||||
/* I2C_ANA_MST_I2C1_CONF : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_CONF 0x00FFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CONF_M ((I2C_ANA_MST_I2C1_CONF_V)<<(I2C_ANA_MST_I2C1_CONF_S))
|
||||
#define I2C_ANA_MST_I2C1_CONF_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_I2C1_CONF_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C_BURST_CONF_REG (DR_REG_I2C_ANA_MST_BASE + 0x10)
|
||||
/* I2C_ANA_MST_I2C_MST_BURST_CTRL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_CTRL 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_M ((I2C_ANA_MST_I2C_MST_BURST_CTRL_V)<<(I2C_ANA_MST_I2C_MST_BURST_CTRL_S))
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_V 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_CTRL_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C_BURST_STATUS_REG (DR_REG_I2C_ANA_MST_BASE + 0x14)
|
||||
/* I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT : R/W ;bitpos:[31:20] ;default: 12'h400 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT 0x00000FFF
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_M ((I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V)<<(I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S))
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_V 0xFFF
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_TIMEOUT_CNT_S 20
|
||||
/* I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG (BIT(2))
|
||||
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_M (BIT(2))
|
||||
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_V 0x1
|
||||
#define I2C_ANA_MST_I2C_MST1_BURST_ERR_FLAG_S 2
|
||||
/* I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG (BIT(1))
|
||||
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_M (BIT(1))
|
||||
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_V 0x1
|
||||
#define I2C_ANA_MST_I2C_MST0_BURST_ERR_FLAG_S 1
|
||||
/* I2C_ANA_MST_I2C_MST_BURST_DONE : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_DONE (BIT(0))
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_DONE_M (BIT(0))
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_DONE_V 0x1
|
||||
#define I2C_ANA_MST_I2C_MST_BURST_DONE_S 0
|
||||
|
||||
#define I2C_ANA_MST_ANA_CONF0_REG (DR_REG_I2C_ANA_MST_BASE + 0x18)
|
||||
/* I2C_ANA_MST_ANA_STATUS0 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_STATUS0 0x000000FF
|
||||
#define I2C_ANA_MST_ANA_STATUS0_M ((I2C_ANA_MST_ANA_STATUS0_V)<<(I2C_ANA_MST_ANA_STATUS0_S))
|
||||
#define I2C_ANA_MST_ANA_STATUS0_V 0xFF
|
||||
#define I2C_ANA_MST_ANA_STATUS0_S 24
|
||||
/* I2C_ANA_MST_ANA_CONF0 : R/W ;bitpos:[23:0] ;default: 24'h00_e408 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_CONF0 0x00FFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF0_M ((I2C_ANA_MST_ANA_CONF0_V)<<(I2C_ANA_MST_ANA_CONF0_S))
|
||||
#define I2C_ANA_MST_ANA_CONF0_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF0_S 0
|
||||
|
||||
#define I2C_ANA_MST_ANA_CONF1_REG (DR_REG_I2C_ANA_MST_BASE + 0x1C)
|
||||
/* I2C_ANA_MST_ANA_STATUS1 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_STATUS1 0x000000FF
|
||||
#define I2C_ANA_MST_ANA_STATUS1_M ((I2C_ANA_MST_ANA_STATUS1_V)<<(I2C_ANA_MST_ANA_STATUS1_S))
|
||||
#define I2C_ANA_MST_ANA_STATUS1_V 0xFF
|
||||
#define I2C_ANA_MST_ANA_STATUS1_S 24
|
||||
/* I2C_ANA_MST_ANA_CONF1 : R/W ;bitpos:[23:0] ;default: 24'h00_002d ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_CONF1 0x00FFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF1_M ((I2C_ANA_MST_ANA_CONF1_V)<<(I2C_ANA_MST_ANA_CONF1_S))
|
||||
#define I2C_ANA_MST_ANA_CONF1_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF1_S 0
|
||||
|
||||
#define I2C_ANA_MST_ANA_CONF2_REG (DR_REG_I2C_ANA_MST_BASE + 0x20)
|
||||
/* I2C_ANA_MST_ANA_STATUS2 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_STATUS2 0x000000FF
|
||||
#define I2C_ANA_MST_ANA_STATUS2_M ((I2C_ANA_MST_ANA_STATUS2_V)<<(I2C_ANA_MST_ANA_STATUS2_S))
|
||||
#define I2C_ANA_MST_ANA_STATUS2_V 0xFF
|
||||
#define I2C_ANA_MST_ANA_STATUS2_S 24
|
||||
/* I2C_ANA_MST_ANA_CONF2 : R/W ;bitpos:[23:0] ;default: 24'h00_0004 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ANA_CONF2 0x00FFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF2_M ((I2C_ANA_MST_ANA_CONF2_V)<<(I2C_ANA_MST_ANA_CONF2_S))
|
||||
#define I2C_ANA_MST_ANA_CONF2_V 0xFFFFFF
|
||||
#define I2C_ANA_MST_ANA_CONF2_S 0
|
||||
|
||||
/**
|
||||
* In I2C_ANA_MST_ANA_CONF1_REG, the real slave bit position is REGI2C_xxx_BIT_MASK << REGI2C_CONF1_SLAVE_SEL_V
|
||||
* In I2C_ANA_MST_ANA_CONF2_REG, the real slave bit position is REGI2C_xxx_BIT_MASK << REGI2C_CONF2_SLAVE_SEL_V
|
||||
*/
|
||||
#define REGI2C_CONF1_SLAVE_SEL_V 2
|
||||
#define REGI2C_CONF2_SLAVE_SEL_V 4
|
||||
|
||||
#define REGI2C_BB_BIT_MASK (BIT(0))
|
||||
#define REGI2C_TXRF_BIT_MASK (BIT(1))
|
||||
#define REGI2C_SDM_BIT_MASK (BIT(2))
|
||||
#define REGI2C_RFPLL_BIT_MASK (BIT(3))
|
||||
#define REGI2C_BIAS_BIT_MASK (BIT(4))
|
||||
#define REGI2C_BBPLL_BIT_MASK (BIT(5))
|
||||
#define REGI2C_ULP_BIT_MASK (BIT(6))
|
||||
#define REGI2C_SAR_MASTER_BIT_MASK (BIT(7))
|
||||
#define REGI2C_SAR_SLAVE_BIT_MASK (BIT(8))
|
||||
#define REGI2C_PERIF_BIT_MASK (BIT(9))
|
||||
#define REGI2C_APLL_BIT_MASK (BIT(10))
|
||||
#define REGI2C_CPLL_BIT_MASK (BIT(11))
|
||||
#define REGI2C_MPLL_BIT_MASK (BIT(12))
|
||||
#define REGI2C_DIG_REG_BIT_MASK (BIT(13))
|
||||
|
||||
#define I2C_ANA_MST_I2C0_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x24)
|
||||
/* I2C_ANA_MST_I2C0_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD 0x0000001F
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S))
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_V 0x1F
|
||||
#define I2C_ANA_MST_I2C0_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_ANA_MST_I2C0_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR 0x0000003F
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S))
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_V 0x3F
|
||||
#define I2C_ANA_MST_I2C0_SCL_PULSE_DUR_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C1_CTRL1_REG (DR_REG_I2C_ANA_MST_BASE + 0x28)
|
||||
/* I2C_ANA_MST_I2C1_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD 0x0000001F
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_M ((I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S))
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_V 0x1F
|
||||
#define I2C_ANA_MST_I2C1_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_ANA_MST_I2C1_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR 0x0000003F
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_M ((I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S))
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_V 0x3F
|
||||
#define I2C_ANA_MST_I2C1_SCL_PULSE_DUR_S 0
|
||||
|
||||
#define I2C_ANA_MST_HW_I2C_CTRL_REG (DR_REG_I2C_ANA_MST_BASE + 0x2C)
|
||||
/* I2C_ANA_MST_ARBITER_DIS : R/W ;bitpos:[11] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_ARBITER_DIS (BIT(11))
|
||||
#define I2C_ANA_MST_ARBITER_DIS_M (BIT(11))
|
||||
#define I2C_ANA_MST_ARBITER_DIS_V 0x1
|
||||
#define I2C_ANA_MST_ARBITER_DIS_S 11
|
||||
/* I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD : R/W ;bitpos:[10:6] ;default: 5'h1 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD 0x0000001F
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_M ((I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V)<<(I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S))
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_V 0x1F
|
||||
#define I2C_ANA_MST_HW_I2C_SDA_SIDE_GUARD_S 6
|
||||
/* I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR : R/W ;bitpos:[5:0] ;default: 6'h2 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR 0x0000003F
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_M ((I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V)<<(I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S))
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_V 0x3F
|
||||
#define I2C_ANA_MST_HW_I2C_SCL_PULSE_DUR_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C_MST_NOUSE_REG (DR_REG_I2C_ANA_MST_BASE + 0x30)
|
||||
/* I2C_ANA_MST_I2C_MST_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C_MST_NOUSE 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_I2C_MST_NOUSE_M ((I2C_ANA_MST_I2C_MST_NOUSE_V)<<(I2C_ANA_MST_I2C_MST_NOUSE_S))
|
||||
#define I2C_ANA_MST_I2C_MST_NOUSE_V 0xFFFFFFFF
|
||||
#define I2C_ANA_MST_I2C_MST_NOUSE_S 0
|
||||
|
||||
#define I2C_ANA_MST_EXT_I2C_MASK_REG (DR_REG_I2C_ANA_MST_BASE + 0x34)
|
||||
/* I2C_ANA_MST_EXT_I2C_SDA_O_MASK : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK 0x0000FFFF
|
||||
#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK_M ((I2C_ANA_MST_EXT_I2C_SDA_O_MASK_V)<<(I2C_ANA_MST_EXT_I2C_SDA_O_MASK_S))
|
||||
#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK_V 0xFFFF
|
||||
#define I2C_ANA_MST_EXT_I2C_SDA_O_MASK_S 16
|
||||
/* I2C_ANA_MST_EXT_I2C_SDA_I_MASK : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK 0x0000FFFF
|
||||
#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK_M ((I2C_ANA_MST_EXT_I2C_SDA_I_MASK_V)<<(I2C_ANA_MST_EXT_I2C_SDA_I_MASK_S))
|
||||
#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK_V 0xFFFF
|
||||
#define I2C_ANA_MST_EXT_I2C_SDA_I_MASK_S 0
|
||||
|
||||
#define I2C_ANA_MST_I2C_MASK_REG (DR_REG_I2C_ANA_MST_BASE + 0x38)
|
||||
/* I2C_ANA_MST_I2C_SDA_O_MASK : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C_SDA_O_MASK 0x0000FFFF
|
||||
#define I2C_ANA_MST_I2C_SDA_O_MASK_M ((I2C_ANA_MST_I2C_SDA_O_MASK_V)<<(I2C_ANA_MST_I2C_SDA_O_MASK_S))
|
||||
#define I2C_ANA_MST_I2C_SDA_O_MASK_V 0xFFFF
|
||||
#define I2C_ANA_MST_I2C_SDA_O_MASK_S 16
|
||||
/* I2C_ANA_MST_I2C_SDA_I_MASK : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_I2C_SDA_I_MASK 0x0000FFFF
|
||||
#define I2C_ANA_MST_I2C_SDA_I_MASK_M ((I2C_ANA_MST_I2C_SDA_I_MASK_V)<<(I2C_ANA_MST_I2C_SDA_I_MASK_S))
|
||||
#define I2C_ANA_MST_I2C_SDA_I_MASK_V 0xFFFF
|
||||
#define I2C_ANA_MST_I2C_SDA_I_MASK_S 0
|
||||
|
||||
#define I2C_ANA_MST_DATE_REG (DR_REG_I2C_ANA_MST_BASE + 0x3C)
|
||||
/* I2C_ANA_MST_CLK_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_CLK_EN (BIT(28))
|
||||
#define I2C_ANA_MST_CLK_EN_M (BIT(28))
|
||||
#define I2C_ANA_MST_CLK_EN_V 0x1
|
||||
#define I2C_ANA_MST_CLK_EN_S 28
|
||||
/* I2C_ANA_MST_DATE : R/W ;bitpos:[27:0] ;default: 28'h2411290 ; */
|
||||
/*description: .*/
|
||||
#define I2C_ANA_MST_DATE 0x0FFFFFFF
|
||||
#define I2C_ANA_MST_DATE_M ((I2C_ANA_MST_DATE_V)<<(I2C_ANA_MST_DATE_S))
|
||||
#define I2C_ANA_MST_DATE_V 0xFFFFFFF
|
||||
#define I2C_ANA_MST_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -20,3 +20,6 @@
|
||||
#define DR_REG_MODEM_SYSCON_BASE (MODEM_BASE + 0x9C00)
|
||||
|
||||
#define DR_REG_MODEM_LPCON_BASE (MODEM_PWR_BASE + 0x2000)
|
||||
|
||||
#define DR_REG_I2C_ANA_MST_BASE (MODEM_PWR_BASE + 0x2800)
|
||||
#define DR_REG_I2C_ANA_MST_MEM_BASE (MODEM_PWR_BASE + 0x2c00)
|
||||
|
||||
@@ -87,6 +87,10 @@ config SOC_CORDIC_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_REGI2C_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_XTAL_SUPPORT_40M
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -0,0 +1,79 @@
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
/**
|
||||
* @file regi2c_saradc.h
|
||||
* @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
|
||||
*
|
||||
* This file lists register fields of SAR, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
|
||||
* function in adc_ll.h.
|
||||
*/
|
||||
|
||||
#define I2C_SARADC 0X69
|
||||
#define I2C_SARADC_HOSTID 0
|
||||
|
||||
#define I2C_SARADC_SAR1_INIT_CODE_LSB 0x0
|
||||
#define I2C_SARADC_SAR1_INIT_CODE_LSB_MSB 0x7
|
||||
#define I2C_SARADC_SAR1_INIT_CODE_LSB_LSB 0x0
|
||||
|
||||
#define I2C_SARADC_SAR1_INIT_CODE_MSB 0x1
|
||||
#define I2C_SARADC_SAR1_INIT_CODE_MSB_MSB 0x3
|
||||
#define I2C_SARADC_SAR1_INIT_CODE_MSB_LSB 0x0
|
||||
|
||||
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
|
||||
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
|
||||
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR1_DREF_ADDR 0x2
|
||||
#define ADC_SAR1_DREF_ADDR_MSB 0x6
|
||||
#define ADC_SAR1_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
|
||||
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
|
||||
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
|
||||
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
|
||||
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR2_SAMPLE_CYCLE_ADDR 0x5
|
||||
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_MSB 0x2
|
||||
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SAR2_DREF_ADDR 0x5
|
||||
#define ADC_SAR2_DREF_ADDR_MSB 0x6
|
||||
#define ADC_SAR2_DREF_ADDR_LSB 0x4
|
||||
|
||||
#define I2C_SARADC_TSENS_DAC 0x6
|
||||
#define I2C_SARADC_TSENS_DAC_MSB 0x3
|
||||
#define I2C_SARADC_TSENS_DAC_LSB 0x0
|
||||
|
||||
#define ADC_SARADC_DTEST_RTC_ADDR 0x7
|
||||
#define ADC_SARADC_DTEST_RTC_ADDR_MSB 0x1
|
||||
#define ADC_SARADC_DTEST_RTC_ADDR_LSB 0x0
|
||||
|
||||
#define ADC_SARADC_ENT_TSENS_ADDR 0x7
|
||||
#define ADC_SARADC_ENT_TSENS_ADDR_MSB 0x2
|
||||
#define ADC_SARADC_ENT_TSENS_ADDR_LSB 0x2
|
||||
|
||||
#define POWER_GLITCH_DREF_VDET_PERIF 11
|
||||
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2
|
||||
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0
|
||||
|
||||
#define POWER_GLITCH_DREF_VDET_VDDPST 11
|
||||
#define POWER_GLITCH_DREF_VDET_VDDPST_MSB 6
|
||||
#define POWER_GLITCH_DREF_VDET_VDDPST_LSB 4
|
||||
|
||||
#define POWER_GLITCH_DREF_VDET_PLLBB 12
|
||||
#define POWER_GLITCH_DREF_VDET_PLLBB_MSB 2
|
||||
#define POWER_GLITCH_DREF_VDET_PLLBB_LSB 0
|
||||
|
||||
#define POWER_GLITCH_DREF_VDET_PLL 12
|
||||
#define POWER_GLITCH_DREF_VDET_PLL_MSB 6
|
||||
#define POWER_GLITCH_DREF_VDET_PLL_LSB 4
|
||||
@@ -97,7 +97,8 @@
|
||||
// #define SOC_PM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14648
|
||||
// #define SOC_BITSCRAMBLER_SUPPORTED 1 // TODO: [ESP32S31] IDF-14714
|
||||
// #define SOC_SIMD_INSTRUCTION_SUPPORTED 1 // TODO: [ESP32S31] IDF-14661
|
||||
#define SOC_CORDIC_SUPPORTED 1
|
||||
#define SOC_CORDIC_SUPPORTED 1
|
||||
#define SOC_REGI2C_SUPPORTED 1
|
||||
|
||||
/*-------------------------- XTAL CAPS ---------------------------------------*/
|
||||
#define SOC_XTAL_SUPPORT_40M 1
|
||||
|
||||
@@ -116,3 +116,6 @@ PROVIDE ( TRACE1 = 0x2D001000 );
|
||||
PROVIDE ( ASSIST_DEBUG = 0x2D002000 );
|
||||
PROVIDE ( MEM_MONITOR0 = 0x2D003000 );
|
||||
PROVIDE ( MEM_MONITOR1 = 0x2D004000 );
|
||||
|
||||
PROVIDE ( MODEM_SYSCON = 0x20109C00 );
|
||||
PROVIDE ( MODEM_LPCON = 0x2010F000 );
|
||||
|
||||
Reference in New Issue
Block a user