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feat(hal): graudate the adc/dac hal driver into a new component

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This commit is contained in:
laokaiyao
2025-11-26 14:29:45 +08:00
parent 55537c99db
commit 841cb4caa1
64 changed files with 583 additions and 450 deletions
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components/bootloader_support/CMakeLists.txt
+4 -2
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@@ -73,7 +73,8 @@ if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_RAM)
set(include_dirs "include" "bootloader_flash/include"
"private_include")
set(priv_requires micro-ecc spi_flash efuse esp_bootloader_format esp_app_format esptool_py)
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio)
# `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_ana_conv)
list(APPEND srcs
"src/bootloader_init.c"
"src/bootloader_clock_loader.c"
@@ -90,7 +91,8 @@ else()
set(priv_include_dirs "private_include")
# heap is required for `heap_memory_layout.h` header
set(priv_requires spi_flash mbedtls efuse heap esp_bootloader_format esp_app_format esptool_py)
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio)
# `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_ana_conv)
endif()
if(BOOTLOADER_BUILD)
components/esp_adc/CMakeLists.txt
+1
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@@ -57,4 +57,5 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
PRIV_REQUIRES esp_driver_gpio efuse esp_pm esp_ringbuf esp_mm ${extra_requires}
REQUIRES esp_hal_ana_conv
LDFRAGMENTS linker.lf)
components/esp_adc/adc_common.c
+1 -1
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@@ -16,7 +16,7 @@
#include "hal/adc_hal.h"
#include "hal/adc_hal_common.h"
#include "esp_private/regi2c_ctrl.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "hal/adc_ll.h"
static const char *TAG = "adc_common";
components/esp_adc/adc_oneshot.c
+1 -1
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@@ -30,7 +30,7 @@
#include "hal/adc_types.h"
#include "hal/adc_oneshot_hal.h"
#include "hal/adc_ll.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/soc_caps.h"
#if CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM
components/esp_adc/linker.lf
+1 -1
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@@ -11,7 +11,7 @@ entries:
esp_clk_tree: esp_clk_tree_enable_src (noflash)
[mapping:adc_hal]
archive: libhal.a
archive: libesp_hal_ana_conv.a
entries:
if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y:
adc_oneshot_hal (noflash)
components/esp_adc/test_apps/adc/CMakeLists.txt
+10 -1
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@@ -11,9 +11,18 @@ project(adc_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(ADC_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_adc
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_ana_conv
)
string(JOIN "," ADC_RTL_DIRS_JOINED ${ADC_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_adc/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${ADC_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/adc_test.elf
find-refs
--from-sections=.iram0.text
components/esp_adc/test_apps/adc/main/test_adc.c
+1 -1
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@@ -9,7 +9,7 @@
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "esp_adc/adc_oneshot.h"
#include "esp_adc/adc_monitor.h"
#include "driver/gpio.h"
components/esp_adc/test_apps/adc/main/test_adc_performance.c
+1 -1
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@@ -11,7 +11,7 @@
#include "esp_log.h"
#include "esp_err.h"
#include "esp_cpu.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_adc/adc_oneshot.h"
components/esp_adc/test_apps/adc/main/test_adc_tsens.c
+1 -1
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@@ -8,7 +8,7 @@
#include <stdlib.h>
#include <string.h>
#include "esp_log.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "esp_adc/adc_oneshot.h"
#include "esp_adc/adc_continuous.h"
#include "driver/gpio.h"
components/esp_adc/test_apps/adc/main/test_adc_wifi.c
+1 -1
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@@ -8,7 +8,7 @@
#include <stdlib.h>
#include <string.h>
#include "esp_log.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "esp_adc/adc_oneshot.h"
#include "driver/gpio.h"
#include "driver/rtc_io.h"
components/esp_adc/test_apps/adc/main/test_common_adc.c
+1 -1
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@@ -11,7 +11,7 @@
#include "freertos/task.h"
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "test_common_adc.h"
#include "hal/adc_ll.h"
components/esp_driver_dac/CMakeLists.txt
+1
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@@ -28,5 +28,6 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS "./include"
PRIV_REQUIRES ${priv_req}
REQUIRES esp_hal_ana_conv
LDFRAGMENTS "linker.lf"
)
components/esp_driver_dac/dac_common.c
+1 -1
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@@ -8,7 +8,7 @@
#include <string.h>
#include "freertos/FreeRTOS.h"
#include "soc/soc_caps.h"
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
#include "hal/dac_types.h"
#include "hal/dac_ll.h"
#include "esp_private/gpio.h"
components/esp_driver_dac/test_apps/dac/CMakeLists.txt
+9 -1
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@@ -9,9 +9,17 @@ project(dac_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(DAC_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_dac
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_ana_conv
)
string(JOIN "," DAC_RTL_DIRS_JOINED ${DAC_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_dac/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${DAC_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/dac_test.elf
find-refs
--from-sections=.iram0.text
components/esp_driver_i2s/CMakeLists.txt
+7 -1
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@@ -6,6 +6,12 @@ endif()
set(srcs)
set(include "include")
set(priv_requires esp_driver_gpio esp_pm esp_mm)
if(${target} STREQUAL "esp32")
# ADC on esp32 is routed to I2S0, I2S driver needs to operate ADC to ensure the I2S function.
list(APPEND priv_requires esp_hal_ana_conv)
endif()
# I2S related source files
if(CONFIG_SOC_I2S_SUPPORTED)
@@ -36,7 +42,7 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${include}
PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm
PRIV_REQUIRES ${priv_requires}
REQUIRES esp_hal_i2s
LDFRAGMENTS linker.lf
)
components/esp_driver_i2s/test_apps/i2s/CMakeLists.txt
+9 -1
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@@ -9,9 +9,17 @@ project(i2s_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(I2S_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_i2s
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_i2s
)
string(JOIN "," I2S_RTL_DIRS_JOINED ${I2S_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_i2s/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${I2S_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/i2s_test.elf
find-refs
--from-sections=.iram0.text
components/esp_driver_parlio/test_apps/parlio/CMakeLists.txt
+9 -1
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@@ -9,10 +9,18 @@ project(parlio_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(PARLIO_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_parlio
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_parlio
)
string(JOIN "," PARLIO_RTL_DIRS_JOINED ${PARLIO_RTL_DIRS})
add_custom_target(
check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_parlio/,${CMAKE_BINARY_DIR}/esp-idf/esp_hal_parlio/
--rtl-dirs ${PARLIO_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/parlio_test.elf
find-refs
--from-sections=.iram0.text
components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt
+1 -1
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@@ -19,7 +19,7 @@ endif()
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_driver_parlio esp_driver_gpio
esp_driver_i2s esp_driver_spi esp_psram
esp_driver_bitscrambler esp_hal_parlio
esp_driver_bitscrambler
WHOLE_ARCHIVE)
if(CONFIG_SOC_BITSCRAMBLER_SUPPORTED)
components/esp_hal_ana_conv/CMakeLists.txt
+31
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@@ -0,0 +1,31 @@
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
set(requires soc hal)
if(${target} STREQUAL "esp32")
list(APPEND requires esp_hal_i2s)
endif()
set(srcs)
set(includes "include")
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND includes "${target}/include")
endif()
if(CONFIG_SOC_ADC_SUPPORTED)
list(APPEND srcs "${target}/adc_periph.c" "adc_hal_common.c" "adc_oneshot_hal.c")
if(CONFIG_SOC_ADC_DMA_SUPPORTED)
list(APPEND srcs "adc_hal.c")
endif()
endif()
if(CONFIG_SOC_DAC_SUPPORTED)
list(APPEND srcs "${target}/dac_periph.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES ${requires})
components/esp_hal_ana_conv/README.md
+101
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@@ -0,0 +1,101 @@
# ESP Hardware Abstraction Layer for Analog Conversion Peripherals
> [!NOTE]
> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
## Overview
The `esp_hal_ana_conv` component provides a **Hardware Abstraction Layer** for analog conversion related peripherals across all ESP-IDF supported targets. This HAL currently supports Analog-to-Digital Converter (ADC), Digital-to-Analog Converter (DAC) and other analog conversion related peripherals. The HAL enables analog signal acquisition, generation, and monitoring capabilities.
## Architecture
The analog conversion HAL is structured in two main sub-layers:
1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control analog conversion peripherals (e.g., initialization, channel configuration, conversion control, DMA setup, sensor reading).
2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
## Supported Controllers
### ADC Controllers
This HAL supports various ADC controller types depending on the ESP chip:
- **RTC Controller**: Single conversion mode for low-power applications, supports deep sleep operation
- **ULP Controller**: Ultra-low-power controller for ULP coprocessor control
- **Digital Controller (DIG)**: Continuous conversion mode with DMA support, high-performance multi-channel scanning
- **Arbiter Controller (ARB)**: Manages multiple controller access to ADC2 (ESP32-S2, ESP32-S3)
- **PWDET Controller**: Power detection controller for Wi-Fi power monitoring (ADC2 only)
### DAC Controllers
This HAL supports various DAC controller types depending on the ESP chip:
- **RTC Controller**: Direct voltage output control
- **DMA Controller**: High-speed data output via I2S or SPI DMA
## ADC Features
### Work Modes
- **Oneshot Mode**: Single conversion per trigger, suitable for polling-based applications
- **Continuous Mode**: Continuous conversion with DMA, supports high-speed multi-channel scanning
- **Low-Power Mode**: Ultra-low-power operation for battery-powered applications
- **PWDET Mode**: Power detection mode for Wi-Fi power monitoring
### Conversion Capabilities
- **Multi-Unit Support**: Support for ADC1 and ADC2 (where available)
- **Conversion Modes**:
- Single unit mode (ADC1 or ADC2 only)
- Both units mode (ADC1 and ADC2 simultaneously)
- Alternate unit mode (ADC1 and ADC2 alternately)
- **Resolution Options**: 9-bit, 10-bit, 11-bit, 12-bit, 13-bit (chip-dependent)
- **Attenuation Options**: 0dB, 2.5dB, 6dB, 12dB for different input voltage ranges
- **Pattern Table**: Configurable scan sequence with up to 16 patterns per unit
### Signal Processing
- **IIR Filtering**: Digital IIR filters for noise reduction at high sampling rates
- **Monitor Function**: Hardware threshold monitoring with interrupt support
- **Data Inversion**: Optional data inversion for compatibility
- **Calibration**: Hardware and software calibration support for improved accuracy
### Clock and Timing
- **Flexible Clock Sources**: APB clock, APLL, XTAL, RC_FAST (chip-dependent)
- **Configurable Sampling Rate**: Adjustable via clock division and trigger interval
- **FSM Timing Control**: Configurable wait times for reset, start, and standby phases
## DAC Features
### Output Capabilities
- **Dual Channel Support**: Two independent DAC channels (DAC_CHAN_0, DAC_CHAN_1)
- **8-bit Resolution**: 256-level voltage output (0V to VDD3P3_RTC)
- **Direct Voltage Output**: Direct control of output voltage value
### Cosine Wave Generator
- **Frequency Control**: Configurable frequency from 130Hz to several MHz
- **Amplitude Control**: Adjustable attenuation (0dB, 6dB, 12dB, 18dB)
- **Phase Control**: 0° or 180° phase shift support
- **DC Offset**: Configurable DC component for signal offset
### Advanced Features
- **DMA Output**: High-speed data streaming via I2S, SPI or GDMA
- **ADC-DAC Synchronization**: Synchronized operation with ADC RTC controller
- **Power Management**: Independent power control per channel
## Usage
The HAL functions primarily serve ESP-IDF peripheral drivers such as `esp_adc` and `esp_driver_dac`.
Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
## Dependencies
- `soc`: Provides chip-specific register definitions
- `hal`: Core hardware abstraction utilities and macros
components/hal/adc_hal.c → components/esp_hal_ana_conv/adc_hal.c
-1
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@@ -188,7 +188,6 @@ void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_c
adc_hal_digi_sample_freq_config(hal, cfg->clk_src, cfg->clk_src_freq_hz, cfg->sample_freq_hz);
}
void adc_hal_digi_dma_link(adc_hal_dma_ctx_t *hal, uint8_t *data_buf)
{
dma_descriptor_t *desc = hal->rx_desc;
components/hal/adc_hal_common.c → components/esp_hal_ana_conv/adc_hal_common.c
+26 -28
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@@ -18,43 +18,43 @@ static adc_ll_controller_t get_controller(adc_unit_t unit, adc_hal_work_mode_t w
if (unit == ADC_UNIT_1) {
switch (work_mode) {
#if SOC_ULP_HAS_ADC || SOC_LP_CORE_SUPPORT_LP_ADC
case ADC_HAL_LP_MODE:
return ADC_LL_CTRL_ULP;
case ADC_HAL_LP_MODE:
return ADC_LL_CTRL_ULP;
#endif
case ADC_HAL_SINGLE_READ_MODE:
case ADC_HAL_SINGLE_READ_MODE:
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
return ADC_LL_CTRL_DIG;
return ADC_LL_CTRL_DIG;
#elif SOC_ADC_RTC_CTRL_SUPPORTED
return ADC_LL_CTRL_RTC;
return ADC_LL_CTRL_RTC;
#endif
case ADC_HAL_CONTINUOUS_READ_MODE:
return ADC_LL_CTRL_DIG;
default:
abort();
case ADC_HAL_CONTINUOUS_READ_MODE:
return ADC_LL_CTRL_DIG;
default:
abort();
}
} else {
switch (work_mode) {
#if SOC_ULP_HAS_ADC || SOC_LP_CORE_SUPPORT_LP_ADC
case ADC_HAL_LP_MODE:
return ADC_LL_CTRL_ULP;
case ADC_HAL_LP_MODE:
return ADC_LL_CTRL_ULP;
#endif
#if !SOC_ADC_ARBITER_SUPPORTED //No ADC2 arbiter on ESP32
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
default:
return ADC_LL_CTRL_DIG;
default:
return ADC_LL_CTRL_DIG;
#else
case ADC_HAL_SINGLE_READ_MODE:
return ADC_LL_CTRL_RTC;
case ADC_HAL_CONTINUOUS_READ_MODE:
return ADC_LL_CTRL_DIG;
case ADC_HAL_PWDET_MODE:
return ADC_LL_CTRL_PWDET;
default:
abort();
case ADC_HAL_SINGLE_READ_MODE:
return ADC_LL_CTRL_RTC;
case ADC_HAL_CONTINUOUS_READ_MODE:
return ADC_LL_CTRL_DIG;
case ADC_HAL_PWDET_MODE:
return ADC_LL_CTRL_PWDET;
default:
abort();
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
#else
default:
return ADC_LL_CTRL_ARB;
default:
return ADC_LL_CTRL_ARB;
#endif
}
}
@@ -66,7 +66,6 @@ void adc_hal_set_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
adc_ll_set_controller(unit, ctrlr);
}
/*---------------------------------------------------------------
Arbiter
---------------------------------------------------------------*/
@@ -78,7 +77,6 @@ void adc_hal_arbiter_config(adc_arbiter_t *config)
}
#endif // #if SOC_ADC_ARBITER_SUPPORTED
/*---------------------------------------------------------------
ADC calibration setting
---------------------------------------------------------------*/
@@ -125,7 +123,7 @@ static uint32_t read_cal_channel(adc_unit_t adc_n)
adc_oneshot_ll_start(adc_n);
#endif
while(!adc_oneshot_ll_get_event(event));
while (!adc_oneshot_ll_get_event(event));
uint32_t read_val = -1;
read_val = adc_oneshot_ll_get_raw_result(adc_n);
@@ -191,8 +189,8 @@ uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool inte
chk_code = code_h + code_l;
uint32_t ret = ((code_sum - chk_code) % (ADC_HAL_CAL_TIMES - 2) < 4)
? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
: (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
: (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
adc_ll_calibration_finish(adc_n);
return ret;
components/hal/adc_oneshot_hal.c → components/esp_hal_ana_conv/adc_oneshot_hal.c
+1 -1
View File
@@ -110,7 +110,7 @@ static void adc_hal_onetime_start(adc_unit_t unit, uint32_t clk_src_freq_hz, uin
HAL_EARLY_LOGD(TAG, "clk_src_freq_hz: %"PRIu32", adc_ctrl_clk: %"PRIu32", sample_delay_us: %"PRIu32"", clk_src_freq_hz, adc_ctrl_clk, sample_delay_us);
//This coefficient (8) is got from test, and verified from DT. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
if (adc_ctrl_clk >= APB_CLK_FREQ/8) {
if (adc_ctrl_clk >= APB_CLK_FREQ / 8) {
sample_delay_us = 0;
}
components/soc/esp32/adc_periph.c → components/esp_hal_ana_conv/esp32/adc_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
components/soc/esp32/dac_periph.c → components/esp_hal_ana_conv/esp32/dac_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
/*
Bunch of constants for DAC peripheral: GPIO number
components/hal/esp32/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32/include/hal/adc_ll.h
+36 -36
View File
@@ -11,7 +11,7 @@
#include "hal/adc_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "soc/sens_reg.h"
@@ -254,20 +254,20 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
uint8_t bit_width;
switch (table.bit_width) {
case 9:
bit_width = 0x0;
break;
case 10:
bit_width = 0x1;
break;
case 11:
bit_width = 0x2;
break;
case 12:
bit_width = 0x3;
break;
default:
bit_width = 0x3;
case 9:
bit_width = 0x0;
break;
case 10:
bit_width = 0x1;
break;
case 11:
bit_width = 0x2;
break;
case 12:
bit_width = 0x3;
break;
default:
bit_width = 0x3;
}
pattern.val = (table.atten & 0x3) | ((bit_width) << 2) | ((table.channel & 0xF) << 4);
@@ -363,23 +363,23 @@ static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth
{
uint32_t reg_val = 0;
switch (bits) {
case ADC_BITWIDTH_9:
reg_val = 0;
break;
case ADC_BITWIDTH_10:
reg_val = 1;
break;
case ADC_BITWIDTH_11:
reg_val = 2;
break;
case ADC_BITWIDTH_12:
reg_val = 3;
break;
case ADC_BITWIDTH_DEFAULT:
reg_val = 3;
break;
default:
HAL_ASSERT(false);
case ADC_BITWIDTH_9:
reg_val = 0;
break;
case ADC_BITWIDTH_10:
reg_val = 1;
break;
case ADC_BITWIDTH_11:
reg_val = 2;
break;
case ADC_BITWIDTH_12:
reg_val = 3;
break;
case ADC_BITWIDTH_DEFAULT:
reg_val = 3;
break;
default:
HAL_ASSERT(false);
}
if (adc_n == ADC_UNIT_1) {
SENS.sar_start_force.sar1_bit_width = reg_val;
@@ -526,9 +526,9 @@ static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten1 = (SENS.sar_atten1 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten2 = (SENS.sar_atten2 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
}
}
@@ -604,7 +604,7 @@ __attribute__((always_inline))
static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{
if (adc_n == ADC_UNIT_1) {
switch ( ctrl ) {
switch (ctrl) {
case ADC_LL_CTRL_RTC:
SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas_start1.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
@@ -630,7 +630,7 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
break;
}
} else { // adc_n == ADC_UNIT_2
switch ( ctrl ) {
switch (ctrl) {
case ADC_LL_CTRL_RTC:
SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
components/hal/esp32/include/hal/dac_ll.h → components/esp_hal_ana_conv/esp32/include/hal/dac_ll.h
+1 -1
View File
@@ -15,7 +15,7 @@
#include <stdlib.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "hal/dac_types.h"
components/soc/esp32c2/adc_periph.c → components/esp_hal_ana_conv/esp32c2/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][5] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
components/hal/esp32c2/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c2/include/hal/adc_ll.h
+18 -18
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
@@ -266,23 +266,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
components/esp_hal_ana_conv/esp32c3/adc_periph.c
+19
View File
@@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[2][5] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
},
/* ADC2 */
{
ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1
}
};
components/hal/esp32c3/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c3/include/hal/adc_ll.h
+19 -20
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
@@ -363,23 +363,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -513,8 +513,7 @@ static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
static inline void adc_ll_digi_dma_clr_eof(void)
{
uint32_t eof_num = HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num);
for (int i = 0; i <= eof_num; i++)
{
for (int i = 0; i <= eof_num; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, i);
}
}
components/soc/esp32c5/adc_periph.c → components/esp_hal_ana_conv/esp32c5/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][6] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
components/hal/esp32c5/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c5/include/hal/adc_ll.h
+29 -31
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -331,17 +331,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
@@ -380,23 +380,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -732,7 +732,6 @@ static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
return ret_val;
}
/**
* Analyze whether the obtained raw data is correct.
* ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data.
@@ -814,7 +813,6 @@ static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t chann
return (adc_atten_t)APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten;
}
/*---------------------------------------------------------------
Calibration
---------------------------------------------------------------*/
components/soc/esp32c6/adc_periph.c → components/esp_hal_ana_conv/esp32c6/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][7] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
components/hal/esp32c6/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c6/include/hal/adc_ll.h
+29 -29
View File
@@ -10,7 +10,7 @@
#include "esp_attr.h"
#include "esp_rom_sys.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -331,17 +331,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
@@ -380,23 +380,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
components/soc/esp32c61/adc_periph.c → components/esp_hal_ana_conv/esp32c61/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][4] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
components/hal/esp32c61/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c61/include/hal/adc_ll.h
+29 -30
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -333,17 +333,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
ADC.saradc_ctrl.saradc_sar_clk_gated = 1;
@@ -382,23 +382,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -868,7 +868,6 @@ static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
return ret_val;
}
/**
* Analyze whether the obtained raw data is correct.
* ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data.
components/soc/esp32h2/adc_periph.c → components/esp_hal_ana_conv/esp32h2/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][5] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
components/hal/esp32h2/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32h2/include/hal/adc_ll.h
+29 -29
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -331,17 +331,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_PLL_F96M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_PLL_F96M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
@@ -380,23 +380,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
components/soc/esp32p4/adc_periph.c → components/esp_hal_ana_conv/esp32p4/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[2][8] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM,
components/hal/esp32p4/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32p4/include/hal/adc_ll.h
+67 -72
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/adc_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst_struct.h"
@@ -225,17 +225,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
ADC.ctrl_reg.sar_clk_gated = 1;
@@ -274,23 +274,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -362,7 +362,7 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
uint8_t offset = (pattern_index % 4) * 6;
adc_ll_digi_pattern_table_t pattern = {0};
if (table.unit == ADC_UNIT_1){
if (table.unit == ADC_UNIT_1) {
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
tab = ADC.sar1_patt_tab[index].sar1_patt_tab; //Read old register value
tab &= (~(0xFC0000 >> offset)); //Clear old data
@@ -377,13 +377,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
}
}
/**
* Rest pattern table to default value
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
for(int i = 0; i < 4; i++) {
for (int i = 0; i < 4; i++) {
ADC.sar1_patt_tab[i].sar1_patt_tab = 0xffffff;
ADC.sar2_patt_tab[i].sar2_patt_tab = 0xffffff;
}
@@ -573,8 +572,6 @@ static inline void _adc_ll_reset_register(void)
_adc_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
* Set ADC digital controller power management.
*
@@ -651,7 +648,6 @@ static inline void adc_ll_set_power_manage(adc_unit_t adc_n, adc_ll_power_t mana
}
}
/**
* Set ADC module controller.
* There are five SAR ADC controllers:
@@ -667,43 +663,43 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
{
if (adc_n == ADC_UNIT_1) {
switch (ctrl) {
case ADC_LL_CTRL_RTC:
LP_ADC.meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
LP_ADC.meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
LP_ADC.meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
case ADC_LL_CTRL_RTC:
LP_ADC.meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
LP_ADC.meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
LP_ADC.meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
}
} else { // adc_n == ADC_UNIT_2
switch (ctrl) {
case ADC_LL_CTRL_RTC:
LP_ADC.meas2_mux.sar2_rtc_force = 1; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
LP_ADC.meas2_mux.sar2_rtc_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
LP_ADC.meas2_mux.sar2_rtc_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
case ADC_LL_CTRL_RTC:
LP_ADC.meas2_mux.sar2_rtc_force = 1; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
LP_ADC.meas2_mux.sar2_rtc_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
LP_ADC.meas2_mux.sar2_rtc_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
}
}
}
@@ -1028,7 +1024,6 @@ static inline void adc_ll_rtc_reset(void)
LPPERI.reset_en.rst_en_lp_adc = 0;
}
/**
* Set the attenuation of a particular channel on ADCn.
*
@@ -1065,9 +1060,9 @@ static inline void adc_ll_rtc_reset(void)
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_UNIT_1) {
LP_ADC.atten1.sar1_atten = ( LP_ADC.atten1.sar1_atten & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
LP_ADC.atten1.sar1_atten = (LP_ADC.atten1.sar1_atten & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_UNIT_2
LP_ADC.atten2.sar2_atten = ( LP_ADC.atten2.sar2_atten & ~(0x3 << ((channel + 2) * 2)) ) | ((atten & 0x3) << ((channel + 2) * 2));
LP_ADC.atten2.sar2_atten = (LP_ADC.atten2.sar2_atten & ~(0x3 << ((channel + 2) * 2))) | ((atten & 0x3) << ((channel + 2) * 2));
}
}
components/soc/esp32s2/adc_periph.c → components/esp_hal_ana_conv/esp32s2/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[2][10] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM,
components/soc/esp32s2/dac_periph.c → components/esp_hal_ana_conv/esp32s2/dac_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
/*
Bunch of constants for DAC peripheral: GPIO number
components/hal/esp32s2/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32s2/include/hal/adc_ll.h
+6 -7
View File
@@ -8,7 +8,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#include "hal/assert.h"
@@ -252,7 +252,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
for(int i = 0; i < 4; i++) {
for (int i = 0; i < 4; i++) {
APB_SARADC.sar1_patt_tab[i] = 0xffffff;
APB_SARADC.sar2_patt_tab[i] = 0xffffff;
}
@@ -507,9 +507,9 @@ static inline void adc_ll_digi_monitor_set_mode(adc_monitor_id_t monitor_id, boo
static inline void adc_ll_digi_monitor_set_thres(adc_monitor_id_t monitor_id, adc_unit_t adc_n, uint8_t channel, int32_t h_thresh, int32_t l_thresh)
{
if (monitor_id == ADC_MONITOR_0) {
APB_SARADC.thres_ctrl.adc1_thres = (h_thresh == -1)? l_thresh : h_thresh;
APB_SARADC.thres_ctrl.adc1_thres = (h_thresh == -1) ? l_thresh : h_thresh;
} else { // monitor_id == ADC_MONITOR_1
APB_SARADC.thres_ctrl.adc2_thres = (h_thresh == -1)? l_thresh : h_thresh;
APB_SARADC.thres_ctrl.adc2_thres = (h_thresh == -1) ? l_thresh : h_thresh;
}
adc_ll_digi_monitor_set_mode(monitor_id, l_thresh == -1);
}
@@ -889,9 +889,9 @@ static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten1 = (SENS.sar_atten1 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten2 = (SENS.sar_atten2 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
}
}
@@ -1294,7 +1294,6 @@ static inline void adc_ll_regi2c_adc_deinit(void)
adc_ll_enable_calibration_ref(ADC_UNIT_2, false);
}
/* Temp code end. */
/**
components/hal/esp32s2/include/hal/dac_ll.h → components/esp_hal_ana_conv/esp32s2/include/hal/dac_ll.h
+1 -1
View File
@@ -15,7 +15,7 @@
#include <stdlib.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
#include "hal/dac_types.h"
#include "soc/apb_saradc_struct.h"
#include "soc/sens_struct.h"
components/soc/esp32s3/adc_periph.c → components/esp_hal_ana_conv/esp32s3/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[2][10] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM,
components/hal/esp32s3/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32s3/include/hal/adc_ll.h
+49 -50
View File
@@ -8,7 +8,7 @@
#include <stdio.h>
#include <stdbool.h>
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#include "hal/assert.h"
@@ -143,7 +143,6 @@ typedef struct {
#pragma pack(pop)
#endif /* _MSC_VER */
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
@@ -260,7 +259,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
for(int i = 0; i < 4; i++) {
for (int i = 0; i < 4; i++) {
APB_SARADC.sar1_patt_tab[i].sar1_patt_tab = 0xffffff;
APB_SARADC.sar2_patt_tab[i].sar2_patt_tab = 0xffffff;
}
@@ -284,7 +283,7 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
adc_ll_digi_pattern_table_t pattern = {0};
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
if (table.unit == ADC_UNIT_1){
if (table.unit == ADC_UNIT_1) {
tab = APB_SARADC.sar1_patt_tab[index].sar1_patt_tab; //Read old register value
tab &= (~(0xFC0000 >> offset)); //Clear old data
tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data
@@ -428,23 +427,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -691,37 +690,37 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
{
if (adc_n == ADC_UNIT_1) {
switch (ctrl) {
case ADC_LL_CTRL_RTC:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
SENS.sar_meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
case ADC_LL_CTRL_RTC:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
SENS.sar_meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
}
} else { // adc_n == ADC_UNIT_2
//If ADC2 is not controlled by ULP, the arbiter will decide which controller to use ADC2.
switch (ctrl) {
case ADC_LL_CTRL_ARB:
SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
SENS.sar_meas2_ctrl2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
case ADC_LL_CTRL_ARB:
SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
SENS.sar_meas2_ctrl2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
}
}
}
@@ -1237,9 +1236,9 @@ static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten1 = (SENS.sar_atten1 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten2 = (SENS.sar_atten2 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
}
}
components/hal/include/hal/adc_hal.h → components/esp_hal_ana_conv/include/hal/adc_hal.h
-1
View File
@@ -78,7 +78,6 @@ typedef struct adc_hal_digi_ctrlr_cfg_t {
uint32_t clk_src_freq_hz; ///< Clock source frequency in hz
} adc_hal_digi_ctrlr_cfg_t;
/*---------------------------------------------------------------
PWDET(Power detect) controller setting
---------------------------------------------------------------*/
components/hal/include/hal/adc_hal_common.h → components/esp_hal_ana_conv/include/hal/adc_hal_common.h
-2
View File
@@ -13,7 +13,6 @@
extern "C" {
#endif
/**
* This header file is only for hardware abstract concepts and APIs
* used by both ADC RTC controller and Digital controller
@@ -92,7 +91,6 @@ uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool inte
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
#ifdef __cplusplus
}
#endif
components/hal/include/hal/adc_oneshot_hal.h → components/esp_hal_ana_conv/include/hal/adc_oneshot_hal.h
-2
View File
@@ -14,7 +14,6 @@
extern "C" {
#endif
typedef struct sens_dev_t *adc_oneshot_soc_handle_t;
typedef struct adc_oneshot_hal_cfg_t {
@@ -84,7 +83,6 @@ void adc_oneshot_hal_setup(adc_oneshot_hal_ctx_t *hal, adc_channel_t channel);
*/
bool adc_oneshot_hal_convert(adc_oneshot_hal_ctx_t *hal, int *out_raw);
#ifdef __cplusplus
}
#endif
components/soc/include/soc/adc_periph.h → components/esp_hal_ana_conv/include/hal/adc_periph.h
View File
components/hal/include/hal/adc_types.h → components/esp_hal_ana_conv/include/hal/adc_types.h
View File
components/hal/include/hal/adc_types_private.h → components/esp_hal_ana_conv/include/hal/adc_types_private.h
-1
View File
@@ -10,7 +10,6 @@
extern "C" {
#endif
#if SOC_ADC_ARBITER_SUPPORTED
/*---------------------------------------------------------------
Arbiter
components/soc/include/soc/dac_periph.h → components/esp_hal_ana_conv/include/hal/dac_periph.h
View File
components/hal/include/hal/dac_types.h → components/esp_hal_ana_conv/include/hal/dac_types.h
+5
View File
@@ -1,3 +1,8 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
components/esp_hw_support/CMakeLists.txt
+3
View File
@@ -243,3 +243,6 @@ if(${target} STREQUAL "esp32p4")
# for mipi_csi_share_hw_ctrl.c
idf_component_optional_requires(PRIVATE esp_hal_cam)
endif()
# Required in `adc_share_hw_ctrl.h`
idf_component_optional_requires(PUBLIC esp_hal_ana_conv)
components/hal/CMakeLists.txt
-13
View File
@@ -5,11 +5,6 @@ set(srcs "hal_utils.c")
set(includes "platform_port/include")
set(requires)
if(${target} STREQUAL "esp32")
# TODO: IDF-14079 remove this dependency when ADC hal is graduated from the common hal component
list(APPEND requires esp_hal_i2s)
endif()
# target specific include must be added before the generic one
# because of the "include_next" directive used by the efuse_hal.h
list(APPEND includes "${target}/include")
@@ -121,14 +116,6 @@ elseif(NOT BOOTLOADER_BUILD)
list(APPEND srcs "etm_hal.c" "${target}/etm_periph.c")
endif()
if(CONFIG_SOC_ADC_SUPPORTED)
list(APPEND srcs "adc_hal_common.c" "adc_oneshot_hal.c")
if(CONFIG_SOC_ADC_DMA_SUPPORTED)
list(APPEND srcs "adc_hal.c")
endif()
endif()
if(CONFIG_SOC_ECC_SUPPORTED)
list(APPEND srcs "ecc_hal.c")
endif()
components/soc/CMakeLists.txt
-8
View File
@@ -64,10 +64,6 @@ if(target STREQUAL "esp32")
list(APPEND srcs "${target_folder}/dport_access.c")
endif()
if(CONFIG_SOC_ADC_SUPPORTED)
list(APPEND srcs "${target_folder}/adc_periph.c")
endif()
if(CONFIG_SOC_DEBUG_PROBE_SUPPORTED)
list(APPEND srcs "${target_folder}/debug_probe_periph.c")
endif()
@@ -114,10 +110,6 @@ if(CONFIG_SOC_IEEE802154_SUPPORTED)
endif()
endif()
if(CONFIG_SOC_DAC_SUPPORTED)
list(APPEND srcs "${target_folder}/dac_periph.c")
endif()
if(CONFIG_SOC_SDIO_SLAVE_SUPPORTED)
list(APPEND srcs "${target_folder}/sdio_slave_periph.c")
endif()
components/soc/esp32c3/adc_periph.c
-27
View File
@@ -1,27 +0,0 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include "soc/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
},
/* ADC2 */
{
ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1
}
};
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core_adc.c
+1 -1
View File
@@ -10,7 +10,7 @@
#include "lp_core_test_app_adc.h"
#include "ulp_lp_core.h"
#include "ulp_lp_core_lp_adc_shared.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "driver/temperature_sensor.h"
docs/doxygen/Doxyfile
+2 -2
View File
@@ -163,6 +163,8 @@ INPUT = \
$(PROJECT_PATH)/components/esp_eth/include/esp_eth.h \
$(PROJECT_PATH)/components/esp_event/include/esp_event_base.h \
$(PROJECT_PATH)/components/esp_event/include/esp_event.h \
$(PROJECT_PATH)/components/esp_hal_ana_conv/include/hal/adc_types.h \
$(PROJECT_PATH)/components/esp_hal_ana_conv/include/hal/dac_types.h \
$(PROJECT_PATH)/components/esp_hal_gpio/include/hal/gpio_types.h \
$(PROJECT_PATH)/components/esp_hal_gpio/include/hal/rtc_io_types.h \
$(PROJECT_PATH)/components/esp_hal_gpio/include/hal/sdm_types.h \
@@ -258,9 +260,7 @@ INPUT = \
$(PROJECT_PATH)/components/freertos/FreeRTOS-Kernel/include/freertos/stream_buffer.h \
$(PROJECT_PATH)/components/freertos/FreeRTOS-Kernel/include/freertos/task.h \
$(PROJECT_PATH)/components/freertos/FreeRTOS-Kernel/include/freertos/timers.h \
$(PROJECT_PATH)/components/hal/include/hal/adc_types.h \
$(PROJECT_PATH)/components/hal/include/hal/color_types.h \
$(PROJECT_PATH)/components/hal/include/hal/dac_types.h \
$(PROJECT_PATH)/components/hal/include/hal/ledc_types.h \
$(PROJECT_PATH)/components/hal/include/hal/mcpwm_types.h \
$(PROJECT_PATH)/components/esp_hal_pcnt/include/hal/pcnt_types.h \
docs/en/api-reference/peripherals/dac.rst
+1 -1
View File
@@ -141,4 +141,4 @@ API Reference
.. include-build-file:: inc/dac_cosine.inc
.. include-build-file:: inc/dac_continuous.inc
.. include-build-file:: inc/components/esp_driver_dac/include/driver/dac_types.inc
.. include-build-file:: inc/components/hal/include/hal/dac_types.inc
.. include-build-file:: inc/components/esp_hal_ana_conv/include/hal/dac_types.inc
docs/zh_CN/api-reference/peripherals/dac.rst
+1 -1
View File
@@ -141,4 +141,4 @@ API 参考
.. include-build-file:: inc/dac_cosine.inc
.. include-build-file:: inc/dac_continuous.inc
.. include-build-file:: inc/components/esp_driver_dac/include/driver/dac_types.inc
.. include-build-file:: inc/components/hal/include/hal/dac_types.inc
.. include-build-file:: inc/components/esp_hal_ana_conv/include/hal/dac_types.inc
tools/ci/check_copyright_ignore.txt
-1
View File
@@ -461,7 +461,6 @@ components/fatfs/src/ff.h
components/fatfs/src/ffconf.h
components/fatfs/src/ffsystem.c
components/fatfs/src/ffunicode.c
components/hal/include/hal/dac_types.h
components/hal/spi_slave_hal.c
components/hal/spi_slave_hal_iram.c
components/idf_test/include/idf_performance.h