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refactor(parlio): refactor of the private parlio caps

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This commit is contained in:
laokaiyao
2025-11-17 18:59:08 +08:00
parent 377c4d2f39
commit 873d90218c
30 changed files with 83 additions and 153 deletions
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components/esp_driver_parlio/src/parlio_common.c
+5 -5
View File
@@ -11,8 +11,8 @@
typedef struct parlio_platform_t {
_lock_t mutex; // platform level mutex lock
parlio_group_t *groups[SOC_PARLIO_GROUPS]; // array of parallel IO group instances
int group_ref_counts[SOC_PARLIO_GROUPS]; // reference count used to protect group install/uninstall
parlio_group_t *groups[PARLIO_LL_GET(INST_NUM)]; // array of parallel IO group instances
int group_ref_counts[PARLIO_LL_GET(INST_NUM)]; // reference count used to protect group install/uninstall
} parlio_platform_t;
static parlio_platform_t s_platform; // singleton platform
@@ -110,12 +110,12 @@ esp_err_t parlio_register_unit_to_group(parlio_unit_base_handle_t unit)
{
parlio_group_t *group = NULL;
int unit_id = -1;
for (int i = 0; i < SOC_PARLIO_GROUPS; i++) {
for (int i = 0; i < PARLIO_LL_GET(INST_NUM); i++) {
group = parlio_acquire_group_handle(i);
ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no memory for group (%d)", i);
portENTER_CRITICAL(&group->spinlock);
if (unit->dir == PARLIO_DIR_TX) {
for (int j = 0; j < SOC_PARLIO_TX_UNITS_PER_GROUP; j++) {
for (int j = 0; j < PARLIO_LL_GET(TX_UNITS_PER_INST); j++) {
if (!group->tx_units[j]) {
group->tx_units[j] = unit;
unit_id = j;
@@ -123,7 +123,7 @@ esp_err_t parlio_register_unit_to_group(parlio_unit_base_handle_t unit)
}
}
} else {
for (int j = 0; j < SOC_PARLIO_RX_UNITS_PER_GROUP; j++) {
for (int j = 0; j < PARLIO_LL_GET(RX_UNITS_PER_INST); j++) {
if (!group->rx_units[j]) {
group->rx_units[j] = unit;
unit_id = j;
components/esp_driver_parlio/src/parlio_priv.h
+2 -2
View File
@@ -133,8 +133,8 @@ typedef struct parlio_group_t {
portMUX_TYPE spinlock; // to protect per-group register level concurrent access
parlio_hal_context_t hal; // hal layer context
uint32_t dma_align; // DMA buffer alignment
parlio_unit_base_handle_t tx_units[SOC_PARLIO_TX_UNITS_PER_GROUP]; // tx unit handles
parlio_unit_base_handle_t rx_units[SOC_PARLIO_RX_UNITS_PER_GROUP]; // rx unit handles
parlio_unit_base_handle_t tx_units[PARLIO_LL_GET(TX_UNITS_PER_INST)]; // tx unit handles
parlio_unit_base_handle_t rx_units[PARLIO_LL_GET(RX_UNITS_PER_INST)]; // rx unit handles
} parlio_group_t;
/**
components/esp_driver_parlio/src/parlio_rx.c
+2 -2
View File
@@ -268,14 +268,14 @@ static esp_err_t parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, const
/* When the source clock comes from internal and supported to output the internal clock,
* enable the gpio output direction and connect to the clock output signal */
if (config->clk_out_gpio_num >= 0) {
#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
#if PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO);
// connect the signal to the GPIO by matrix, it will also enable the output path properly
esp_rom_gpio_connect_out_signal(config->clk_out_gpio_num,
parlio_periph_signals.groups[group_id].rx_units[unit_id].clk_out_sig, false, false);
#else
ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "this target not support to output the clock");
#endif // SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
#endif // PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
}
/* Initialize the valid GPIO as input */
components/esp_driver_parlio/src/parlio_tx.c
+6 -6
View File
@@ -520,14 +520,14 @@ static void parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio_tx_trans_
}
} else {
// non-loop transmission
#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#if PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
// for DMA EOF supported target, we need to set the EOF condition to DMA EOF
parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DMA_EOF);
#else
// for DMA EOF not supported target, we need to set the bit length to the configured bit lens
parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DATA_LEN);
parlio_ll_tx_set_trans_bit_len(hal->regs, t->payload_bits);
#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#endif // PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
}
if (tx_unit->bs_handle) {
@@ -641,9 +641,9 @@ esp_err_t parlio_tx_unit_transmit(parlio_tx_unit_handle_t tx_unit, const void *p
ESP_RETURN_ON_FALSE(tx_unit && payload && payload_bits, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE((payload_bits % tx_unit->data_width) == 0, ESP_ERR_INVALID_ARG, TAG, "payload bit length must align to bus width");
ESP_RETURN_ON_FALSE(payload_bits <= tx_unit->max_transfer_bits, ESP_ERR_INVALID_ARG, TAG, "payload bit length too large");
#if !SOC_PARLIO_TRANS_BIT_ALIGN
#if !PARLIO_LL_SUPPORT(TRANS_BIT_ALIGN)
ESP_RETURN_ON_FALSE((payload_bits % 8) == 0, ESP_ERR_INVALID_ARG, TAG, "payload bit length must be multiple of 8");
#endif // !SOC_PARLIO_TRANS_BIT_ALIGN
#endif // !PARLIO_LL_SUPPORT(TRANS_BIT_ALIGN)
#if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
if (config->flags.loop_transmission) {
@@ -654,13 +654,13 @@ esp_err_t parlio_tx_unit_transmit(parlio_tx_unit_handle_t tx_unit, const void *p
ESP_RETURN_ON_FALSE(config->flags.loop_transmission == false, ESP_ERR_NOT_SUPPORTED, TAG, "loop transmission is not supported on this chip");
#endif
#if !SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#if !PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
// check the max payload size if it's not a loop transmission and the DMA EOF is not supported
if (!config->flags.loop_transmission) {
ESP_RETURN_ON_FALSE(tx_unit->max_transfer_bits <= PARLIO_LL_TX_MAX_BITS_PER_FRAME,
ESP_ERR_INVALID_ARG, TAG, "invalid transfer size, max transfer size should be less than %d", PARLIO_LL_TX_MAX_BITS_PER_FRAME / 8);
}
#endif // !SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#endif // !PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
size_t alignment = esp_ptr_external_ram(payload) ? tx_unit->ext_mem_align : tx_unit->int_mem_align;
// check alignment
components/esp_driver_parlio/test_apps/parlio/CMakeLists.txt
+11 -11
View File
@@ -9,17 +9,17 @@ project(parlio_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_parlio/,
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_parlio/
--elf-file ${CMAKE_BINARY_DIR}/parlio_test.elf
find-refs
--from-sections=.iram0.text
--to-sections=.flash.text,.flash.rodata
--exit-code
DEPENDS ${elf}
)
add_custom_target(
check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_parlio/,${CMAKE_BINARY_DIR}/esp-idf/esp_hal_parlio/
--elf-file ${CMAKE_BINARY_DIR}/parlio_test.elf
find-refs
--from-sections=.iram0.text
--to-sections=.flash.text,.flash.rodata
--exit-code
DEPENDS ${elf}
)
endif()
message(STATUS "Checking parlio registers are not read-write by half-word")
components/esp_driver_parlio/test_apps/parlio/main/CMakeLists.txt
+1 -1
View File
@@ -19,7 +19,7 @@ endif()
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity esp_driver_parlio esp_driver_gpio
esp_driver_i2s esp_driver_spi esp_psram
esp_driver_bitscrambler
esp_driver_bitscrambler esp_hal_parlio
WHOLE_ARCHIVE)
if(CONFIG_SOC_BITSCRAMBLER_SUPPORTED)
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c
+2 -2
View File
@@ -202,7 +202,7 @@ TEST_CASE("parlio_tx_bitscrambler_test", "[parlio_bitscrambler]")
test_parlio_bitscrambler();
}
#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#if PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
static void test_parlio_bitscrambler_different_input_output_sizes(void)
{
parlio_tx_unit_handle_t tx_unit = NULL;
@@ -353,4 +353,4 @@ TEST_CASE("parlio_tx_bitscrambler_different_input_output_sizes_test", "[parlio_b
{
test_parlio_bitscrambler_different_input_output_sizes();
}
#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#endif // PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
+6 -5
View File
@@ -21,6 +21,7 @@
#include "soc/soc_caps.h"
#include "soc/spi_periph.h"
#include "hal/parlio_periph.h"
#include "hal/parlio_ll.h"
#include "esp_attr.h"
#include "test_board.h"
#include "esp_private/parlio_rx_private.h"
@@ -29,7 +30,7 @@
#define TEST_I2S_PORT I2S_NUM_0
#define TEST_VALID_SIG (PARLIO_RX_UNIT_MAX_DATA_WIDTH - 1)
#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
#if PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
#define TEST_OUTPUT_CLK_PIN TEST_CLK_GPIO
#else
#define TEST_OUTPUT_CLK_PIN -1
@@ -399,11 +400,11 @@ TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]")
TEST_CASE("parallel_rx_unit_install_uninstall", "[parlio_rx]")
{
printf("install rx units exhaustively\r\n");
parlio_rx_unit_handle_t units[SOC_PARLIO_GROUPS * SOC_PARLIO_RX_UNITS_PER_GROUP];
parlio_rx_unit_handle_t units[PARLIO_LL_GET(INST_NUM) * PARLIO_LL_GET(RX_UNITS_PER_INST)];
int k = 0;
parlio_rx_unit_config_t config = TEST_DEFAULT_UNIT_CONFIG(PARLIO_CLK_SRC_DEFAULT, 1000000);
for (int i = 0; i < SOC_PARLIO_GROUPS; i++) {
for (int j = 0; j < SOC_PARLIO_RX_UNITS_PER_GROUP; j++) {
for (int i = 0; i < PARLIO_LL_GET(INST_NUM); i++) {
for (int j = 0; j < PARLIO_LL_GET(RX_UNITS_PER_INST); j++) {
TEST_ESP_OK(parlio_new_rx_unit(&config, &units[k++]));
}
}
@@ -421,7 +422,7 @@ TEST_CASE("parallel_rx_unit_install_uninstall", "[parlio_rx]")
// clock from internal
config.clk_src = PARLIO_CLK_SRC_DEFAULT;
config.clk_out_gpio_num = TEST_CLK_GPIO;
#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
#if PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
TEST_ESP_OK(parlio_new_rx_unit(&config, &units[0]));
TEST_ESP_OK(parlio_del_rx_unit(units[0]));
#else
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c
+5 -5
View File
@@ -19,7 +19,7 @@
TEST_CASE("parallel_tx_unit_install_uninstall", "[parlio_tx]")
{
printf("install tx units exhaustively\r\n");
parlio_tx_unit_handle_t units[SOC_PARLIO_GROUPS * SOC_PARLIO_TX_UNITS_PER_GROUP];
parlio_tx_unit_handle_t units[PARLIO_LL_GET(INST_NUM) * PARLIO_LL_GET(TX_UNITS_PER_INST)];
int k = 0;
parlio_tx_unit_config_t config = {
.clk_src = PARLIO_CLK_SRC_DEFAULT,
@@ -31,8 +31,8 @@ TEST_CASE("parallel_tx_unit_install_uninstall", "[parlio_tx]")
.max_transfer_size = 64,
.valid_gpio_num = -1,
};
for (int i = 0; i < SOC_PARLIO_GROUPS; i++) {
for (int j = 0; j < SOC_PARLIO_TX_UNITS_PER_GROUP; j++) {
for (int i = 0; i < PARLIO_LL_GET(INST_NUM); i++) {
for (int j = 0; j < PARLIO_LL_GET(TX_UNITS_PER_INST); j++) {
TEST_ESP_OK(parlio_new_tx_unit(&config, &units[k++]));
}
}
@@ -649,7 +649,7 @@ TEST_CASE("parlio_tx_loop_transmission", "[parlio_tx]")
}
#endif // SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#if PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
TEST_CASE("parlio_tx can transmit buffer larger than max_size decided by datalen_eof", "[parlio_tx]")
{
printf("install parlio tx unit\r\n");
@@ -695,4 +695,4 @@ TEST_CASE("parlio_tx can transmit buffer larger than max_size decided by datalen
TEST_ESP_OK(parlio_del_tx_unit(tx_unit));
free(buffer);
}
#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#endif // PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
components/esp_hal_parlio/esp32c5/include/hal/parlio_ll.h
+9
View File
@@ -17,6 +17,15 @@
#include "soc/parl_io_struct.h"
#include "hal/parlio_types.h"
#define PARLIO_LL_GET(attr) (PARLIO_LL_ ## attr)
#define PARLIO_LL_SUPPORT(feat) (PARLIO_LL_SUPPORT_ ## feat)
#define PARLIO_LL_INST_NUM 1 /*!< Number of parallel IO peripherals */
#define PARLIO_LL_TX_UNITS_PER_INST 1 /*!< number of TX units in each instance */
#define PARLIO_LL_RX_UNITS_PER_INST 1 /*!< number of RX units in each instance */
#define PARLIO_LL_SUPPORT_RX_CLK_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define PARLIO_LL_SUPPORT_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define PARLIO_LL_SUPPORT_TX_EOF_FROM_DMA 1 /*!< Support to treat DMA EOF as TX unit EOF */
#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
#define PARLIO_LL_RX_MAX_CLK_INT_DIV 0x10000
#define PARLIO_LL_RX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider
components/esp_hal_parlio/esp32c5/parlio_periph.c
+1 -1
View File
@@ -72,7 +72,7 @@ static const regdma_entries_config_t parlio_regs_retention[] = {
.owner = ENTRY(0) | ENTRY(2)
}, \
};
const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
const parlio_reg_retention_info_t parlio_reg_retention_info[PARLIO_LL_GET(INST_NUM)] = {
[0] = {
.regdma_entry_array = parlio_regs_retention,
.array_size = ARRAY_SIZE(parlio_regs_retention),
components/esp_hal_parlio/esp32c6/include/hal/parlio_ll.h
+6
View File
@@ -17,6 +17,12 @@
#include "soc/parl_io_struct.h"
#include "hal/parlio_types.h"
#define PARLIO_LL_GET(attr) (PARLIO_LL_ ## attr)
#define PARLIO_LL_SUPPORT(feat) (PARLIO_LL_SUPPORT_ ## feat)
#define PARLIO_LL_INST_NUM 1 /*!< Number of parallel IO peripherals */
#define PARLIO_LL_TX_UNITS_PER_INST 1 /*!< number of TX units in each instance */
#define PARLIO_LL_RX_UNITS_PER_INST 1 /*!< number of RX units in each instance */
#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
#define PARLIO_LL_RX_MAX_CLK_INT_DIV 0x10000
#define PARLIO_LL_RX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider
components/esp_hal_parlio/esp32c6/parlio_periph.c
+1 -1
View File
@@ -86,7 +86,7 @@ static const regdma_entries_config_t parlio_regs_retention[] = {
.owner = ENTRY(0) | ENTRY(2)
}, \
};
const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
const parlio_reg_retention_info_t parlio_reg_retention_info[PARLIO_LL_GET(INST_NUM)] = {
[0] = {
.regdma_entry_array = parlio_regs_retention,
.array_size = ARRAY_SIZE(parlio_regs_retention),
components/esp_hal_parlio/esp32h2/include/hal/parlio_ll.h
+8
View File
@@ -19,6 +19,14 @@
#include "soc/parl_io_struct.h"
#include "hal/parlio_types.h"
#define PARLIO_LL_GET(attr) (PARLIO_LL_ ## attr)
#define PARLIO_LL_SUPPORT(feat) (PARLIO_LL_SUPPORT_ ## feat)
#define PARLIO_LL_INST_NUM 1 /*!< Number of parallel IO peripherals */
#define PARLIO_LL_TX_UNITS_PER_INST 1 /*!< number of TX units in each instance */
#define PARLIO_LL_RX_UNITS_PER_INST 1 /*!< number of RX units in each instance */
#define PARLIO_LL_SUPPORT_RX_CLK_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define PARLIO_LL_SUPPORT_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
#define PARLIO_LL_RX_MAX_CLK_INT_DIV 0x10000
#define PARLIO_LL_RX_MAX_CLK_FRACT_DIV 0 // Not support fractional divider
components/esp_hal_parlio/esp32h2/parlio_periph.c
+1 -1
View File
@@ -72,7 +72,7 @@ static const regdma_entries_config_t parlio_regs_retention[] = {
.owner = ENTRY(0) | ENTRY(2)
}, \
};
const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
const parlio_reg_retention_info_t parlio_reg_retention_info[PARLIO_LL_GET(INST_NUM)] = {
[0] = {
.regdma_entry_array = parlio_regs_retention,
.array_size = ARRAY_SIZE(parlio_regs_retention),
components/esp_hal_parlio/esp32p4/include/hal/parlio_ll.h
+8
View File
@@ -19,6 +19,14 @@
#include "soc/lp_clkrst_struct.h"
#include "soc/parl_io_struct.h"
#define PARLIO_LL_GET(attr) (PARLIO_LL_ ## attr)
#define PARLIO_LL_SUPPORT(feat) (PARLIO_LL_SUPPORT_ ## feat)
#define PARLIO_LL_INST_NUM 1 /*!< Number of parallel IO peripherals */
#define PARLIO_LL_TX_UNITS_PER_INST 1 /*!< number of TX units in each instance */
#define PARLIO_LL_RX_UNITS_PER_INST 1 /*!< number of RX units in each instance */
#define PARLIO_LL_SUPPORT_RX_CLK_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define PARLIO_LL_SUPPORT_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define PARLIO_LL_RX_MAX_BYTES_PER_FRAME 0xFFFF
#define PARLIO_LL_RX_MAX_CLK_INT_DIV 0x100
#define PARLIO_LL_RX_MAX_CLK_FRACT_DIV 0x100
components/esp_hal_parlio/esp32p4/parlio_periph.c
+1 -1
View File
@@ -88,7 +88,7 @@ static const regdma_entries_config_t parlio_regs_retention[] = {
.owner = ENTRY(0)
},
};
const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS] = {
const parlio_reg_retention_info_t parlio_reg_retention_info[PARLIO_LL_GET(INST_NUM)] = {
[0] = {
.regdma_entry_array = parlio_regs_retention,
.array_size = ARRAY_SIZE(parlio_regs_retention),
components/esp_hal_parlio/include/hal/parlio_periph.h
+6 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,6 +12,7 @@
#if SOC_PARLIO_SUPPORTED
#include "soc/parl_io_reg.h"
#include "soc/parl_io_struct.h"
#include "hal/parlio_ll.h"
#endif
#include "soc/regdma.h"
#if SOC_PARLIO_SUPPORT_SLEEP_RETENTION
@@ -30,17 +31,17 @@ typedef struct {
const int clk_out_sig;
const int clk_in_sig;
const int cs_sig;
} tx_units[SOC_PARLIO_TX_UNITS_PER_GROUP];
} tx_units[PARLIO_LL_GET(TX_UNITS_PER_INST)];
struct {
const int data_sigs[SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH];
const int clk_out_sig;
const int clk_in_sig;
} rx_units[SOC_PARLIO_RX_UNITS_PER_GROUP];
} rx_units[PARLIO_LL_GET(RX_UNITS_PER_INST)];
const int tx_irq_id;
const int rx_irq_id;
const shared_periph_module_t module;
const char *module_name;
} groups[SOC_PARLIO_GROUPS];
} groups[PARLIO_LL_GET(INST_NUM)];
} parlio_signal_conn_t;
extern const parlio_signal_conn_t parlio_periph_signals;
@@ -52,7 +53,7 @@ typedef struct {
uint32_t array_size;
} parlio_reg_retention_info_t;
extern const parlio_reg_retention_info_t parlio_reg_retention_info[SOC_PARLIO_GROUPS];
extern const parlio_reg_retention_info_t parlio_reg_retention_info[PARLIO_LL_GET(INST_NUM)];
#endif // SOC_PARLIO_SUPPORT_SLEEP_RETENTION
#endif
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-24
View File
@@ -899,18 +899,6 @@ config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_PARLIO_GROUPS
int
default 1
config SOC_PARLIO_TX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_RX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
int
default 8
@@ -927,22 +915,10 @@ config SOC_PARLIO_RX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
bool
default y
config SOC_PARLIO_TRANS_BIT_ALIGN
bool
default y
config SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
bool
default y
config SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
bool
default y
config SOC_PARLIO_SUPPORT_SLEEP_RETENTION
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
-6
View File
@@ -365,17 +365,11 @@
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
/*-------------------------- PARLIO CAPS --------------------------------------*/
#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission */
#define SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA 1 /*!< Support to treat DMA EOF as TX unit EOF */
#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1 /*!< Support back up registers before sleep */
#define SOC_PARLIO_SUPPORT_I80_LCD 1 /*!< Support to drive I80 interfaced LCD */
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
-12
View File
@@ -827,18 +827,6 @@ config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_PARLIO_GROUPS
int
default 1
config SOC_PARLIO_TX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_RX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
int
default 16
components/soc/esp32c6/include/soc/soc_caps.h
-3
View File
@@ -336,9 +336,6 @@
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
/*-------------------------- PARLIO CAPS --------------------------------------*/
#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_RX_SHARE_INTERRUPT 1 /*!< TX and RX unit share the same interrupt source number */
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
-20
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@@ -819,18 +819,6 @@ config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_PARLIO_GROUPS
int
default 1
config SOC_PARLIO_TX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_RX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
int
default 8
@@ -847,14 +835,6 @@ config SOC_PARLIO_RX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
bool
default y
config SOC_PARLIO_TRANS_BIT_ALIGN
bool
default y
config SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
-5
View File
@@ -349,15 +349,10 @@
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
/*-------------------------- PARLIO CAPS --------------------------------------*/
#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission. Note, 1 data-width loop transmission only avliable in chip version above 1.2 */
#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1 /*!< Support back up registers before sleep */
components/soc/esp32h21/include/soc/soc_caps.h
-5
View File
@@ -327,15 +327,10 @@
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
/*-------------------------- PARLIO CAPS --------------------------------------*/
// #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
// #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
// #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
// #define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
// #define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
// #define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
// #define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
/*--------------------------- MPI CAPS ---------------------------------------*/
#define SOC_MPI_MEM_BLOCKS_NUM (4)
components/soc/esp32h4/include/soc/soc_caps.h
-3
View File
@@ -345,9 +345,6 @@
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
/*-------------------------- PARLIO CAPS --------------------------------------*/
// #define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
// #define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
// #define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
// #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the TX unit */
// #define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 8 /*!< Number of data lines of the RX unit */
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-20
View File
@@ -1259,18 +1259,6 @@ config SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO
bool
default y
config SOC_PARLIO_GROUPS
int
default 1
config SOC_PARLIO_TX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_RX_UNITS_PER_GROUP
int
default 1
config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
int
default 16
@@ -1287,14 +1275,6 @@ config SOC_PARLIO_RX_CLK_SUPPORT_GATING
bool
default y
config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
bool
default y
config SOC_PARLIO_TRANS_BIT_ALIGN
bool
default y
config SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
-5
View File
@@ -465,15 +465,10 @@
#define SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO 1
/*-------------------------- PARLIO CAPS --------------------------------------*/
#define SOC_PARLIO_GROUPS 1U /*!< Number of parallel IO peripherals */
#define SOC_PARLIO_TX_UNITS_PER_GROUP 1U /*!< number of TX units in each group */
#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */
#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */
#define SOC_PARLIO_TX_CLK_SUPPORT_GATING 1 /*!< Support gating TX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_GATING 1 /*!< Support gating RX clock */
#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
#define SOC_PARLIO_TRANS_BIT_ALIGN 1 /*!< Support bit alignment in transaction */
#define SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION 1 /*!< Support loop transmission */
#define SOC_PARLIO_SUPPORT_SLEEP_RETENTION 1 /*!< Support back up registers before sleep */
#define SOC_PARLIO_SUPPORT_I80_LCD 1 /*!< Support to drive I80 interfaced LCD */
docs/en/api-reference/peripherals/parlio/parlio_tx.rst
+1 -1
View File
@@ -321,7 +321,7 @@ The waveform of the external clock input is shown below:
After writing the BitScrambler program, we can enable it by calling :cpp:func:`parlio_tx_unit_decorate_bitscrambler`. And configure the :cpp:member:`parlio_transmit_config_t::bitscrambler_program` to point to the binary file of the BitScrambler program. Different transmission transactions can use different BitScrambler programs. The binary file must conform to the BitScrambler assembly language specification, and will be loaded into the BitScrambler's instruction memory at runtime. For details on how to write and compile the BitScrambler program, please refer to :doc:`BitScrambler Programming Guide </api-reference/peripherals/bitscrambler>`.
.. only:: not SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
.. only:: esp32p4
.. note::
docs/zh_CN/api-reference/peripherals/parlio/parlio_tx.rst
+1 -1
View File
@@ -321,7 +321,7 @@ TX 单元可以选择各种不同的时钟源，其中外部时钟源较为特
编写好比特调节器程序后，通过调用 :cpp:func:`parlio_tx_unit_decorate_bitscrambler` 启用比特调节器。并在 :cpp:member:`parlio_transmit_config_t::bitscrambler_program` 配置本次传输使用比特调节器程序的二进制文件。不同的传输事务可以使用不同的比特调节器程序。该二进制文件必须符合比特调节器的汇编语言规范，并且在运行时会被加载到比特调节器的指令存储器中。如何编写并编译比特调节器程序请参考 :doc:`比特调节器编程指南 </api-reference/peripherals/bitscrambler>`。
.. only:: not SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
.. only:: esp32p4
.. note::