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Merge branch 'feature/graduate_i2s_parlio_analog_hal_components_v6.0' into 'release/v6.0'

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Feature/graduate i2s parlio analog hal components v6.0

See merge request espressif/esp-idf!44043
This commit is contained in:
morris
2025-12-11 16:58:37 +08:00
parent 49aa2d5bd7 11ce7a9011
commit 946dcf73e3
234 changed files with 1733 additions and 1626 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/bootloader_support/CMakeLists.txt
+4 -2
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@@ -73,7 +73,8 @@ if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_RAM)
set(include_dirs "include" "bootloader_flash/include"
"private_include")
set(priv_requires micro-ecc spi_flash efuse esp_bootloader_format esp_app_format esptool_py)
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio)
# `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_ana_conv)
list(APPEND srcs
"src/bootloader_init.c"
"src/bootloader_clock_loader.c"
@@ -90,7 +91,8 @@ else()
set(priv_include_dirs "private_include")
# heap is required for `heap_memory_layout.h` header
set(priv_requires spi_flash mbedtls efuse heap esp_bootloader_format esp_app_format esptool_py)
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio)
# `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_ana_conv)
endif()
if(BOOTLOADER_BUILD)
components/bootloader_support/src/bootloader_random_esp32.c
+2 -1
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@@ -9,7 +9,8 @@
#include "soc/sens_reg.h"
#include "soc/syscon_reg.h"
#include "soc/dport_reg.h"
#include "soc/i2s_periph.h"
#include "soc/i2s_reg.h"
#include "soc/periph_defs.h"
#include "esp_log.h"
#include "soc/io_mux_reg.h"
components/bootloader_support/src/bootloader_random_esp32s2.c
-1
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@@ -9,7 +9,6 @@
#include "soc/sens_reg.h"
#include "soc/dport_reg.h"
#include "soc/syscon_reg.h"
#include "soc/i2s_periph.h"
#include "esp_log.h"
#include "soc/apb_saradc_reg.h"
#include "esp_private/regi2c_ctrl.h"
components/driver/CMakeLists.txt
+1 -1
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@@ -45,7 +45,7 @@ else()
idf_component_register(SRCS "${srcs}"
INCLUDE_DIRS ${includes}
PRIV_REQUIRES esp_timer esp_mm esp_driver_gpio esp_ringbuf esp_pm
REQUIRES esp_hal_i2c esp_hal_twai
REQUIRES esp_hal_i2c esp_hal_twai esp_hal_touch_sens
LDFRAGMENTS ${ldfragments}
)
endif()
components/driver/test_apps/.build-test-rules.yml
+2 -1
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@@ -25,13 +25,14 @@ components/driver/test_apps/touch_element:
- if: IDF_TARGET not in ["esp32s2", "esp32s3"]
reason: only supports esp32s2 and esp32s3
depends_filepatterns:
- components/soc/**/touch_sensor_periph.h
- components/soc/esp32s2/**/rtc_cntl_*
- components/soc/esp32s3/**/rtc_cntl_*
- components/soc/esp32s2/**/rtc_io_struct.h
- components/soc/esp32s3/**/rtc_io_struct.h
- components/soc/esp32s2/**/sens_struct.h
- components/soc/esp32s3/**/sens_struct.h
depends_components:
- esp_hal_touch_sens
components/driver/test_apps/touch_sensor_v1:
disable:
components/driver/touch_sensor/esp32/touch_sensor.c
+4 -4
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@@ -11,7 +11,7 @@
#include "esp_log.h"
#include "sys/lock.h"
#include "soc/rtc.h"
#include "soc/soc_caps_full.h"
#include "soc/soc_caps.h"
#include "soc/periph_defs.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
@@ -29,7 +29,7 @@
#endif
#include "sys/queue.h"
#include "hal/touch_sensor_legacy_types.h"
#include "hal/touch_sensor_hal.h"
#include "hal/touch_sensor_legacy_hal.h"
typedef struct {
esp_timer_handle_t timer;
@@ -52,8 +52,8 @@ static SemaphoreHandle_t rtc_touch_mux = NULL;
static __attribute__((unused)) const char *TOUCH_TAG = "TOUCH_SENSOR";
#define TOUCH_CHANNEL_CHECK(channel) ESP_RETURN_ON_FALSE(channel < SOC_MODULE_ATTR(TOUCH, CHAN_NUM), ESP_ERR_INVALID_ARG, TOUCH_TAG, "Touch channel error");
#define TOUCH_CHANNEL_CHECK_ISR(channel) ESP_RETURN_ON_FALSE_ISR(channel < SOC_MODULE_ATTR(TOUCH, CHAN_NUM), ESP_ERR_INVALID_ARG, TOUCH_TAG, "Touch channel error");
#define TOUCH_CHANNEL_CHECK(channel) ESP_RETURN_ON_FALSE(channel < TOUCH_LL_GET(CHAN_NUM), ESP_ERR_INVALID_ARG, TOUCH_TAG, "Touch channel error");
#define TOUCH_CHANNEL_CHECK_ISR(channel) ESP_RETURN_ON_FALSE_ISR(channel < TOUCH_LL_GET(CHAN_NUM), ESP_ERR_INVALID_ARG, TOUCH_TAG, "Touch channel error");
#define TOUCH_NULL_POINTER_CHECK(p, name) ESP_RETURN_ON_FALSE((p), ESP_ERR_INVALID_ARG, TOUCH_TAG, "input param '"name"' is NULL")
#define TOUCH_NULL_POINTER_CHECK_ISR(p, name) ESP_RETURN_ON_FALSE_ISR((p), ESP_ERR_INVALID_ARG, TOUCH_TAG, "input param '"name"' is NULL")
#define TOUCH_PARAM_CHECK_STR(s) ""s" parameter error"
components/driver/touch_sensor/esp32s2/touch_sensor.c
+8 -8
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@@ -10,7 +10,7 @@
#include "esp_log.h"
#include "sys/lock.h"
#include "soc/soc_pins.h"
#include "soc/soc_caps_full.h"
#include "soc/soc_caps.h"
#include "soc/rtc_cntl_reg.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
@@ -24,7 +24,7 @@
#include "esp_check.h"
#include "hal/touch_sensor_legacy_types.h"
#include "hal/touch_sensor_hal.h"
#include "hal/touch_sensor_legacy_hal.h"
#ifndef NDEBUG
// Enable built-in checks in queue.h in debug builds
@@ -40,8 +40,8 @@
static __attribute__((unused)) const char *TOUCH_TAG = "TOUCH_SENSOR";
#define TOUCH_CHANNEL_CHECK(channel) do { \
ESP_RETURN_ON_FALSE(channel < SOC_MODULE_ATTR(TOUCH, CHAN_NUM) && channel >= 0, ESP_ERR_INVALID_ARG, TOUCH_TAG, "Touch channel error"); \
ESP_RETURN_ON_FALSE(channel != SOC_TOUCH_DENOISE_CHANNEL, ESP_ERR_INVALID_ARG, TOUCH_TAG, "TOUCH0 is internal denoise channel"); \
ESP_RETURN_ON_FALSE(channel < TOUCH_LL_GET(CHAN_NUM) && channel >= 0, ESP_ERR_INVALID_ARG, TOUCH_TAG, "Touch channel error"); \
ESP_RETURN_ON_FALSE(channel != TOUCH_LL_GET(DENOISE_CHAN_ID), ESP_ERR_INVALID_ARG, TOUCH_TAG, "TOUCH0 is internal denoise channel"); \
} while (0);
#define TOUCH_CH_MASK_CHECK(mask) ESP_RETURN_ON_FALSE((mask <= TOUCH_PAD_BIT_MASK_ALL), ESP_ERR_INVALID_ARG, TOUCH_TAG, "touch channel bitmask error");
#define TOUCH_INTR_MASK_CHECK(mask) ESP_RETURN_ON_FALSE(mask & TOUCH_PAD_INTR_MASK_ALL, ESP_ERR_INVALID_ARG, TOUCH_TAG, "intr mask error");
@@ -422,7 +422,7 @@ esp_err_t touch_pad_filter_disable(void)
esp_err_t touch_pad_denoise_enable(void)
{
TOUCH_ENTER_CRITICAL();
touch_hal_clear_channel_mask(BIT(SOC_TOUCH_DENOISE_CHANNEL));
touch_hal_clear_channel_mask(BIT(TOUCH_LL_GET(DENOISE_CHAN_ID)));
touch_hal_denoise_enable();
TOUCH_EXIT_CRITICAL();
return ESP_OK;
@@ -447,7 +447,7 @@ esp_err_t touch_pad_denoise_set_config(const touch_pad_denoise_t *denoise)
.tie_opt = TOUCH_PAD_TIE_OPT_DEFAULT,
};
TOUCH_ENTER_CRITICAL();
touch_hal_set_meas_mode(SOC_TOUCH_DENOISE_CHANNEL, &meas);
touch_hal_set_meas_mode(TOUCH_LL_GET(DENOISE_CHAN_ID), &meas);
touch_hal_denoise_set_config(denoise);
TOUCH_EXIT_CRITICAL();
@@ -473,7 +473,7 @@ esp_err_t touch_pad_denoise_read_data(uint32_t *data)
esp_err_t touch_pad_waterproof_set_config(const touch_pad_waterproof_t *waterproof)
{
TOUCH_NULL_POINTER_CHECK(waterproof, "waterproof");
ESP_RETURN_ON_FALSE(waterproof->guard_ring_pad < SOC_MODULE_ATTR(TOUCH, CHAN_NUM), ESP_ERR_INVALID_ARG, TOUCH_TAG, TOUCH_PARAM_CHECK_STR("pad"));
ESP_RETURN_ON_FALSE(waterproof->guard_ring_pad < TOUCH_LL_GET(CHAN_NUM), ESP_ERR_INVALID_ARG, TOUCH_TAG, TOUCH_PARAM_CHECK_STR("pad"));
ESP_RETURN_ON_FALSE(waterproof->shield_driver < TOUCH_PAD_SHIELD_DRV_MAX, ESP_ERR_INVALID_ARG, TOUCH_TAG, TOUCH_PARAM_CHECK_STR("shield_driver"));
TOUCH_ENTER_CRITICAL();
@@ -493,7 +493,7 @@ esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof)
esp_err_t touch_pad_waterproof_enable(void)
{
touch_pad_io_init(SOC_TOUCH_SHIELD_CHANNEL);
touch_pad_io_init(TOUCH_LL_GET(SHIELD_CHAN_ID));
TOUCH_ENTER_CRITICAL();
touch_hal_waterproof_enable();
TOUCH_EXIT_CRITICAL();
components/driver/touch_sensor/esp32s3/touch_sensor.c
+8 -8
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@@ -10,7 +10,7 @@
#include "esp_log.h"
#include "sys/lock.h"
#include "soc/soc_pins.h"
#include "soc/soc_caps_full.h"
#include "soc/soc_caps.h"
#include "soc/rtc_cntl_reg.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
@@ -24,7 +24,7 @@
#include "esp_check.h"
#include "hal/touch_sensor_legacy_types.h"
#include "hal/touch_sensor_hal.h"
#include "hal/touch_sensor_legacy_hal.h"
#ifndef NDEBUG
// Enable built-in checks in queue.h in debug builds
@@ -40,8 +40,8 @@
static __attribute__((unused)) const char *TOUCH_TAG = "TOUCH_SENSOR";
#define TOUCH_CHANNEL_CHECK(channel) do { \
ESP_RETURN_ON_FALSE(channel < SOC_MODULE_ATTR(TOUCH, CHAN_NUM) && channel >= 0, ESP_ERR_INVALID_ARG, TOUCH_TAG, "Touch channel error"); \
ESP_RETURN_ON_FALSE(channel != SOC_TOUCH_DENOISE_CHANNEL, ESP_ERR_INVALID_ARG, TOUCH_TAG, "TOUCH0 is internal denoise channel"); \
ESP_RETURN_ON_FALSE(channel < TOUCH_LL_GET(CHAN_NUM) && channel >= 0, ESP_ERR_INVALID_ARG, TOUCH_TAG, "Touch channel error"); \
ESP_RETURN_ON_FALSE(channel != TOUCH_LL_GET(DENOISE_CHAN_ID), ESP_ERR_INVALID_ARG, TOUCH_TAG, "TOUCH0 is internal denoise channel"); \
} while (0);
#define TOUCH_CH_MASK_CHECK(mask) ESP_RETURN_ON_FALSE((mask <= TOUCH_PAD_BIT_MASK_ALL), ESP_ERR_INVALID_ARG, TOUCH_TAG, "touch channel bitmask error");
#define TOUCH_INTR_MASK_CHECK(mask) ESP_RETURN_ON_FALSE(mask & TOUCH_PAD_INTR_MASK_ALL, ESP_ERR_INVALID_ARG, TOUCH_TAG, "intr mask error");
@@ -396,7 +396,7 @@ esp_err_t touch_pad_filter_disable(void)
esp_err_t touch_pad_denoise_enable(void)
{
TOUCH_ENTER_CRITICAL();
touch_hal_clear_channel_mask(BIT(SOC_TOUCH_DENOISE_CHANNEL));
touch_hal_clear_channel_mask(BIT(TOUCH_LL_GET(DENOISE_CHAN_ID)));
touch_hal_denoise_enable();
TOUCH_EXIT_CRITICAL();
return ESP_OK;
@@ -421,7 +421,7 @@ esp_err_t touch_pad_denoise_set_config(const touch_pad_denoise_t *denoise)
.tie_opt = TOUCH_PAD_TIE_OPT_DEFAULT,
};
TOUCH_ENTER_CRITICAL();
touch_hal_set_meas_mode(SOC_TOUCH_DENOISE_CHANNEL, &meas);
touch_hal_set_meas_mode(TOUCH_LL_GET(DENOISE_CHAN_ID), &meas);
touch_hal_denoise_set_config(denoise);
TOUCH_EXIT_CRITICAL();
@@ -446,7 +446,7 @@ esp_err_t touch_pad_denoise_read_data(uint32_t *data)
esp_err_t touch_pad_waterproof_set_config(const touch_pad_waterproof_t *waterproof)
{
TOUCH_NULL_POINTER_CHECK(waterproof, "waterproof");
ESP_RETURN_ON_FALSE(waterproof->guard_ring_pad < SOC_MODULE_ATTR(TOUCH, CHAN_NUM), ESP_ERR_INVALID_ARG, TOUCH_TAG, TOUCH_PARAM_CHECK_STR("pad"));
ESP_RETURN_ON_FALSE(waterproof->guard_ring_pad < TOUCH_LL_GET(CHAN_NUM), ESP_ERR_INVALID_ARG, TOUCH_TAG, TOUCH_PARAM_CHECK_STR("pad"));
ESP_RETURN_ON_FALSE(waterproof->shield_driver < TOUCH_PAD_SHIELD_DRV_MAX, ESP_ERR_INVALID_ARG, TOUCH_TAG, TOUCH_PARAM_CHECK_STR("shield_driver"));
TOUCH_ENTER_CRITICAL();
@@ -466,7 +466,7 @@ esp_err_t touch_pad_waterproof_get_config(touch_pad_waterproof_t *waterproof)
esp_err_t touch_pad_waterproof_enable(void)
{
touch_pad_io_init(SOC_TOUCH_SHIELD_CHANNEL);
touch_pad_io_init(TOUCH_LL_GET(SHIELD_CHAN_ID));
TOUCH_ENTER_CRITICAL();
touch_hal_waterproof_enable();
TOUCH_EXIT_CRITICAL();
components/driver/touch_sensor/touch_sensor_common.c
+10 -10
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@@ -11,7 +11,7 @@
#include "esp_log.h"
#include "sys/lock.h"
#include "soc/soc_pins.h"
#include "soc/soc_caps_full.h"
#include "soc/soc_caps.h"
#include "freertos/FreeRTOS.h"
#include "freertos/semphr.h"
#include "freertos/timers.h"
@@ -19,7 +19,7 @@
#include "esp_private/rtc_ctrl.h"
#include "esp_private/gpio.h"
#include "hal/touch_sensor_legacy_types.h"
#include "hal/touch_sensor_hal.h"
#include "hal/touch_sensor_legacy_hal.h"
static const char *TOUCH_TAG = "TOUCH_SENSOR";
#define TOUCH_CHECK(a, str, ret_val) ({ \
@@ -30,18 +30,18 @@ static const char *TOUCH_TAG = "TOUCH_SENSOR";
})
#ifdef CONFIG_IDF_TARGET_ESP32
#define TOUCH_CHANNEL_CHECK(channel) do { \
TOUCH_CHECK(channel < SOC_MODULE_ATTR(TOUCH, CHAN_NUM) && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \
TOUCH_CHECK(channel < TOUCH_LL_GET(CHAN_NUM) && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \
} while (0);
#else // !CONFIG_IDF_TARGET_ESP32
#define TOUCH_CHANNEL_CHECK(channel) do { \
TOUCH_CHECK(channel < SOC_MODULE_ATTR(TOUCH, CHAN_NUM) && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \
TOUCH_CHECK(channel != SOC_TOUCH_DENOISE_CHANNEL, "TOUCH0 is internal denoise channel", ESP_ERR_INVALID_ARG); \
TOUCH_CHECK(channel < TOUCH_LL_GET(CHAN_NUM) && channel >= 0, "Touch channel error", ESP_ERR_INVALID_ARG); \
TOUCH_CHECK(channel != TOUCH_LL_GET(DENOISE_CHAN_ID), "TOUCH0 is internal denoise channel", ESP_ERR_INVALID_ARG); \
} while (0);
#endif // CONFIG_IDF_TARGET_ESP32
#define TOUCH_GET_IO_NUM(channel) (touch_sensor_channel_io_map[channel])
_Static_assert(TOUCH_PAD_MAX == SOC_MODULE_ATTR(TOUCH, CHAN_NUM), "Touch sensor channel number not equal to chip capabilities");
_Static_assert(TOUCH_PAD_MAX == TOUCH_LL_GET(CHAN_NUM), "Touch sensor channel number not equal to chip capabilities");
extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
#define TOUCH_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
@@ -88,7 +88,7 @@ esp_err_t touch_pad_get_voltage(touch_high_volt_t *refh, touch_low_volt_t *refl,
esp_err_t touch_pad_set_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t slope, touch_tie_opt_t opt)
{
TOUCH_CHECK(touch_num < SOC_MODULE_ATTR(TOUCH, CHAN_NUM), "Touch channel error", ESP_ERR_INVALID_ARG);
TOUCH_CHECK(touch_num < TOUCH_LL_GET(CHAN_NUM), "Touch channel error", ESP_ERR_INVALID_ARG);
TOUCH_CHECK(slope < TOUCH_PAD_SLOPE_MAX, "touch slope error", ESP_ERR_INVALID_ARG);
TOUCH_CHECK(opt < TOUCH_PAD_TIE_OPT_MAX, "touch opt error", ESP_ERR_INVALID_ARG);
@@ -105,7 +105,7 @@ esp_err_t touch_pad_set_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t slope,
esp_err_t touch_pad_get_cnt_mode(touch_pad_t touch_num, touch_cnt_slope_t *slope, touch_tie_opt_t *opt)
{
TOUCH_CHECK(touch_num < SOC_MODULE_ATTR(TOUCH, CHAN_NUM), "Touch channel error", ESP_ERR_INVALID_ARG);
TOUCH_CHECK(touch_num < TOUCH_LL_GET(CHAN_NUM), "Touch channel error", ESP_ERR_INVALID_ARG);
touch_hal_meas_mode_t meas = {0};
TOUCH_ENTER_CRITICAL();
@@ -184,7 +184,7 @@ esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint16_t threshold)
esp_err_t touch_pad_set_thresh(touch_pad_t touch_num, uint32_t threshold)
{
TOUCH_CHANNEL_CHECK(touch_num);
TOUCH_CHECK(touch_num != SOC_TOUCH_DENOISE_CHANNEL,
TOUCH_CHECK(touch_num != TOUCH_LL_GET(DENOISE_CHAN_ID),
"TOUCH0 is internal denoise channel", ESP_ERR_INVALID_ARG);
TOUCH_ENTER_CRITICAL();
touch_hal_set_threshold(touch_num, threshold);
@@ -204,7 +204,7 @@ esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint16_t *threshold)
esp_err_t touch_pad_get_thresh(touch_pad_t touch_num, uint32_t *threshold)
{
TOUCH_CHANNEL_CHECK(touch_num);
TOUCH_CHECK(touch_num != SOC_TOUCH_DENOISE_CHANNEL,
TOUCH_CHECK(touch_num != TOUCH_LL_GET(DENOISE_CHAN_ID),
"TOUCH0 is internal denoise channel", ESP_ERR_INVALID_ARG);
touch_hal_get_threshold(touch_num, threshold);
return ESP_OK;
components/esp_adc/CMakeLists.txt
+1
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@@ -57,4 +57,5 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
PRIV_REQUIRES esp_driver_gpio efuse esp_pm esp_ringbuf esp_mm ${extra_requires}
REQUIRES esp_hal_ana_conv
LDFRAGMENTS linker.lf)
components/esp_adc/adc_common.c
+1 -1
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@@ -16,7 +16,7 @@
#include "hal/adc_hal.h"
#include "hal/adc_hal_common.h"
#include "esp_private/regi2c_ctrl.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "hal/adc_ll.h"
static const char *TAG = "adc_common";
components/esp_adc/adc_oneshot.c
+1 -1
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@@ -30,7 +30,7 @@
#include "hal/adc_types.h"
#include "hal/adc_oneshot_hal.h"
#include "hal/adc_ll.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/soc_caps.h"
#if CONFIG_ADC_ONESHOT_CTRL_FUNC_IN_IRAM
components/esp_adc/esp32/adc_dma.c
+1 -1
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@@ -14,7 +14,7 @@
#include "hal/i2s_types.h"
#include "driver/i2s_types.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "esp_private/i2s_platform.h"
#include "esp_private/adc_dma.h"
#include "hal/i2s_ll.h"
components/esp_adc/linker.lf
+1 -1
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@@ -11,7 +11,7 @@ entries:
esp_clk_tree: esp_clk_tree_enable_src (noflash)
[mapping:adc_hal]
archive: libhal.a
archive: libesp_hal_ana_conv.a
entries:
if ADC_ONESHOT_CTRL_FUNC_IN_IRAM = y:
adc_oneshot_hal (noflash)
components/esp_adc/test_apps/adc/CMakeLists.txt
+10 -1
View File
@@ -11,9 +11,18 @@ project(adc_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(ADC_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_adc
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_ana_conv
)
string(JOIN "," ADC_RTL_DIRS_JOINED ${ADC_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_adc/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${ADC_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/adc_test.elf
find-refs
--from-sections=.iram0.text
components/esp_adc/test_apps/adc/main/test_adc.c
+1 -1
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@@ -9,7 +9,7 @@
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "esp_adc/adc_oneshot.h"
#include "esp_adc/adc_monitor.h"
#include "driver/gpio.h"
components/esp_adc/test_apps/adc/main/test_adc_performance.c
+1 -1
View File
@@ -11,7 +11,7 @@
#include "esp_log.h"
#include "esp_err.h"
#include "esp_cpu.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "esp_adc/adc_oneshot.h"
components/esp_adc/test_apps/adc/main/test_adc_tsens.c
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdlib.h>
#include <string.h>
#include "esp_log.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "esp_adc/adc_oneshot.h"
#include "esp_adc/adc_continuous.h"
#include "driver/gpio.h"
components/esp_adc/test_apps/adc/main/test_adc_wifi.c
+1 -1
View File
@@ -8,7 +8,7 @@
#include <stdlib.h>
#include <string.h>
#include "esp_log.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "esp_adc/adc_oneshot.h"
#include "driver/gpio.h"
#include "driver/rtc_io.h"
components/esp_adc/test_apps/adc/main/test_common_adc.c
+1 -1
View File
@@ -11,7 +11,7 @@
#include "freertos/task.h"
#include "driver/gpio.h"
#include "driver/rtc_io.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "test_common_adc.h"
#include "hal/adc_ll.h"
components/esp_driver_ana_cmpr/CMakeLists.txt
+1
View File
@@ -19,5 +19,6 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS "include"
PRIV_REQUIRES "${priv_requires}"
REQUIRES esp_hal_ana_cmpr
LDFRAGMENTS "linker.lf"
)
components/esp_driver_ana_cmpr/ana_cmpr_private.h
+1 -1
View File
@@ -24,7 +24,7 @@
#include "driver/ana_cmpr_types.h"
#include "soc/soc_caps.h"
#include "hal/ana_cmpr_ll.h"
#include "soc/ana_cmpr_periph.h"
#include "hal/ana_cmpr_periph.h"
#define TAG "ana_cmpr"
components/esp_driver_ana_cmpr/test_apps/analog_comparator/CMakeLists.txt
+9 -1
View File
@@ -9,9 +9,17 @@ project(test_ana_cmpr)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(ANA_CMPR_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_ana_cmpr
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_ana_cmpr
)
string(JOIN "," ANA_CMPR_RTL_DIRS_JOINED ${ANA_CMPR_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_ana_cmpr/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${ANA_CMPR_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/test_ana_cmpr.elf
find-refs
--from-sections=.iram0.text
components/esp_driver_dac/CMakeLists.txt
+1
View File
@@ -28,5 +28,6 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS "./include"
PRIV_REQUIRES ${priv_req}
REQUIRES esp_hal_ana_conv
LDFRAGMENTS "linker.lf"
)
components/esp_driver_dac/dac_common.c
+1 -1
View File
@@ -8,7 +8,7 @@
#include <string.h>
#include "freertos/FreeRTOS.h"
#include "soc/soc_caps.h"
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
#include "hal/dac_types.h"
#include "hal/dac_ll.h"
#include "esp_private/gpio.h"
components/esp_driver_dac/esp32/dac_dma.c
+1 -1
View File
@@ -18,7 +18,7 @@
#include "hal/i2s_hal.h"
#include "hal/i2s_types.h"
#include "hal/clk_tree_ll.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "../dac_priv_dma.h"
#include "esp_private/i2s_platform.h"
#include "esp_private/esp_clk.h"
components/esp_driver_dac/test_apps/dac/CMakeLists.txt
+9 -1
View File
@@ -9,9 +9,17 @@ project(dac_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(DAC_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_dac
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_ana_conv
)
string(JOIN "," DAC_RTL_DIRS_JOINED ${DAC_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_dac/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${DAC_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/dac_test.elf
find-refs
--from-sections=.iram0.text
components/esp_driver_dac/test_apps/dac/main/test_dac.c
+1 -1
View File
@@ -18,7 +18,7 @@
#if CONFIG_IDF_TARGET_ESP32
#include "esp_private/i2s_platform.h"
// Following headers are used to test the conversion frequency
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "driver/pulse_cnt.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp_private/spi_common_internal.h"
components/esp_driver_gpio/src/dedic_gpio.c
+1 -1
View File
@@ -15,7 +15,7 @@
#include "esp_log.h"
#include "esp_check.h"
#include "esp_cpu.h"
#include "soc/soc_caps_full.h"
#include "soc/soc_caps.h"
#include "soc/io_mux_reg.h"
#include "hal/dedic_gpio_caps.h"
#include "hal/dedic_gpio_cpu_ll.h"
components/esp_driver_gpio/test_apps/gpio_extensions/main/test_dedicated_gpio.c
+1 -1
View File
@@ -11,7 +11,7 @@
#include "unity.h"
#include "unity_test_utils.h"
#include "esp_rom_sys.h"
#include "soc/soc_caps_full.h"
#include "soc/soc_caps.h"
#include "hal/dedic_gpio_caps.h"
#include "hal/dedic_gpio_periph.h"
#include "hal/dedic_gpio_cpu_ll.h"
components/esp_driver_gpio/test_apps/gpio_extensions/main/test_gpio_filter.c
+1 -1
View File
@@ -12,7 +12,7 @@
#include "unity.h"
#include "driver/gpio_filter.h"
#include "driver/dedic_gpio.h"
#include "soc/soc_caps_full.h"
#include "soc/soc_caps.h"
#if CONFIG_IDF_TARGET_ESP32P4
#define TEST_FILTER_GPIO 20
components/esp_driver_i2s/CMakeLists.txt
+8 -1
View File
@@ -6,6 +6,12 @@ endif()
set(srcs)
set(include "include")
set(priv_requires esp_driver_gpio esp_pm esp_mm)
if(${target} STREQUAL "esp32")
# ADC on esp32 is routed to I2S0, I2S driver needs to operate ADC to ensure the I2S function.
list(APPEND priv_requires esp_hal_ana_conv)
endif()
# I2S related source files
if(CONFIG_SOC_I2S_SUPPORTED)
@@ -36,6 +42,7 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${include}
PRIV_REQUIRES esp_driver_gpio esp_pm esp_mm
PRIV_REQUIRES ${priv_requires}
REQUIRES esp_hal_i2s
LDFRAGMENTS linker.lf
)
components/esp_driver_i2s/i2s_common.c
+11 -12
View File
@@ -21,9 +21,8 @@
#endif
#include "esp_log.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "soc/soc_caps.h"
#include "soc/soc_caps_full.h"
#include "hal/i2s_hal.h"
#include "hal/hal_utils.h"
#include "hal/dma_types.h"
@@ -227,13 +226,13 @@ static esp_err_t i2s_destroy_controller_obj(i2s_controller_t **i2s_obj)
* @param id i2s port id
* @param search_reverse reverse the sequence of port acquirement
* set false to acquire from I2S_NUM_0 first
* set true to acquire from SOC_I2S_ATTR(INST_NUM) - 1 first
* set true to acquire from I2S_LL_GET(INST_NUM) - 1 first
* @return
* - pointer of acquired i2s controller object
*/
static i2s_controller_t *i2s_acquire_controller_obj(int id)
{
if (id < 0 || id >= SOC_I2S_ATTR(INST_NUM)) {
if (id < 0 || id >= I2S_LL_GET(INST_NUM)) {
return NULL;
}
/* pre-alloc controller object */
@@ -792,17 +791,17 @@ esp_err_t i2s_init_dma_intr(i2s_chan_handle_t handle, int intr_flag)
{
esp_err_t ret = ESP_OK;
int port_id = handle->controller->id;
ESP_RETURN_ON_FALSE((port_id >= 0) && (port_id < SOC_I2S_ATTR(INST_NUM)), ESP_ERR_INVALID_ARG, TAG, "invalid handle");
ESP_RETURN_ON_FALSE((port_id >= 0) && (port_id < I2S_LL_GET(INST_NUM)), ESP_ERR_INVALID_ARG, TAG, "invalid handle");
/* Set GDMA trigger module */
gdma_trigger_t trig = {.periph = GDMA_TRIG_PERIPH_I2S};
switch (port_id) {
#if SOC_I2S_ATTR(INST_NUM) > 2
#if I2S_LL_GET(INST_NUM) > 2
case I2S_NUM_2:
trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S2;
break;
#endif
#if SOC_I2S_ATTR(INST_NUM) > 1
#if I2S_LL_GET(INST_NUM) > 1
case I2S_NUM_1:
trig.instance_id = SOC_GDMA_TRIG_PERIPH_I2S1;
break;
@@ -863,7 +862,7 @@ esp_err_t i2s_init_dma_intr(i2s_chan_handle_t handle, int intr_flag)
{
esp_err_t ret = ESP_OK;
int port_id = handle->controller->id;
ESP_RETURN_ON_FALSE((port_id >= 0) && (port_id < SOC_I2S_ATTR(INST_NUM)), ESP_ERR_INVALID_ARG, TAG, "invalid handle");
ESP_RETURN_ON_FALSE((port_id >= 0) && (port_id < I2S_LL_GET(INST_NUM)), ESP_ERR_INVALID_ARG, TAG, "invalid handle");
intr_flag |= handle->intr_prio_flags;
/* Initialize I2S module interrupt */
if (handle->dir == I2S_DIR_TX) {
@@ -985,7 +984,7 @@ esp_err_t i2s_new_channel(const i2s_chan_config_t *chan_cfg, i2s_chan_handle_t *
/* Parameter validity check */
I2S_NULL_POINTER_CHECK(TAG, chan_cfg);
I2S_NULL_POINTER_CHECK(TAG, tx_handle || rx_handle);
ESP_RETURN_ON_FALSE((chan_cfg->id >= 0 && chan_cfg->id < SOC_I2S_ATTR(INST_NUM)) || chan_cfg->id == I2S_NUM_AUTO, ESP_ERR_INVALID_ARG, TAG, "invalid I2S port id");
ESP_RETURN_ON_FALSE((chan_cfg->id >= 0 && chan_cfg->id < I2S_LL_GET(INST_NUM)) || chan_cfg->id == I2S_NUM_AUTO, ESP_ERR_INVALID_ARG, TAG, "invalid I2S port id");
ESP_RETURN_ON_FALSE(chan_cfg->dma_desc_num >= 2, ESP_ERR_INVALID_ARG, TAG, "there should be at least 2 DMA buffers");
ESP_RETURN_ON_FALSE(chan_cfg->intr_priority >= 0 && chan_cfg->intr_priority <= 7, ESP_ERR_INVALID_ARG, TAG, "intr_priority should be within 0~7");
#if !SOC_HAS(PAU)
@@ -1003,7 +1002,7 @@ esp_err_t i2s_new_channel(const i2s_chan_config_t *chan_cfg, i2s_chan_handle_t *
/* Channel will be registered to one i2s port automatically if id is I2S_NUM_AUTO
* Otherwise, the channel will be registered to the specific port. */
if (id == I2S_NUM_AUTO) {
for (int i = 0; i < SOC_I2S_ATTR(INST_NUM) && !channel_found; i++) {
for (int i = 0; i < I2S_LL_GET(INST_NUM) && !channel_found; i++) {
i2s_obj = i2s_acquire_controller_obj(i);
if (!i2s_obj) {
continue;
@@ -1062,7 +1061,7 @@ esp_err_t i2s_new_channel(const i2s_chan_config_t *chan_cfg, i2s_chan_handle_t *
err:
/* if the controller object has no channel, find the corresponding global object and destroy it */
if (i2s_obj != NULL && i2s_obj->rx_chan == NULL && i2s_obj->tx_chan == NULL) {
for (int i = 0; i < SOC_I2S_ATTR(INST_NUM); i++) {
for (int i = 0; i < I2S_LL_GET(INST_NUM); i++) {
if (i2s_obj == g_i2s.controller[i]) {
i2s_destroy_controller_obj(&g_i2s.controller[i]);
break;
@@ -1173,7 +1172,7 @@ esp_err_t i2s_channel_get_info(i2s_chan_handle_t handle, i2s_chan_info_t *chan_i
I2S_NULL_POINTER_CHECK(TAG, chan_info);
/* Find whether the handle is a registered i2s handle or still available */
for (int i = 0; i < SOC_I2S_ATTR(INST_NUM); i++) {
for (int i = 0; i < I2S_LL_GET(INST_NUM); i++) {
if (g_i2s.controller[i] != NULL) {
if (g_i2s.controller[i]->tx_chan == handle ||
g_i2s.controller[i]->rx_chan == handle) {
components/esp_driver_i2s/i2s_platform.c
+4 -4
View File
@@ -16,8 +16,8 @@ static const char *TAG = "i2s_platform";
*/
i2s_platform_t g_i2s = {
.spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED,
.controller[0 ...(SOC_I2S_ATTR(INST_NUM) - 1)] = NULL, // groups will be lazy installed
.comp_name[0 ...(SOC_I2S_ATTR(INST_NUM) - 1)] = NULL,
.controller[0 ...(I2S_LL_GET(INST_NUM) - 1)] = NULL, // groups will be lazy installed
.comp_name[0 ...(I2S_LL_GET(INST_NUM) - 1)] = NULL,
#if SOC_LP_I2S_SUPPORTED
.lp_controller[0 ...(SOC_LP_I2S_NUM - 1)] = NULL,
.lp_comp_name[0 ...(SOC_LP_I2S_NUM - 1)] = NULL,
@@ -34,7 +34,7 @@ esp_err_t i2s_platform_acquire_occupation(i2s_ctlr_t type, int id, const char *c
{
esp_err_t ret = ESP_OK;
const char *occupied_comp = NULL;
ESP_RETURN_ON_FALSE(id < SOC_I2S_ATTR(INST_NUM), ESP_ERR_INVALID_ARG, TAG, "invalid i2s port id");
ESP_RETURN_ON_FALSE(id < I2S_LL_GET(INST_NUM), ESP_ERR_INVALID_ARG, TAG, "invalid i2s port id");
if (type == I2S_CTLR_HP) {
portENTER_CRITICAL(&g_i2s.spinlock);
@@ -79,7 +79,7 @@ esp_err_t i2s_platform_acquire_occupation(i2s_ctlr_t type, int id, const char *c
esp_err_t i2s_platform_release_occupation(i2s_ctlr_t type, int id)
{
esp_err_t ret = ESP_OK;
ESP_RETURN_ON_FALSE(id < SOC_I2S_ATTR(INST_NUM), ESP_ERR_INVALID_ARG, TAG, "invalid i2s port id");
ESP_RETURN_ON_FALSE(id < I2S_LL_GET(INST_NUM), ESP_ERR_INVALID_ARG, TAG, "invalid i2s port id");
if (type == I2S_CTLR_HP) {
portENTER_CRITICAL(&g_i2s.spinlock);
components/esp_driver_i2s/i2s_private.h
+4 -4
View File
@@ -13,7 +13,7 @@
#include "freertos/queue.h"
#include "soc/lldesc.h"
#include "soc/soc_caps.h"
#include "soc/soc_caps_full.h"
#include "hal/i2s_periph.h"
#include "hal/i2s_hal.h"
#include "hal/lp_i2s_hal.h"
#if SOC_LP_I2S_SUPPORTED
@@ -225,11 +225,11 @@ struct lp_i2s_channel_obj_t {
*/
typedef struct {
portMUX_TYPE spinlock; /*!< Platform level lock */
i2s_controller_t *controller[SOC_I2S_ATTR(INST_NUM)]; /*!< Controller object */
const char *comp_name[SOC_I2S_ATTR(INST_NUM)]; /*!< The component name that occupied i2s controller */
i2s_controller_t *controller[I2S_LL_GET(INST_NUM)]; /*!< Controller object */
const char *comp_name[I2S_LL_GET(INST_NUM)]; /*!< The component name that occupied i2s controller */
#if SOC_LP_I2S_SUPPORTED
lp_i2s_controller_t *lp_controller[SOC_LP_I2S_NUM]; /*!< LP controller object*/
const char *lp_comp_name[SOC_I2S_ATTR(INST_NUM)]; /*!< The component name that occupied lp i2s controller */
const char *lp_comp_name[I2S_LL_GET(INST_NUM)]; /*!< The component name that occupied lp i2s controller */
#endif
} i2s_platform_t;
components/esp_driver_i2s/lp_i2s.c
+1 -1
View File
@@ -28,7 +28,7 @@
#include "esp_private/i2s_platform.h"
#include "esp_private/lp_i2s_private.h"
#include "i2s_private.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#define LP_I2S_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
components/esp_driver_i2s/test_apps/i2s/CMakeLists.txt
+9 -1
View File
@@ -9,9 +9,17 @@ project(i2s_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(I2S_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_i2s
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_i2s
)
string(JOIN "," I2S_RTL_DIRS_JOINED ${I2S_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_i2s/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${I2S_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/i2s_test.elf
find-refs
--from-sections=.iram0.text
components/esp_driver_i2s/test_apps/i2s/main/test_i2s.c
+6 -6
View File
@@ -20,7 +20,7 @@
#include "unity.h"
#include "math.h"
#include "esp_rom_gpio.h"
#include "soc/i2s_periph.h"
#include "hal/i2s_periph.h"
#include "driver/i2s_std.h"
#if SOC_I2S_SUPPORTS_PDM
#include "driver/i2s_pdm.h"
@@ -55,7 +55,7 @@ static void i2s_test_io_config(int mode)
gpio_set_direction(DATA_OUT_IO, GPIO_MODE_INPUT_OUTPUT);
switch (mode) {
#if SOC_I2S_ATTR(INST_NUM) > 1
#if I2S_LL_GET(INST_NUM) > 1
case I2S_TEST_MODE_SLAVE_TO_MASTER: {
esp_rom_gpio_connect_out_signal(MASTER_BCK_IO, i2s_periph_signal[0].m_rx_bck_sig, 0, 0);
esp_rom_gpio_connect_in_signal(MASTER_BCK_IO, i2s_periph_signal[1].s_tx_bck_sig, 0);
@@ -169,14 +169,14 @@ TEST_CASE("I2S_basic_channel_allocation_reconfig_deleting_test", "[i2s]")
/* Exhaust test */
std_cfg.gpio_cfg.mclk = -1;
i2s_chan_handle_t tx_ex[SOC_I2S_ATTR(INST_NUM)] = {};
for (int i = 0; i < SOC_I2S_ATTR(INST_NUM); i++) {
i2s_chan_handle_t tx_ex[I2S_LL_GET(INST_NUM)] = {};
for (int i = 0; i < I2S_LL_GET(INST_NUM); i++) {
TEST_ESP_OK(i2s_new_channel(&chan_cfg, &tx_ex[i], NULL));
TEST_ESP_OK(i2s_channel_init_std_mode(tx_ex[i], &std_cfg));
TEST_ESP_OK(i2s_channel_enable(tx_ex[i]));
}
TEST_ESP_ERR(ESP_ERR_NOT_FOUND, i2s_new_channel(&chan_cfg, &tx_handle, NULL));
for (int i = 0; i < SOC_I2S_ATTR(INST_NUM); i++) {
for (int i = 0; i < I2S_LL_GET(INST_NUM); i++) {
TEST_ESP_OK(i2s_channel_disable(tx_ex[i]));
TEST_ESP_OK(i2s_del_channel(tx_ex[i]));
}
@@ -812,7 +812,7 @@ TEST_CASE("I2S_loopback_test", "[i2s]")
TEST_ESP_OK(i2s_del_channel(rx_handle));
}
#if SOC_I2S_ATTR(INST_NUM) > 1 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#if I2S_LL_GET(INST_NUM) > 1 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
TEST_CASE("I2S_master_write_slave_read_test", "[i2s]")
{
i2s_chan_handle_t tx_handle;
components/esp_driver_i2s/test_apps/i2s/main/test_i2s_sleep.c
+1 -1
View File
@@ -13,7 +13,7 @@
#include "driver/i2s_std.h"
#include "driver/uart.h"
#include "soc/i2s_struct.h"
#include "soc/soc_caps_full.h"
#include "soc/soc_caps.h"
#include "esp_sleep.h"
#include "esp_private/sleep_cpu.h"
#include "esp_private/esp_sleep_internal.h"
components/esp_driver_parlio/CMakeLists.txt
+1
View File
@@ -21,5 +21,6 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${public_include}
PRIV_REQUIRES "${priv_requires}"
REQUIRES esp_hal_parlio
LDFRAGMENTS "linker.lf"
)
components/esp_driver_parlio/linker.lf
+2 -2
View File
@@ -33,8 +33,8 @@ entries:
esp_dma_utils: esp_dma_split_rx_buffer_to_cache_aligned (noflash)
esp_dma_utils: esp_dma_merge_aligned_rx_buffers (noflash)
[mapping:parlio_driver_soc_periph]
archive: libsoc.a
[mapping:parlio_driver_hal_periph]
archive: libesp_hal_parlio.a
entries:
if PARLIO_RX_ISR_HANDLER_IN_IRAM = y:
parlio_periph: parlio_periph_signals (noflash)
components/esp_driver_parlio/src/parlio_common.c
+5 -5
View File
@@ -11,8 +11,8 @@
typedef struct parlio_platform_t {
_lock_t mutex; // platform level mutex lock
parlio_group_t *groups[SOC_PARLIO_GROUPS]; // array of parallel IO group instances
int group_ref_counts[SOC_PARLIO_GROUPS]; // reference count used to protect group install/uninstall
parlio_group_t *groups[PARLIO_LL_GET(INST_NUM)]; // array of parallel IO group instances
int group_ref_counts[PARLIO_LL_GET(INST_NUM)]; // reference count used to protect group install/uninstall
} parlio_platform_t;
static parlio_platform_t s_platform; // singleton platform
@@ -110,12 +110,12 @@ esp_err_t parlio_register_unit_to_group(parlio_unit_base_handle_t unit)
{
parlio_group_t *group = NULL;
int unit_id = -1;
for (int i = 0; i < SOC_PARLIO_GROUPS; i++) {
for (int i = 0; i < PARLIO_LL_GET(INST_NUM); i++) {
group = parlio_acquire_group_handle(i);
ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no memory for group (%d)", i);
portENTER_CRITICAL(&group->spinlock);
if (unit->dir == PARLIO_DIR_TX) {
for (int j = 0; j < SOC_PARLIO_TX_UNITS_PER_GROUP; j++) {
for (int j = 0; j < PARLIO_LL_GET(TX_UNITS_PER_INST); j++) {
if (!group->tx_units[j]) {
group->tx_units[j] = unit;
unit_id = j;
@@ -123,7 +123,7 @@ esp_err_t parlio_register_unit_to_group(parlio_unit_base_handle_t unit)
}
}
} else {
for (int j = 0; j < SOC_PARLIO_RX_UNITS_PER_GROUP; j++) {
for (int j = 0; j < PARLIO_LL_GET(RX_UNITS_PER_INST); j++) {
if (!group->rx_units[j]) {
group->rx_units[j] = unit;
unit_id = j;
components/esp_driver_parlio/src/parlio_priv.h
+3 -3
View File
@@ -27,7 +27,7 @@
#include "freertos/queue.h"
#include "freertos/idf_additions.h"
#include "soc/soc_caps.h"
#include "soc/parlio_periph.h"
#include "hal/parlio_periph.h"
#include "hal/parlio_types.h"
#include "hal/parlio_hal.h"
#include "hal/parlio_ll.h"
@@ -132,8 +132,8 @@ typedef struct parlio_group_t {
portMUX_TYPE spinlock; // to protect per-group register level concurrent access
parlio_hal_context_t hal; // hal layer context
uint32_t dma_align; // DMA buffer alignment
parlio_unit_base_handle_t tx_units[SOC_PARLIO_TX_UNITS_PER_GROUP]; // tx unit handles
parlio_unit_base_handle_t rx_units[SOC_PARLIO_RX_UNITS_PER_GROUP]; // rx unit handles
parlio_unit_base_handle_t tx_units[PARLIO_LL_GET(TX_UNITS_PER_INST)]; // tx unit handles
parlio_unit_base_handle_t rx_units[PARLIO_LL_GET(RX_UNITS_PER_INST)]; // rx unit handles
} parlio_group_t;
/**
components/esp_driver_parlio/src/parlio_rx.c
+2 -2
View File
@@ -268,14 +268,14 @@ static esp_err_t parlio_rx_unit_set_gpio(parlio_rx_unit_handle_t rx_unit, const
/* When the source clock comes from internal and supported to output the internal clock,
* enable the gpio output direction and connect to the clock output signal */
if (config->clk_out_gpio_num >= 0) {
#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
#if PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
gpio_func_sel(config->clk_out_gpio_num, PIN_FUNC_GPIO);
// connect the signal to the GPIO by matrix, it will also enable the output path properly
esp_rom_gpio_connect_out_signal(config->clk_out_gpio_num,
parlio_periph_signals.groups[group_id].rx_units[unit_id].clk_out_sig, false, false);
#else
ESP_RETURN_ON_FALSE(false, ESP_ERR_NOT_SUPPORTED, TAG, "this target not support to output the clock");
#endif // SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
#endif // PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
}
/* Initialize the valid GPIO as input */
components/esp_driver_parlio/src/parlio_tx.c
+6 -6
View File
@@ -520,14 +520,14 @@ static void parlio_tx_do_transaction(parlio_tx_unit_t *tx_unit, parlio_tx_trans_
}
} else {
// non-loop transmission
#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#if PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
// for DMA EOF supported target, we need to set the EOF condition to DMA EOF
parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DMA_EOF);
#else
// for DMA EOF not supported target, we need to set the bit length to the configured bit lens
parlio_ll_tx_set_eof_condition(hal->regs, PARLIO_LL_TX_EOF_COND_DATA_LEN);
parlio_ll_tx_set_trans_bit_len(hal->regs, t->payload_bits);
#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#endif // PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
}
if (tx_unit->bs_handle) {
@@ -641,9 +641,9 @@ esp_err_t parlio_tx_unit_transmit(parlio_tx_unit_handle_t tx_unit, const void *p
ESP_RETURN_ON_FALSE(tx_unit && payload && payload_bits, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE((payload_bits % tx_unit->data_width) == 0, ESP_ERR_INVALID_ARG, TAG, "payload bit length must align to bus width");
ESP_RETURN_ON_FALSE(payload_bits <= tx_unit->max_transfer_bits, ESP_ERR_INVALID_ARG, TAG, "payload bit length too large");
#if !SOC_PARLIO_TRANS_BIT_ALIGN
#if !PARLIO_LL_SUPPORT(TRANS_BIT_ALIGN)
ESP_RETURN_ON_FALSE((payload_bits % 8) == 0, ESP_ERR_INVALID_ARG, TAG, "payload bit length must be multiple of 8");
#endif // !SOC_PARLIO_TRANS_BIT_ALIGN
#endif // !PARLIO_LL_SUPPORT(TRANS_BIT_ALIGN)
#if SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
if (config->flags.loop_transmission) {
@@ -654,13 +654,13 @@ esp_err_t parlio_tx_unit_transmit(parlio_tx_unit_handle_t tx_unit, const void *p
ESP_RETURN_ON_FALSE(config->flags.loop_transmission == false, ESP_ERR_NOT_SUPPORTED, TAG, "loop transmission is not supported on this chip");
#endif
#if !SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#if !PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
// check the max payload size if it's not a loop transmission and the DMA EOF is not supported
if (!config->flags.loop_transmission) {
ESP_RETURN_ON_FALSE(tx_unit->max_transfer_bits <= PARLIO_LL_TX_MAX_BITS_PER_FRAME,
ESP_ERR_INVALID_ARG, TAG, "invalid transfer size, max transfer size should be less than %d", PARLIO_LL_TX_MAX_BITS_PER_FRAME / 8);
}
#endif // !SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#endif // !PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
size_t alignment = esp_ptr_external_ram(payload) ? tx_unit->ext_mem_align : tx_unit->int_mem_align;
// check alignment
components/esp_driver_parlio/test_apps/parlio/CMakeLists.txt
+19 -10
View File
@@ -9,16 +9,25 @@ project(parlio_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_parlio/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--elf-file ${CMAKE_BINARY_DIR}/parlio_test.elf
find-refs
--from-sections=.iram0.text
--to-sections=.flash.text,.flash.rodata
--exit-code
DEPENDS ${elf}
)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(PARLIO_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_parlio
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_parlio
)
string(JOIN "," PARLIO_RTL_DIRS_JOINED ${PARLIO_RTL_DIRS})
add_custom_target(
check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${PARLIO_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/parlio_test.elf
find-refs
--from-sections=.iram0.text
--to-sections=.flash.text,.flash.rodata
--exit-code
DEPENDS ${elf}
)
endif()
message(STATUS "Checking parlio registers are not read-write by half-word")
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_bitscrambler.c
+2 -2
View File
@@ -202,7 +202,7 @@ TEST_CASE("parlio_tx_bitscrambler_test", "[parlio_bitscrambler]")
test_parlio_bitscrambler();
}
#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#if PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
static void test_parlio_bitscrambler_different_input_output_sizes(void)
{
parlio_tx_unit_handle_t tx_unit = NULL;
@@ -353,4 +353,4 @@ TEST_CASE("parlio_tx_bitscrambler_different_input_output_sizes_test", "[parlio_b
{
test_parlio_bitscrambler_different_input_output_sizes();
}
#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#endif // PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_rx.c
+21 -32
View File
@@ -19,9 +19,9 @@
#include "hal/cache_hal.h"
#include "hal/cache_ll.h"
#include "soc/soc_caps.h"
#include "soc/i2s_periph.h"
#include "soc/spi_periph.h"
#include "soc/parlio_periph.h"
#include "hal/parlio_periph.h"
#include "hal/parlio_ll.h"
#include "esp_attr.h"
#include "test_board.h"
#include "esp_private/parlio_rx_private.h"
@@ -30,7 +30,7 @@
#define TEST_I2S_PORT I2S_NUM_0
#define TEST_VALID_SIG (PARLIO_RX_UNIT_MAX_DATA_WIDTH - 1)
#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
#if PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
#define TEST_OUTPUT_CLK_PIN TEST_CLK_GPIO
#else
#define TEST_OUTPUT_CLK_PIN -1
@@ -96,20 +96,6 @@ static bool test_parlio_rx_timeout_callback(parlio_rx_unit_handle_t rx_unit, con
return false;
}
static void connect_signal_internally(uint32_t gpio, uint32_t sigo, uint32_t sigi)
{
gpio_config_t gpio_conf = {
.pin_bit_mask = BIT64(gpio),
.mode = GPIO_MODE_INPUT_OUTPUT,
.intr_type = GPIO_INTR_DISABLE,
.pull_down_en = GPIO_PULLDOWN_DISABLE,
.pull_up_en = GPIO_PULLUP_DISABLE,
};
gpio_config(&gpio_conf);
esp_rom_gpio_connect_out_signal(gpio, sigo, false, false);
esp_rom_gpio_connect_in_signal(gpio, sigi, false);
}
#define TEST_EOF_DATA_LEN 64
static void pulse_delimiter_sender_task_i2s(void *args)
@@ -155,17 +141,6 @@ static void pulse_delimiter_sender_task_i2s(void *args)
// Transmission will start after enable the tx channel
TEST_ESP_OK(i2s_channel_enable(tx_chan));
// Connect GPIO signals
connect_signal_internally(TEST_CLK_GPIO,
i2s_periph_signal[TEST_I2S_PORT].m_tx_bck_sig,
parlio_periph_signals.groups[0].rx_units[0].clk_in_sig);
connect_signal_internally(TEST_VALID_GPIO,
i2s_periph_signal[TEST_I2S_PORT].m_tx_ws_sig,
parlio_periph_signals.groups[0].rx_units[0].data_sigs[TEST_VALID_SIG]);
connect_signal_internally(TEST_DATA0_GPIO,
i2s_periph_signal[TEST_I2S_PORT].data_out_sig,
parlio_periph_signals.groups[0].rx_units[0].data_sigs[0]);
while (!((*task_flags) & TEST_TASK_FINISHED_BIT)) {
vTaskDelay(pdMS_TO_TICKS(1));
*task_flags |= TEST_TASK_DATA_READY_BIT;
@@ -193,6 +168,20 @@ static void cs_low(spi_transaction_t *trans)
#define TEST_SPI_CLK_FREQ 100000
static void connect_signal_internally(uint32_t gpio, uint32_t sigo, uint32_t sigi)
{
gpio_config_t gpio_conf = {
.pin_bit_mask = BIT64(gpio),
.mode = GPIO_MODE_INPUT_OUTPUT,
.intr_type = GPIO_INTR_DISABLE,
.pull_down_en = GPIO_PULLDOWN_DISABLE,
.pull_up_en = GPIO_PULLUP_DISABLE,
};
gpio_config(&gpio_conf);
esp_rom_gpio_connect_out_signal(gpio, sigo, false, false);
esp_rom_gpio_connect_in_signal(gpio, sigi, false);
}
static void level_delimiter_sender_task_spi(void *args)
{
uint32_t *task_flags = (uint32_t *)args;
@@ -411,11 +400,11 @@ TEST_CASE("parallel_rx_unit_pulse_delimiter_test_via_i2s", "[parlio_rx]")
TEST_CASE("parallel_rx_unit_install_uninstall", "[parlio_rx]")
{
printf("install rx units exhaustively\r\n");
parlio_rx_unit_handle_t units[SOC_PARLIO_GROUPS * SOC_PARLIO_RX_UNITS_PER_GROUP];
parlio_rx_unit_handle_t units[PARLIO_LL_GET(INST_NUM) * PARLIO_LL_GET(RX_UNITS_PER_INST)];
int k = 0;
parlio_rx_unit_config_t config = TEST_DEFAULT_UNIT_CONFIG(PARLIO_CLK_SRC_DEFAULT, 1000000);
for (int i = 0; i < SOC_PARLIO_GROUPS; i++) {
for (int j = 0; j < SOC_PARLIO_RX_UNITS_PER_GROUP; j++) {
for (int i = 0; i < PARLIO_LL_GET(INST_NUM); i++) {
for (int j = 0; j < PARLIO_LL_GET(RX_UNITS_PER_INST); j++) {
TEST_ESP_OK(parlio_new_rx_unit(&config, &units[k++]));
}
}
@@ -433,7 +422,7 @@ TEST_CASE("parallel_rx_unit_install_uninstall", "[parlio_rx]")
// clock from internal
config.clk_src = PARLIO_CLK_SRC_DEFAULT;
config.clk_out_gpio_num = TEST_CLK_GPIO;
#if SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
#if PARLIO_LL_SUPPORT(RX_CLK_OUTPUT)
TEST_ESP_OK(parlio_new_rx_unit(&config, &units[0]));
TEST_ESP_OK(parlio_del_rx_unit(units[0]));
#else
components/esp_driver_parlio/test_apps/parlio/main/test_parlio_tx.c
+5 -5
View File
@@ -19,7 +19,7 @@
TEST_CASE("parallel_tx_unit_install_uninstall", "[parlio_tx]")
{
printf("install tx units exhaustively\r\n");
parlio_tx_unit_handle_t units[SOC_PARLIO_GROUPS * SOC_PARLIO_TX_UNITS_PER_GROUP];
parlio_tx_unit_handle_t units[PARLIO_LL_GET(INST_NUM) * PARLIO_LL_GET(TX_UNITS_PER_INST)];
int k = 0;
parlio_tx_unit_config_t config = {
.clk_src = PARLIO_CLK_SRC_DEFAULT,
@@ -31,8 +31,8 @@ TEST_CASE("parallel_tx_unit_install_uninstall", "[parlio_tx]")
.max_transfer_size = 64,
.valid_gpio_num = -1,
};
for (int i = 0; i < SOC_PARLIO_GROUPS; i++) {
for (int j = 0; j < SOC_PARLIO_TX_UNITS_PER_GROUP; j++) {
for (int i = 0; i < PARLIO_LL_GET(INST_NUM); i++) {
for (int j = 0; j < PARLIO_LL_GET(TX_UNITS_PER_INST); j++) {
TEST_ESP_OK(parlio_new_tx_unit(&config, &units[k++]));
}
}
@@ -649,7 +649,7 @@ TEST_CASE("parlio_tx_loop_transmission", "[parlio_tx]")
}
#endif // SOC_PARLIO_TX_SUPPORT_LOOP_TRANSMISSION
#if SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#if PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
TEST_CASE("parlio_tx can transmit buffer larger than max_size decided by datalen_eof", "[parlio_tx]")
{
printf("install parlio tx unit\r\n");
@@ -695,4 +695,4 @@ TEST_CASE("parlio_tx can transmit buffer larger than max_size decided by datalen
TEST_ESP_OK(parlio_del_tx_unit(tx_unit));
free(buffer);
}
#endif // SOC_PARLIO_TX_SUPPORT_EOF_FROM_DMA
#endif // PARLIO_LL_SUPPORT(TX_EOF_FROM_DMA)
components/esp_driver_touch_sens/CMakeLists.txt
+1
View File
@@ -22,5 +22,6 @@ endif()
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES ${priv_require}
REQUIRES esp_hal_touch_sens # public require because hal/touch_sens_type.h needs to be public
INCLUDE_DIRS ${public_inc}
)
components/esp_driver_touch_sens/common/touch_sens_common.c
+1 -1
View File
@@ -11,7 +11,7 @@
#include "soc/soc_caps.h"
#include "soc/rtc.h"
#include "soc/clk_tree_defs.h"
#include "soc/touch_sensor_periph.h"
#include "hal/touch_sensor_periph.h"
#include "esp_private/gpio.h"
#include "driver/touch_sens.h"
#include "esp_private/esp_gpio_reserve.h"
components/esp_driver_touch_sens/common/touch_sens_private.h
+1 -1
View File
@@ -84,7 +84,7 @@ extern portMUX_TYPE g_touch_spinlock;
*
*/
struct touch_sensor_s {
touch_channel_handle_t ch[SOC_MODULE_ATTR(TOUCH, CHAN_NUM)]; /*!< Touch sensor channel handles, will be NULL if the channel is not registered */
touch_channel_handle_t ch[TOUCH_LL_GET(CHAN_NUM)]; /*!< Touch sensor channel handles, will be NULL if the channel is not registered */
uint32_t chan_mask; /*!< Enabled channel mask, corresponding bit will be set if the channel is registered */
uint32_t src_freq_hz; /*!< Source clock frequency */
uint32_t interval_freq_hz; /*!< Frequency of the interval clock */
components/esp_driver_touch_sens/hw_ver1/touch_version_specific.c
+1 -1
View File
@@ -15,7 +15,7 @@
#include "freertos/semphr.h"
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "soc/touch_sensor_periph.h"
#include "hal/touch_sensor_periph.h"
#include "soc/rtc.h"
#include "hal/hal_utils.h"
#include "driver/touch_sens.h"
components/esp_driver_touch_sens/hw_ver2/touch_version_specific.c
+2 -2
View File
@@ -15,7 +15,7 @@
#include "freertos/semphr.h"
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "soc/touch_sensor_periph.h"
#include "hal/touch_sensor_periph.h"
#include "soc/rtc.h"
#include "hal/hal_utils.h"
#include "driver/touch_sens.h"
@@ -68,7 +68,7 @@ void IRAM_ATTR touch_priv_default_intr_handler(void *arg)
return;
}
/* It actually won't be out of range in the real environment, but limit the range to pass the coverity check */
uint32_t curr_chan_offset = (curr_chan >= SOC_MODULE_ATTR(TOUCH, CHAN_NUM) ? SOC_MODULE_ATTR(TOUCH, CHAN_NUM) - 1 : curr_chan) - TOUCH_MIN_CHAN_ID;
uint32_t curr_chan_offset = (curr_chan >= TOUCH_LL_GET(CHAN_NUM) ? TOUCH_LL_GET(CHAN_NUM) - 1 : curr_chan) - TOUCH_MIN_CHAN_ID;
data.chan = g_touch->ch[curr_chan_offset];
/* If the channel is not registered, return directly */
if (!data.chan) {
components/esp_driver_touch_sens/hw_ver3/touch_version_specific.c
+2 -2
View File
@@ -15,7 +15,7 @@
#include "freertos/semphr.h"
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "soc/touch_sensor_periph.h"
#include "hal/touch_sensor_periph.h"
#include "soc/rtc.h"
#include "soc/chip_revision.h"
#include "hal/efuse_hal.h"
@@ -63,7 +63,7 @@ void IRAM_ATTR touch_priv_default_intr_handler(void *arg)
touch_base_event_data_t data;
touch_ll_get_active_channel_mask(&data.status_mask);
int ch_offset = touch_ll_get_current_meas_channel() - TOUCH_MIN_CHAN_ID;
if (ch_offset < 0 || ch_offset >= (int)SOC_MODULE_ATTR(TOUCH, CHAN_NUM)) {
if (ch_offset < 0 || ch_offset >= (int)TOUCH_LL_GET(CHAN_NUM)) {
/* Not a valid channel */
return;
}
components/esp_driver_touch_sens/test_apps/touch_sens/CMakeLists.txt
+9 -1
View File
@@ -10,9 +10,17 @@ project(touch_sens)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
# Collect RTL directories in a variable for readability. Join them
# with commas so they are passed as a single --rtl-dirs argument to the script.
set(TOUCH_SENS_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_touch_sens
${CMAKE_BINARY_DIR}/esp-idf/hal
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_touch_sens
)
string(JOIN "," TOUCH_SENS_RTL_DIRS_JOINED ${TOUCH_SENS_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_touch_sens/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${TOUCH_SENS_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/touch_sens.elf
find-refs
--from-sections=.iram0.text
components/esp_hal_ana_cmpr/CMakeLists.txt
+21
View File
@@ -0,0 +1,21 @@
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
set(srcs)
set(includes "include")
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND includes "${target}/include")
endif()
# Analog comparator related source files
if(CONFIG_SOC_ANA_CMPR_SUPPORTED)
list(APPEND srcs "${target}/ana_cmpr_periph.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES soc hal)
components/esp_hal_ana_cmpr/README.md
+72
View File
@@ -0,0 +1,72 @@
# ESP Hardware Abstraction Layer for Analog Comparator Peripheral
> [!NOTE]
> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
## Overview
The `esp_hal_ana_cmpr` component provides a **Hardware Abstraction Layer** for Analog Comparator peripherals across supported ESP-IDF targets. Analog comparators compare two analog voltage signals and generate digital outputs based on the comparison result, enabling threshold detection, zero-crossing detection, and analog signal monitoring applications.
## Architecture
The Analog Comparator HAL is structured in two main sub-layers:
1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control analog comparator peripherals (e.g., initialization, reference voltage configuration, cross detection setup, interrupt handling).
2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
## Supported Controllers
This HAL supports analog comparator controllers on the following ESP chips:
- **ESP32-P4**: Dual analog comparator units (ANA_CMPR_U0, ANA_CMPR_U1)
- **Others**: Single analog comparator unit
## Features
### Reference Voltage Configuration
- **Internal Reference Voltage**: Configurable internal reference voltage from 0% to 70% VDD in 10% steps (0.0V, 0.1VDD, 0.2VDD, ..., 0.7VDD)
- **External Reference Voltage**: Support for external reference voltage via dedicated GPIO pad (typically GPIO10)
- **Reference Source Selection**: Switch between internal and external reference sources
### Cross Detection
- **Positive Cross Detection**: Detects when the input analog signal crosses the reference voltage from low to high
- **Negative Cross Detection**: Detects when the input analog signal crosses the reference voltage from high to low
- **Any Cross Detection**: Detects both positive and negative crossings
- **Debounce Filtering**: Configurable debounce cycle to ensure stable cross detection and filter out noise
### Interrupt Handling
- **Multiple Interrupt Types**: Support for positive cross, negative cross, and any cross interrupts
- **Interrupt Masking**: Flexible interrupt enable/disable control per interrupt type
- **Interrupt Status**: Read interrupt status and clear interrupt flags
- **Interrupt Register Access**: Direct access to interrupt status register for advanced use cases
### Signal Processing
- **Debounce Cycle**: Configurable debounce cycle count to filter out glitches and ensure stable detection
- **Hardware Filtering**: Built-in hardware filtering for noise reduction
### Event Task Matrix (ETM) Support
- **ETM Event Source**: Analog comparator cross events can be used as ETM event sources for precise timing and synchronization
- **Multiple Event Types**: Support for positive and negative cross events as separate ETM sources
### Peripheral Configuration
- **GPIO Mapping**: Each comparator unit has dedicated source GPIO and external reference GPIO pins
- **Module Identification**: Each comparator unit has a unique module name for identification
- **Interrupt Source**: Each comparator unit has a dedicated interrupt source
## Usage
The HAL functions primarily serve ESP-IDF peripheral drivers such as `esp_driver_ana_cmpr`.
Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
## Dependencies
- `soc`: Provides chip-specific register definitions
- `hal`: Core hardware abstraction utilities and macros
components/soc/esp32c5/ana_cmpr_periph.c → components/esp_hal_ana_cmpr/esp32c5/ana_cmpr_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ana_cmpr_periph.h"
#include "hal/ana_cmpr_periph.h"
#include "soc/ana_cmpr_struct.h"
const ana_cmpr_periph_t ana_cmpr_periph[SOC_ANA_CMPR_NUM] = {
components/hal/esp32c5/include/hal/ana_cmpr_ll.h → components/esp_hal_ana_cmpr/esp32c5/include/hal/ana_cmpr_ll.h
-1
View File
@@ -28,7 +28,6 @@ extern "C" {
#define ANALOG_CMPR_LL_ETM_SOURCE(unit, type) (GPIO_EVT_ZERO_DET_POS0 + (unit) * 2 + (type))
/**
* @brief Enable analog comparator
*
components/soc/esp32c61/ana_cmpr_periph.c → components/esp_hal_ana_cmpr/esp32c61/ana_cmpr_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ana_cmpr_periph.h"
#include "hal/ana_cmpr_periph.h"
#include "soc/ana_cmpr_struct.h"
const ana_cmpr_periph_t ana_cmpr_periph[SOC_ANA_CMPR_NUM] = {
components/hal/esp32c61/include/hal/ana_cmpr_ll.h → components/esp_hal_ana_cmpr/esp32c61/include/hal/ana_cmpr_ll.h
-1
View File
@@ -28,7 +28,6 @@ extern "C" {
#define ANALOG_CMPR_LL_ETM_SOURCE(unit, type) (GPIO_EVT_ZERO_DET_POS0 + (unit) * 2 + (type))
/**
* @brief Enable analog comparator
*
components/soc/esp32h2/ana_cmpr_periph.c → components/esp_hal_ana_cmpr/esp32h2/ana_cmpr_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ana_cmpr_periph.h"
#include "hal/ana_cmpr_periph.h"
#include "soc/ana_cmpr_struct.h"
const ana_cmpr_periph_t ana_cmpr_periph[SOC_ANA_CMPR_NUM] = {
components/hal/esp32h2/include/hal/ana_cmpr_ll.h → components/esp_hal_ana_cmpr/esp32h2/include/hal/ana_cmpr_ll.h
View File
components/hal/esp32h21/include/hal/ana_cmpr_ll.h → components/esp_hal_ana_cmpr/esp32h21/include/hal/ana_cmpr_ll.h
View File
components/soc/esp32p4/ana_cmpr_periph.c → components/esp_hal_ana_cmpr/esp32p4/ana_cmpr_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/ana_cmpr_periph.h"
#include "hal/ana_cmpr_periph.h"
#include "soc/ana_cmpr_struct.h"
const ana_cmpr_periph_t ana_cmpr_periph[SOC_ANA_CMPR_NUM] = {
components/hal/esp32p4/include/hal/ana_cmpr_ll.h → components/esp_hal_ana_cmpr/esp32p4/include/hal/ana_cmpr_ll.h
-1
View File
@@ -28,7 +28,6 @@ extern "C" {
#define ANALOG_CMPR_LL_ETM_SOURCE(unit, type) (GPIO_EVT_ZERO_DET_POS0 + (unit) * 2 + (type))
/**
* @brief Enable analog comparator
*
components/soc/include/soc/ana_cmpr_periph.h → components/esp_hal_ana_cmpr/include/hal/ana_cmpr_periph.h
View File
components/hal/include/hal/ana_cmpr_types.h → components/esp_hal_ana_cmpr/include/hal/ana_cmpr_types.h
View File
components/esp_hal_ana_conv/CMakeLists.txt
+31
View File
@@ -0,0 +1,31 @@
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
set(requires soc hal)
if(${target} STREQUAL "esp32")
list(APPEND requires esp_hal_i2s)
endif()
set(srcs)
set(includes "include")
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND includes "${target}/include")
endif()
if(CONFIG_SOC_ADC_SUPPORTED)
list(APPEND srcs "${target}/adc_periph.c" "adc_hal_common.c" "adc_oneshot_hal.c")
if(CONFIG_SOC_ADC_DMA_SUPPORTED)
list(APPEND srcs "adc_hal.c")
endif()
endif()
if(CONFIG_SOC_DAC_SUPPORTED)
list(APPEND srcs "${target}/dac_periph.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES ${requires})
components/esp_hal_ana_conv/README.md
+101
View File
@@ -0,0 +1,101 @@
# ESP Hardware Abstraction Layer for Analog Conversion Peripherals
> [!NOTE]
> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
## Overview
The `esp_hal_ana_conv` component provides a **Hardware Abstraction Layer** for analog conversion related peripherals across all ESP-IDF supported targets. This HAL currently supports Analog-to-Digital Converter (ADC), Digital-to-Analog Converter (DAC) and other analog conversion related peripherals. The HAL enables analog signal acquisition, generation, and monitoring capabilities.
## Architecture
The analog conversion HAL is structured in two main sub-layers:
1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control analog conversion peripherals (e.g., initialization, channel configuration, conversion control, DMA setup, sensor reading).
2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
## Supported Controllers
### ADC Controllers
This HAL supports various ADC controller types depending on the ESP chip:
- **RTC Controller**: Single conversion mode for low-power applications, supports deep sleep operation
- **ULP Controller**: Ultra-low-power controller for ULP coprocessor control
- **Digital Controller (DIG)**: Continuous conversion mode with DMA support, high-performance multi-channel scanning
- **Arbiter Controller (ARB)**: Manages multiple controller access to ADC2 (ESP32-S2, ESP32-S3)
- **PWDET Controller**: Power detection controller for Wi-Fi power monitoring (ADC2 only)
### DAC Controllers
This HAL supports various DAC controller types depending on the ESP chip:
- **RTC Controller**: Direct voltage output control
- **DMA Controller**: High-speed data output via I2S or SPI DMA
## ADC Features
### Work Modes
- **Oneshot Mode**: Single conversion per trigger, suitable for polling-based applications
- **Continuous Mode**: Continuous conversion with DMA, supports high-speed multi-channel scanning
- **Low-Power Mode**: Ultra-low-power operation for battery-powered applications
- **PWDET Mode**: Power detection mode for Wi-Fi power monitoring
### Conversion Capabilities
- **Multi-Unit Support**: Support for ADC1 and ADC2 (where available)
- **Conversion Modes**:
- Single unit mode (ADC1 or ADC2 only)
- Both units mode (ADC1 and ADC2 simultaneously)
- Alternate unit mode (ADC1 and ADC2 alternately)
- **Resolution Options**: 9-bit, 10-bit, 11-bit, 12-bit, 13-bit (chip-dependent)
- **Attenuation Options**: 0dB, 2.5dB, 6dB, 12dB for different input voltage ranges
- **Pattern Table**: Configurable scan sequence with up to 16 patterns per unit
### Signal Processing
- **IIR Filtering**: Digital IIR filters for noise reduction at high sampling rates
- **Monitor Function**: Hardware threshold monitoring with interrupt support
- **Data Inversion**: Optional data inversion for compatibility
- **Calibration**: Hardware and software calibration support for improved accuracy
### Clock and Timing
- **Flexible Clock Sources**: APB clock, APLL, XTAL, RC_FAST (chip-dependent)
- **Configurable Sampling Rate**: Adjustable via clock division and trigger interval
- **FSM Timing Control**: Configurable wait times for reset, start, and standby phases
## DAC Features
### Output Capabilities
- **Dual Channel Support**: Two independent DAC channels (DAC_CHAN_0, DAC_CHAN_1)
- **8-bit Resolution**: 256-level voltage output (0V to VDD3P3_RTC)
- **Direct Voltage Output**: Direct control of output voltage value
### Cosine Wave Generator
- **Frequency Control**: Configurable frequency from 130Hz to several MHz
- **Amplitude Control**: Adjustable attenuation (0dB, 6dB, 12dB, 18dB)
- **Phase Control**: 0° or 180° phase shift support
- **DC Offset**: Configurable DC component for signal offset
### Advanced Features
- **DMA Output**: High-speed data streaming via I2S, SPI or GDMA
- **ADC-DAC Synchronization**: Synchronized operation with ADC RTC controller
- **Power Management**: Independent power control per channel
## Usage
The HAL functions primarily serve ESP-IDF peripheral drivers such as `esp_adc` and `esp_driver_dac`.
Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
## Dependencies
- `soc`: Provides chip-specific register definitions
- `hal`: Core hardware abstraction utilities and macros
components/hal/adc_hal.c → components/esp_hal_ana_conv/adc_hal.c
+1 -2
View File
@@ -8,7 +8,7 @@
#include "hal/adc_hal.h"
#include "hal/assert.h"
#include "soc/lldesc.h"
#include "soc/soc_caps_full.h"
#include "soc/soc_caps.h"
#if SOC_IS(ESP32)
//ADC utilises I2S0 DMA on ESP32
@@ -188,7 +188,6 @@ void adc_hal_digi_controller_config(adc_hal_dma_ctx_t *hal, const adc_hal_digi_c
adc_hal_digi_sample_freq_config(hal, cfg->clk_src, cfg->clk_src_freq_hz, cfg->sample_freq_hz);
}
void adc_hal_digi_dma_link(adc_hal_dma_ctx_t *hal, uint8_t *data_buf)
{
dma_descriptor_t *desc = hal->rx_desc;
components/hal/adc_hal_common.c → components/esp_hal_ana_conv/adc_hal_common.c
+26 -28
View File
@@ -18,43 +18,43 @@ static adc_ll_controller_t get_controller(adc_unit_t unit, adc_hal_work_mode_t w
if (unit == ADC_UNIT_1) {
switch (work_mode) {
#if SOC_ULP_HAS_ADC || SOC_LP_CORE_SUPPORT_LP_ADC
case ADC_HAL_LP_MODE:
return ADC_LL_CTRL_ULP;
case ADC_HAL_LP_MODE:
return ADC_LL_CTRL_ULP;
#endif
case ADC_HAL_SINGLE_READ_MODE:
case ADC_HAL_SINGLE_READ_MODE:
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
return ADC_LL_CTRL_DIG;
return ADC_LL_CTRL_DIG;
#elif SOC_ADC_RTC_CTRL_SUPPORTED
return ADC_LL_CTRL_RTC;
return ADC_LL_CTRL_RTC;
#endif
case ADC_HAL_CONTINUOUS_READ_MODE:
return ADC_LL_CTRL_DIG;
default:
abort();
case ADC_HAL_CONTINUOUS_READ_MODE:
return ADC_LL_CTRL_DIG;
default:
abort();
}
} else {
switch (work_mode) {
#if SOC_ULP_HAS_ADC || SOC_LP_CORE_SUPPORT_LP_ADC
case ADC_HAL_LP_MODE:
return ADC_LL_CTRL_ULP;
case ADC_HAL_LP_MODE:
return ADC_LL_CTRL_ULP;
#endif
#if !SOC_ADC_ARBITER_SUPPORTED //No ADC2 arbiter on ESP32
#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
default:
return ADC_LL_CTRL_DIG;
default:
return ADC_LL_CTRL_DIG;
#else
case ADC_HAL_SINGLE_READ_MODE:
return ADC_LL_CTRL_RTC;
case ADC_HAL_CONTINUOUS_READ_MODE:
return ADC_LL_CTRL_DIG;
case ADC_HAL_PWDET_MODE:
return ADC_LL_CTRL_PWDET;
default:
abort();
case ADC_HAL_SINGLE_READ_MODE:
return ADC_LL_CTRL_RTC;
case ADC_HAL_CONTINUOUS_READ_MODE:
return ADC_LL_CTRL_DIG;
case ADC_HAL_PWDET_MODE:
return ADC_LL_CTRL_PWDET;
default:
abort();
#endif //#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
#else
default:
return ADC_LL_CTRL_ARB;
default:
return ADC_LL_CTRL_ARB;
#endif
}
}
@@ -66,7 +66,6 @@ void adc_hal_set_controller(adc_unit_t unit, adc_hal_work_mode_t work_mode)
adc_ll_set_controller(unit, ctrlr);
}
/*---------------------------------------------------------------
Arbiter
---------------------------------------------------------------*/
@@ -78,7 +77,6 @@ void adc_hal_arbiter_config(adc_arbiter_t *config)
}
#endif // #if SOC_ADC_ARBITER_SUPPORTED
/*---------------------------------------------------------------
ADC calibration setting
---------------------------------------------------------------*/
@@ -125,7 +123,7 @@ static uint32_t read_cal_channel(adc_unit_t adc_n)
adc_oneshot_ll_start(adc_n);
#endif
while(!adc_oneshot_ll_get_event(event));
while (!adc_oneshot_ll_get_event(event));
uint32_t read_val = -1;
read_val = adc_oneshot_ll_get_raw_result(adc_n);
@@ -191,8 +189,8 @@ uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool inte
chk_code = code_h + code_l;
uint32_t ret = ((code_sum - chk_code) % (ADC_HAL_CAL_TIMES - 2) < 4)
? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
: (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
? (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2)
: (code_sum - chk_code) / (ADC_HAL_CAL_TIMES - 2) + 1;
adc_ll_calibration_finish(adc_n);
return ret;
components/hal/adc_oneshot_hal.c → components/esp_hal_ana_conv/adc_oneshot_hal.c
+1 -1
View File
@@ -110,7 +110,7 @@ static void adc_hal_onetime_start(adc_unit_t unit, uint32_t clk_src_freq_hz, uin
HAL_EARLY_LOGD(TAG, "clk_src_freq_hz: %"PRIu32", adc_ctrl_clk: %"PRIu32", sample_delay_us: %"PRIu32"", clk_src_freq_hz, adc_ctrl_clk, sample_delay_us);
//This coefficient (8) is got from test, and verified from DT. When digi_clk is not smaller than ``APB_CLK_FREQ/8``, no delay is needed.
if (adc_ctrl_clk >= APB_CLK_FREQ/8) {
if (adc_ctrl_clk >= APB_CLK_FREQ / 8) {
sample_delay_us = 0;
}
components/soc/esp32/adc_periph.c → components/esp_hal_ana_conv/esp32/adc_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
components/soc/esp32/dac_periph.c → components/esp_hal_ana_conv/esp32/dac_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
/*
Bunch of constants for DAC peripheral: GPIO number
components/hal/esp32/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32/include/hal/adc_ll.h
+36 -36
View File
@@ -11,7 +11,7 @@
#include "hal/adc_types.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "soc/sens_reg.h"
@@ -254,20 +254,20 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
uint8_t bit_width;
switch (table.bit_width) {
case 9:
bit_width = 0x0;
break;
case 10:
bit_width = 0x1;
break;
case 11:
bit_width = 0x2;
break;
case 12:
bit_width = 0x3;
break;
default:
bit_width = 0x3;
case 9:
bit_width = 0x0;
break;
case 10:
bit_width = 0x1;
break;
case 11:
bit_width = 0x2;
break;
case 12:
bit_width = 0x3;
break;
default:
bit_width = 0x3;
}
pattern.val = (table.atten & 0x3) | ((bit_width) << 2) | ((table.channel & 0xF) << 4);
@@ -363,23 +363,23 @@ static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth
{
uint32_t reg_val = 0;
switch (bits) {
case ADC_BITWIDTH_9:
reg_val = 0;
break;
case ADC_BITWIDTH_10:
reg_val = 1;
break;
case ADC_BITWIDTH_11:
reg_val = 2;
break;
case ADC_BITWIDTH_12:
reg_val = 3;
break;
case ADC_BITWIDTH_DEFAULT:
reg_val = 3;
break;
default:
HAL_ASSERT(false);
case ADC_BITWIDTH_9:
reg_val = 0;
break;
case ADC_BITWIDTH_10:
reg_val = 1;
break;
case ADC_BITWIDTH_11:
reg_val = 2;
break;
case ADC_BITWIDTH_12:
reg_val = 3;
break;
case ADC_BITWIDTH_DEFAULT:
reg_val = 3;
break;
default:
HAL_ASSERT(false);
}
if (adc_n == ADC_UNIT_1) {
SENS.sar_start_force.sar1_bit_width = reg_val;
@@ -526,9 +526,9 @@ static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten1 = (SENS.sar_atten1 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten2 = (SENS.sar_atten2 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
}
}
@@ -604,7 +604,7 @@ __attribute__((always_inline))
static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t ctrl)
{
if (adc_n == ADC_UNIT_1) {
switch ( ctrl ) {
switch (ctrl) {
case ADC_LL_CTRL_RTC:
SENS.sar_read_ctrl.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas_start1.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
@@ -630,7 +630,7 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
break;
}
} else { // adc_n == ADC_UNIT_2
switch ( ctrl ) {
switch (ctrl) {
case ADC_LL_CTRL_RTC:
SENS.sar_meas_start2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas_start2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
components/hal/esp32/include/hal/dac_ll.h → components/esp_hal_ana_conv/esp32/include/hal/dac_ll.h
+1 -1
View File
@@ -15,7 +15,7 @@
#include <stdlib.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
#include "soc/rtc_io_struct.h"
#include "soc/sens_struct.h"
#include "hal/dac_types.h"
components/soc/esp32c2/adc_periph.c → components/esp_hal_ana_conv/esp32c2/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][5] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
components/hal/esp32c2/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c2/include/hal/adc_ll.h
+18 -18
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
@@ -266,23 +266,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
components/esp_hal_ana_conv/esp32c3/adc_periph.c
+19
View File
@@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[2][5] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM
},
/* ADC2 */
{
ADC2_CHANNEL_0_GPIO_NUM, -1, -1, -1, -1
}
};
components/hal/esp32c3/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c3/include/hal/adc_ll.h
+19 -20
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
@@ -363,23 +363,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -513,8 +513,7 @@ static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
static inline void adc_ll_digi_dma_clr_eof(void)
{
uint32_t eof_num = HAL_FORCE_READ_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num);
for (int i = 0; i <= eof_num; i++)
{
for (int i = 0; i <= eof_num; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, i);
}
}
components/soc/esp32c5/adc_periph.c → components/esp_hal_ana_conv/esp32c5/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][6] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
components/hal/esp32c5/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c5/include/hal/adc_ll.h
+29 -31
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -331,17 +331,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
@@ -380,23 +380,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -732,7 +732,6 @@ static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
return ret_val;
}
/**
* Analyze whether the obtained raw data is correct.
* ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data.
@@ -814,7 +813,6 @@ static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t chann
return (adc_atten_t)APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten;
}
/*---------------------------------------------------------------
Calibration
---------------------------------------------------------------*/
components/soc/esp32c6/adc_periph.c → components/esp_hal_ana_conv/esp32c6/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][7] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
components/hal/esp32c6/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c6/include/hal/adc_ll.h
+29 -29
View File
@@ -10,7 +10,7 @@
#include "esp_attr.h"
#include "esp_rom_sys.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -331,17 +331,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
@@ -380,23 +380,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
components/soc/esp32c61/adc_periph.c → components/esp_hal_ana_conv/esp32c61/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][4] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
components/hal/esp32c61/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32c61/include/hal/adc_ll.h
+29 -30
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -333,17 +333,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
ADC.saradc_ctrl.saradc_sar_clk_gated = 1;
@@ -382,23 +382,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -868,7 +868,6 @@ static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
return ret_val;
}
/**
* Analyze whether the obtained raw data is correct.
* ADC2 can use arbiter. The arbitration result is stored in the channel information of the returned data.
components/soc/esp32h2/adc_periph.c → components/esp_hal_ana_conv/esp32h2/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[1][5] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
components/hal/esp32h2/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32h2/include/hal/adc_ll.h
+29 -29
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/apb_saradc_struct.h"
#include "soc/apb_saradc_reg.h"
#include "soc/pmu_reg.h"
@@ -331,17 +331,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_PLL_F96M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
PCR.saradc_clkm_conf.saradc_clkm_sel = 0;
break;
case ADC_DIGI_CLK_SRC_PLL_F96M:
PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
@@ -380,23 +380,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
components/soc/esp32p4/adc_periph.c → components/esp_hal_ana_conv/esp32p4/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[2][8] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM,
components/hal/esp32p4/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32p4/include/hal/adc_ll.h
+67 -72
View File
@@ -9,7 +9,7 @@
#include <stdlib.h>
#include "esp_attr.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "soc/adc_struct.h"
#include "soc/clk_tree_defs.h"
#include "soc/hp_sys_clkrst_struct.h"
@@ -225,17 +225,17 @@ __attribute__((always_inline))
static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
{
switch (clk_src) {
case ADC_DIGI_CLK_SRC_XTAL:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
case ADC_DIGI_CLK_SRC_XTAL:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 0;
break;
case ADC_DIGI_CLK_SRC_RC_FAST:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 1;
break;
case ADC_DIGI_CLK_SRC_PLL_F80M:
HP_SYS_CLKRST.peri_clk_ctrl22.reg_adc_clk_src_sel = 2;
break;
default:
HAL_ASSERT(false && "unsupported clock");
}
// Enable ADC_CTRL_CLK (i.e. digital domain clock)
ADC.ctrl_reg.sar_clk_gated = 1;
@@ -274,23 +274,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -362,7 +362,7 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
uint8_t offset = (pattern_index % 4) * 6;
adc_ll_digi_pattern_table_t pattern = {0};
if (table.unit == ADC_UNIT_1){
if (table.unit == ADC_UNIT_1) {
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
tab = ADC.sar1_patt_tab[index].sar1_patt_tab; //Read old register value
tab &= (~(0xFC0000 >> offset)); //Clear old data
@@ -377,13 +377,12 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
}
}
/**
* Rest pattern table to default value
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
for(int i = 0; i < 4; i++) {
for (int i = 0; i < 4; i++) {
ADC.sar1_patt_tab[i].sar1_patt_tab = 0xffffff;
ADC.sar2_patt_tab[i].sar2_patt_tab = 0xffffff;
}
@@ -573,8 +572,6 @@ static inline void _adc_ll_reset_register(void)
_adc_ll_reset_register(__VA_ARGS__); \
} while(0)
/**
* Set ADC digital controller power management.
*
@@ -651,7 +648,6 @@ static inline void adc_ll_set_power_manage(adc_unit_t adc_n, adc_ll_power_t mana
}
}
/**
* Set ADC module controller.
* There are five SAR ADC controllers:
@@ -667,43 +663,43 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
{
if (adc_n == ADC_UNIT_1) {
switch (ctrl) {
case ADC_LL_CTRL_RTC:
LP_ADC.meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
LP_ADC.meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
LP_ADC.meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
case ADC_LL_CTRL_RTC:
LP_ADC.meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
LP_ADC.meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
LP_ADC.meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
}
} else { // adc_n == ADC_UNIT_2
switch (ctrl) {
case ADC_LL_CTRL_RTC:
LP_ADC.meas2_mux.sar2_rtc_force = 1; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
LP_ADC.meas2_mux.sar2_rtc_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
LP_ADC.meas2_mux.sar2_rtc_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
case ADC_LL_CTRL_RTC:
LP_ADC.meas2_mux.sar2_rtc_force = 1; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
LP_ADC.meas2_mux.sar2_rtc_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
LP_ADC.meas2_mux.sar2_rtc_force = 0; // 1: Select digital control; 0: Select RTC control.
LP_ADC.meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
LP_ADC.meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
}
}
}
@@ -1028,7 +1024,6 @@ static inline void adc_ll_rtc_reset(void)
LPPERI.reset_en.rst_en_lp_adc = 0;
}
/**
* Set the attenuation of a particular channel on ADCn.
*
@@ -1065,9 +1060,9 @@ static inline void adc_ll_rtc_reset(void)
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_UNIT_1) {
LP_ADC.atten1.sar1_atten = ( LP_ADC.atten1.sar1_atten & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
LP_ADC.atten1.sar1_atten = (LP_ADC.atten1.sar1_atten & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_UNIT_2
LP_ADC.atten2.sar2_atten = ( LP_ADC.atten2.sar2_atten & ~(0x3 << ((channel + 2) * 2)) ) | ((atten & 0x3) << ((channel + 2) * 2));
LP_ADC.atten2.sar2_atten = (LP_ADC.atten2.sar2_atten & ~(0x3 << ((channel + 2) * 2))) | ((atten & 0x3) << ((channel + 2) * 2));
}
}
components/soc/esp32s2/adc_periph.c → components/esp_hal_ana_conv/esp32s2/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[2][10] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM,
components/soc/esp32s2/dac_periph.c → components/esp_hal_ana_conv/esp32s2/dac_periph.c
+1 -1
View File
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
/*
Bunch of constants for DAC peripheral: GPIO number
components/hal/esp32s2/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32s2/include/hal/adc_ll.h
+6 -7
View File
@@ -8,7 +8,7 @@
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#include "hal/assert.h"
@@ -252,7 +252,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
for(int i = 0; i < 4; i++) {
for (int i = 0; i < 4; i++) {
APB_SARADC.sar1_patt_tab[i] = 0xffffff;
APB_SARADC.sar2_patt_tab[i] = 0xffffff;
}
@@ -507,9 +507,9 @@ static inline void adc_ll_digi_monitor_set_mode(adc_monitor_id_t monitor_id, boo
static inline void adc_ll_digi_monitor_set_thres(adc_monitor_id_t monitor_id, adc_unit_t adc_n, uint8_t channel, int32_t h_thresh, int32_t l_thresh)
{
if (monitor_id == ADC_MONITOR_0) {
APB_SARADC.thres_ctrl.adc1_thres = (h_thresh == -1)? l_thresh : h_thresh;
APB_SARADC.thres_ctrl.adc1_thres = (h_thresh == -1) ? l_thresh : h_thresh;
} else { // monitor_id == ADC_MONITOR_1
APB_SARADC.thres_ctrl.adc2_thres = (h_thresh == -1)? l_thresh : h_thresh;
APB_SARADC.thres_ctrl.adc2_thres = (h_thresh == -1) ? l_thresh : h_thresh;
}
adc_ll_digi_monitor_set_mode(monitor_id, l_thresh == -1);
}
@@ -889,9 +889,9 @@ static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten1 = (SENS.sar_atten1 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten2 = (SENS.sar_atten2 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
}
}
@@ -1294,7 +1294,6 @@ static inline void adc_ll_regi2c_adc_deinit(void)
adc_ll_enable_calibration_ref(ADC_UNIT_2, false);
}
/* Temp code end. */
/**
components/hal/esp32s2/include/hal/dac_ll.h → components/esp_hal_ana_conv/esp32s2/include/hal/dac_ll.h
+1 -1
View File
@@ -15,7 +15,7 @@
#include <stdlib.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/dac_periph.h"
#include "hal/dac_periph.h"
#include "hal/dac_types.h"
#include "soc/apb_saradc_struct.h"
#include "soc/sens_struct.h"
components/soc/esp32s3/adc_periph.c → components/esp_hal_ana_conv/esp32s3/adc_periph.c
+2 -2
View File
@@ -4,10 +4,10 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
const int adc_channel_io_map[2][10] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM,
components/hal/esp32s3/include/hal/adc_ll.h → components/esp_hal_ana_conv/esp32s3/include/hal/adc_ll.h
+49 -50
View File
@@ -8,7 +8,7 @@
#include <stdio.h>
#include <stdbool.h>
#include "soc/adc_periph.h"
#include "hal/adc_periph.h"
#include "hal/adc_types.h"
#include "hal/adc_types_private.h"
#include "hal/assert.h"
@@ -143,7 +143,6 @@ typedef struct {
#pragma pack(pop)
#endif /* _MSC_VER */
/*---------------------------------------------------------------
Digital controller setting
---------------------------------------------------------------*/
@@ -260,7 +259,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
*/
static inline void adc_ll_digi_reset_pattern_table(void)
{
for(int i = 0; i < 4; i++) {
for (int i = 0; i < 4; i++) {
APB_SARADC.sar1_patt_tab[i].sar1_patt_tab = 0xffffff;
APB_SARADC.sar2_patt_tab[i].sar2_patt_tab = 0xffffff;
}
@@ -284,7 +283,7 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
adc_ll_digi_pattern_table_t pattern = {0};
pattern.val = (table.atten & 0x3) | ((table.channel & 0xF) << 2);
if (table.unit == ADC_UNIT_1){
if (table.unit == ADC_UNIT_1) {
tab = APB_SARADC.sar1_patt_tab[index].sar1_patt_tab; //Read old register value
tab &= (~(0xFC0000 >> offset)); //Clear old data
tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; //Fill in the new data
@@ -428,23 +427,23 @@ static inline void adc_ll_digi_filter_set_factor(adc_digi_iir_filter_t idx, adc_
{
uint32_t factor_reg_val = 0;
switch (coeff) {
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
case ADC_DIGI_IIR_FILTER_COEFF_2:
factor_reg_val = 1;
break;
case ADC_DIGI_IIR_FILTER_COEFF_4:
factor_reg_val = 2;
break;
case ADC_DIGI_IIR_FILTER_COEFF_8:
factor_reg_val = 3;
break;
case ADC_DIGI_IIR_FILTER_COEFF_16:
factor_reg_val = 4;
break;
case ADC_DIGI_IIR_FILTER_COEFF_64:
factor_reg_val = 6;
break;
default:
HAL_ASSERT(false);
}
if (idx == ADC_DIGI_IIR_FILTER_0) {
@@ -691,37 +690,37 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
{
if (adc_n == ADC_UNIT_1) {
switch (ctrl) {
case ADC_LL_CTRL_RTC:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
SENS.sar_meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
case ADC_LL_CTRL_RTC:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
SENS.sar_meas1_mux.sar1_dig_force = 0; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_DIG:
SENS.sar_meas1_mux.sar1_dig_force = 1; // 1: Select digital control; 0: Select RTC control.
SENS.sar_meas1_ctrl2.meas1_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas1_ctrl2.sar1_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
}
} else { // adc_n == ADC_UNIT_2
//If ADC2 is not controlled by ULP, the arbiter will decide which controller to use ADC2.
switch (ctrl) {
case ADC_LL_CTRL_ARB:
SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
SENS.sar_meas2_ctrl2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
case ADC_LL_CTRL_ARB:
SENS.sar_meas2_ctrl2.meas2_start_force = 1; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 1; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
case ADC_LL_CTRL_ULP:
SENS.sar_meas2_ctrl2.meas2_start_force = 0; // 1: SW control RTC ADC start; 0: ULP control RTC ADC start.
SENS.sar_meas2_ctrl2.sar2_en_pad_force = 0; // 1: SW control RTC ADC bit map; 0: ULP control RTC ADC bit map;
break;
default:
break;
}
}
}
@@ -1237,9 +1236,9 @@ static inline void adc_ll_rtc_set_arbiter_stable_cycle(uint32_t cycle)
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
{
if (adc_n == ADC_UNIT_1) {
SENS.sar_atten1 = ( SENS.sar_atten1 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten1 = (SENS.sar_atten1 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
} else { // adc_n == ADC_UNIT_2
SENS.sar_atten2 = ( SENS.sar_atten2 & ~(0x3 << (channel * 2)) ) | ((atten & 0x3) << (channel * 2));
SENS.sar_atten2 = (SENS.sar_atten2 & ~(0x3 << (channel * 2))) | ((atten & 0x3) << (channel * 2));
}
}
components/hal/include/hal/adc_hal.h → components/esp_hal_ana_conv/include/hal/adc_hal.h
-1
View File
@@ -78,7 +78,6 @@ typedef struct adc_hal_digi_ctrlr_cfg_t {
uint32_t clk_src_freq_hz; ///< Clock source frequency in hz
} adc_hal_digi_ctrlr_cfg_t;
/*---------------------------------------------------------------
PWDET(Power detect) controller setting
---------------------------------------------------------------*/
components/hal/include/hal/adc_hal_common.h → components/esp_hal_ana_conv/include/hal/adc_hal_common.h
-2
View File
@@ -13,7 +13,6 @@
extern "C" {
#endif
/**
* This header file is only for hardware abstract concepts and APIs
* used by both ADC RTC controller and Digital controller
@@ -92,7 +91,6 @@ uint32_t adc_hal_self_calibration(adc_unit_t adc_n, adc_atten_t atten, bool inte
#endif //SOC_ADC_CALIBRATION_V1_SUPPORTED
#ifdef __cplusplus
}
#endif

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