feat(driver_spi): s31 gpspi driver support

2026-04-27 19:13:21 +00:00 · 2026-02-09 18:31:00 +08:00
parent 64704886b7
commit 99bf74f022
64 changed files with 1736 additions and 443 deletions
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -68,13 +68,12 @@
 #define SLAVE_IOMUX_PIN_WP      SPI3_IOMUX_PIN_NUM_WP
 #define SLAVE_IOMUX_PIN_HD      SPI3_IOMUX_PIN_NUM_HD

-#define UNCONNECTED_PIN         27
 #define INPUT_ONLY_PIN          34
 #define GPIO_DELAY              (12.5*2)
 #define ESP_SPI_SLAVE_TV        (12.5*3.5)
 #define WIRE_DELAY              12.5

-#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32H4
+#else   // CONFIG_IDF_TARGET_ESP32
 #define SLAVE_IOMUX_PIN_MISO    -1
 #define SLAVE_IOMUX_PIN_MOSI    -1
 #define SLAVE_IOMUX_PIN_SCLK    -1
@@ -82,24 +81,13 @@
 #define SLAVE_IOMUX_PIN_WP      -1
 #define SLAVE_IOMUX_PIN_HD      -1

-#if CONFIG_IDF_TARGET_ESP32H4
-#define UNCONNECTED_PIN         27
-#else
-#define UNCONNECTED_PIN         41
-#endif
 #define INPUT_ONLY_PIN          46
 #define GPIO_DELAY              0
 #define ESP_SPI_SLAVE_TV        0
 #define WIRE_DELAY              12.5
-
-#else
-#define UNCONNECTED_PIN         8
-#define GPIO_DELAY              0
-#define ESP_SPI_SLAVE_TV        0
-#define WIRE_DELAY              12.5
 #endif  //CONFIG_IDF_TARGET_ESP32

-#define FUNC_SPI    SPI2_FUNC_NUM
+#define FUNC_SPI    SPI2_FUNC_NUM_QUAD
 #define FUNC_GPIO   PIN_FUNC_GPIO

 //Delay information
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
@@ -536,25 +536,18 @@ static bool check_iomux_pins_oct(spi_host_device_t host, const spi_bus_config_t*

 static bool check_iomux_pins_quad(spi_host_device_t host, const spi_bus_config_t* bus_config)
 {
-    if (bus_config->sclk_io_num >= 0 &&
-            bus_config->sclk_io_num != spi_periph_signal[host].spiclk_iomux_pin) {
-        return false;
-    }
-    if (bus_config->quadwp_io_num >= 0 &&
-            bus_config->quadwp_io_num != spi_periph_signal[host].spiwp_iomux_pin) {
-        return false;
-    }
-    if (bus_config->quadhd_io_num >= 0 &&
-            bus_config->quadhd_io_num != spi_periph_signal[host].spihd_iomux_pin) {
-        return false;
-    }
-    if (bus_config->mosi_io_num >= 0 &&
-            bus_config->mosi_io_num != spi_periph_signal[host].spid_iomux_pin) {
-        return false;
-    }
-    if (bus_config->miso_io_num >= 0 &&
-            bus_config->miso_io_num != spi_periph_signal[host].spiq_iomux_pin) {
-        return false;
+    int io_nums[] = {bus_config->data0_io_num, bus_config->data1_io_num, bus_config->data2_io_num, bus_config->data3_io_num, bus_config->sclk_io_num};
+    int io_mux_nums[] = {spi_periph_signal[host].spid_iomux_pin, spi_periph_signal[host].spiq_iomux_pin, spi_periph_signal[host].spiwp_iomux_pin, spi_periph_signal[host].spihd_iomux_pin, spi_periph_signal[host].spiclk_iomux_pin};
+#ifdef SPI2_IOMUX_PIN_2_NUM_MOSI
+    int io_mux_2_nums[] = {SPI2_IOMUX_PIN_2_NUM_MOSI, SPI2_IOMUX_PIN_2_NUM_MISO, SPI2_IOMUX_PIN_2_NUM_WP, SPI2_IOMUX_PIN_2_NUM_HD, SPI2_IOMUX_PIN_2_NUM_CLK};
+#else
+    // use same pin again to fake the second set of pins
+    int *io_mux_2_nums = io_mux_nums;
+#endif
+    for (size_t i = 0; i < sizeof(io_nums) / sizeof(io_nums[0]); i++) {
+        if (io_nums[i] >= 0 && (io_nums[i] != io_mux_nums[i]) && (io_nums[i] != io_mux_2_nums[i])) {
+            return false;
+        }
    }
    return true;
 }
@@ -594,25 +587,14 @@ static void bus_iomux_pins_set_oct(spi_host_device_t host, const spi_bus_config_

 static void bus_iomux_pins_set_quad(spi_host_device_t host, const spi_bus_config_t* bus_config)
 {
-    if (bus_config->mosi_io_num >= 0) {
-        gpio_iomux_input(bus_config->mosi_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spid_in);
-        gpio_iomux_output(bus_config->mosi_io_num, spi_periph_signal[host].func);
-    }
-    if (bus_config->miso_io_num >= 0) {
-        gpio_iomux_input(bus_config->miso_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spiq_in);
-        gpio_iomux_output(bus_config->miso_io_num, spi_periph_signal[host].func);
-    }
-    if (bus_config->quadwp_io_num >= 0) {
-        gpio_iomux_input(bus_config->quadwp_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spiwp_in);
-        gpio_iomux_output(bus_config->quadwp_io_num, spi_periph_signal[host].func);
-    }
-    if (bus_config->quadhd_io_num >= 0) {
-        gpio_iomux_input(bus_config->quadhd_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spihd_in);
-        gpio_iomux_output(bus_config->quadhd_io_num, spi_periph_signal[host].func);
-    }
-    if (bus_config->sclk_io_num >= 0) {
-        gpio_iomux_input(bus_config->sclk_io_num, spi_periph_signal[host].func, spi_periph_signal[host].spiclk_in);
-        gpio_iomux_output(bus_config->sclk_io_num, spi_periph_signal[host].func);
+    int io_nums[] = {bus_config->data0_io_num, bus_config->data1_io_num, bus_config->data2_io_num, bus_config->data3_io_num, bus_config->sclk_io_num};
+    int io_signals[] = {spi_periph_signal[host].spid_in, spi_periph_signal[host].spiq_in, spi_periph_signal[host].spiwp_in, spi_periph_signal[host].spihd_in, spi_periph_signal[host].spiclk_in};
+
+    for (size_t i = 0; i < sizeof(io_nums) / sizeof(io_nums[0]); i++) {
+        if (io_nums[i] >= 0) {
+            gpio_iomux_input(io_nums[i], spi_periph_signal[host].func, io_signals[i]);
+            gpio_iomux_output(io_nums[i], spi_periph_signal[host].func);
+        }
    }
 }

@@ -687,6 +687,7 @@ static SPI_MASTER_ISR_ATTR void spi_setup_device(spi_device_t *dev, spi_trans_pr
 #if SPI_LL_SRC_PRE_DIV_MAX
            //we set mst_div as const 2, then (hs_clk = 2*mst_clk) to ensure timing turning work as past
            //and sure (hs_div * mst_div = source_pre_div)
+            assert(hal_dev->timing_conf.source_pre_div >= 2);   // source_pre_div must be even and at least 2
            spi_ll_clk_source_pre_div(hal->hw, hal_dev->timing_conf.source_pre_div / 2, 2);
 #endif
            spi_ll_set_clk_source(hal->hw, hal_dev->timing_conf.clock_source);
@@ -104,4 +104,10 @@
 #define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          60
 #define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          25

+#elif CONFIG_IDF_TARGET_ESP32S31
+#define IDF_TARGET_MAX_SPI_CLK_FREQ                 40*1000*1000
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_DMA          22
+#define IDF_TARGET_MAX_TRANS_TIME_POLL_CPU          17
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_DMA          32
+#define IDF_TARGET_MAX_TRANS_TIME_INTR_CPU          28
 #endif
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
@@ -138,7 +138,7 @@ TEST_CASE("SPI Master clockdiv calculation routines", "[spi]")

 // Test All clock source
 #define TEST_CLK_BYTE_LEN           10000
-#define TEST_TRANS_TIME_BIAS_RATIO  (float)10.0/100   // think 10% transfer time bias as acceptable
+#define TEST_TRANS_TIME_BIAS_RATIO  (float)15.0/100   // think 15% transfer time bias as acceptable
 TEST_CASE("SPI Master clk_source and divider accuracy", "[spi]")
 {
    int64_t start = 0, end = 0;
@@ -677,6 +677,24 @@ TEST_CASE("spi bus setting with different pin configs", "[spi]")
    };
    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
    TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+
+#ifdef SPI2_IOMUX_PIN_2_NUM_MOSI
+    ESP_LOGI(TAG, "check 2nd set of iomux pins...");
+    flags_expected = SPICOMMON_BUSFLAG_MOSI | SPICOMMON_BUSFLAG_MISO | SPICOMMON_BUSFLAG_QUAD | SPICOMMON_BUSFLAG_SCLK | SPICOMMON_BUSFLAG_IOMUX_PINS;
+    // all 2nd iomux pins
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = SPI2_IOMUX_PIN_2_NUM_MOSI, .miso_io_num = SPI2_IOMUX_PIN_2_NUM_MISO, .sclk_io_num = SPI2_IOMUX_PIN_2_NUM_CLK, .quadhd_io_num = SPI2_IOMUX_PIN_2_NUM_HD, .quadwp_io_num = SPI2_IOMUX_PIN_2_NUM_WP,
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_MASTER, &flags_o));
+    TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o);
+
+    // mixed 1st and 2nd iomux pins
+    cfg = (spi_bus_config_t) {
+        .mosi_io_num = SPI2_IOMUX_PIN_NUM_MOSI, .miso_io_num = SPI2_IOMUX_PIN_2_NUM_MISO, .sclk_io_num = SPI2_IOMUX_PIN_2_NUM_CLK, .quadhd_io_num = SPI2_IOMUX_PIN_NUM_HD, .quadwp_io_num = SPI2_IOMUX_PIN_2_NUM_WP,
+    };
+    TEST_ESP_OK(spicommon_bus_initialize_io(TEST_SPI_HOST, &cfg, flags_expected | SPICOMMON_BUSFLAG_SLAVE, &flags_o));
+    TEST_ASSERT_EQUAL_HEX32(flags_expected, flags_o);
+#endif
 }

 TEST_CASE("SPI Master no response when switch from host1 (SPI2) to host2 (SPI3)", "[spi]")
@@ -934,7 +952,7 @@ void test_cmd_addr(spi_slave_task_context_t *slave_context, bool lsb_first)

    //initial master, mode 0, 1MHz
    spi_bus_config_t buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
-    buscfg.quadhd_io_num = UNCONNECTED_PIN;
+    buscfg.flags |= SPICOMMON_BUSFLAG_GPIO_PINS;
    TEST_ESP_OK(spi_bus_initialize(TEST_SPI_HOST, &buscfg, SPI_DMA_CH_AUTO));
    spi_device_interface_config_t devcfg = SPI_DEVICE_TEST_DEFAULT_CONFIG();
    devcfg.clock_speed_hz = 1 * 1000 * 1000;
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -35,27 +35,6 @@
 /********************************************************************************
 *      Test SIO
 ********************************************************************************/
-#if CONFIG_IDF_TARGET_ESP32
-#define MASTER_DIN_SIGNAL    HSPID_IN_IDX
-#elif CONFIG_IDF_TARGET_ESP32P4
-#define MASTER_DIN_SIGNAL    SPI2_D_PAD_IN_IDX
-#else
-#define MASTER_DIN_SIGNAL    FSPID_IN_IDX
-#endif
-static void inner_connect(spi_bus_config_t bus)
-{
-    //Master MOSI(spid_out) output to `mosi_num`
-    spitest_gpio_output_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_out);
-    //Slave MOSI(spid_in) input to `mosi_num`
-    spitest_gpio_input_sel(bus.mosi_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spid_in);
-
-    //Master MOSI input(spid_in) to `miso_num`, due to SIO mode, we use Master's `spid_in` to receive data
-    spitest_gpio_input_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in);
-    //Slave MISO output(spiq_out)
-    spitest_gpio_output_sel(bus.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SLAVE_HOST].spiq_out);
-    //Force this signal goes through gpio matrix
-    GPIO.func_in_sel_cfg[MASTER_DIN_SIGNAL].sig_in_sel = 1;
-}

 TEST_CASE("SPI Single Board Test SIO", "[spi]")
 {
@@ -76,7 +55,8 @@ TEST_CASE("SPI Single Board Test SIO", "[spi]")
    TEST_ESP_OK(spi_slave_initialize(TEST_SLAVE_HOST, &bus_cfg, &slv_cfg, SPI_DMA_DISABLED));

    same_pin_func_sel(TEST_SPI_HOST, TEST_SLAVE_HOST, bus_cfg, dev_cfg.spics_io_num);
-    inner_connect(bus_cfg);
+    // fix sio internal connection
+    spitest_gpio_input_sel(bus_cfg.miso_io_num, FUNC_GPIO, spi_periph_signal[TEST_SPI_HOST].spid_in);

    WORD_ALIGNED_ATTR uint8_t master_rx_buffer[320];
    WORD_ALIGNED_ATTR uint8_t slave_rx_buffer[320];
@@ -85,6 +85,6 @@ def test_master_esp_flash(case_tester) -> None:  # type: ignore
    indirect=True,
 )
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
+@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='no runner')
 def test_master_multi_dev(case_tester) -> None:  # type: ignore
    case_tester.run_all_multi_dev_cases(reset=True)
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
@@ -106,8 +106,8 @@ static void local_test_start(spi_device_handle_t *spi, int freq, const spitest_p
        devcfg.spics_io_num = MASTER_IOMUX_PIN_CS;
        slvcfg.spics_io_num = MASTER_IOMUX_PIN_CS;
    }
-    //this does nothing, but avoid the driver from using iomux pins if required
-    buscfg.quadhd_io_num = (!pset->master_iomux && !pset->slave_iomux ? UNCONNECTED_PIN : -1);
+    bool use_iomux = pset->master_iomux || pset->slave_iomux;
+    buscfg.flags |= (use_iomux ? 0 : SPICOMMON_BUSFLAG_GPIO_PINS);
    devcfg.mode = pset->mode;
    const int cs_pretrans_max = 15;
    if (pset->dup == HALF_DUPLEX_MISO) {
@@ -721,10 +721,8 @@ static void test_master_start(spi_device_handle_t *spi, int freq, const spitest_
 {
    //master config
    spi_bus_config_t buspset = SPI_BUS_TEST_DEFAULT_CONFIG();
-    //this does nothing, but avoid the driver from using native pins
-    if (!pset->master_iomux) {
-        buspset.quadhd_io_num = UNCONNECTED_PIN;
-    }
+    buspset.flags |= (pset->master_iomux ? 0 : SPICOMMON_BUSFLAG_GPIO_PINS);
+
    spi_device_interface_config_t devpset = SPI_DEVICE_TEST_DEFAULT_CONFIG();
    devpset.spics_io_num = PIN_NUM_CS;
    devpset.mode = pset->mode;
@@ -865,10 +863,8 @@ static void timing_slave_start(int speed, const spitest_param_set_t *pset, spite
 {
    //slave config
    spi_bus_config_t slv_buscfg = SPI_BUS_TEST_DEFAULT_CONFIG();
-    //this does nothing, but avoid the driver from using native pins
-    if (!pset->slave_iomux) {
-        slv_buscfg.quadhd_io_num = UNCONNECTED_PIN;
-    }
+    slv_buscfg.flags |= (pset->slave_iomux ? 0 : SPICOMMON_BUSFLAG_GPIO_PINS);
+
    spi_slave_interface_config_t slvcfg = SPI_SLAVE_TEST_DEFAULT_CONFIG();
    slvcfg.spics_io_num = PIN_NUM_CS;
    slvcfg.mode = pset->mode;
@@ -6,7 +6,6 @@ from pytest_embedded_idf.utils import idf_parametrize

@pytest.mark.generic
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
 def test_param_single_dev(case_tester) -> None:  # type: ignore
    case_tester.run_all_normal_cases(reset=True)

@@ -14,6 +13,6 @@ def test_param_single_dev(case_tester) -> None:  # type: ignore
@pytest.mark.generic_multi_device
@pytest.mark.parametrize('count', [2], indirect=True)
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
+@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='no runner')
 def test_param_multi_dev(case_tester) -> None:  # type: ignore
    case_tester.run_all_multi_dev_cases(reset=True)
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
@@ -32,6 +32,7 @@ def test_slave_single_dev_esp32c5_rev1(case_tester) -> None:  # type: ignore
@pytest.mark.generic_multi_device
@pytest.mark.parametrize('count, config', [(2, 'release'), (2, 'iram_safe')], indirect=True)
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
+@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='no runner')
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
 def test_slave_multi_dev(case_tester) -> None:  # type: ignore
    case_tester.run_all_multi_dev_cases(reset=True)
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
@@ -28,5 +28,6 @@ def test_slave_hd_single_dev_esp32c5_rev1(case_tester) -> None:  # type: ignore
@pytest.mark.generic_multi_device
@pytest.mark.parametrize('count, config', [(2, 'release')], indirect=True)
@idf_parametrize('target', soc_filtered_targets('SOC_SPI_SUPPORT_SLAVE_HD_VER2 == 1'), indirect=['target'])
+@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='no runner')
 def test_slave_hd_multi_dev(case_tester) -> None:  # type: ignore
    case_tester.run_all_multi_dev_cases(reset=True)
@@ -23,7 +23,7 @@
 #define SPI_D2WD_PIN_NUM_WP         7
 #define SPI_D2WD_PIN_NUM_HD         11

-#define SPI2_FUNC_NUM           1
+#define SPI2_FUNC_NUM_QUAD      1
 #define SPI2_IOMUX_PIN_NUM_MISO 12
 #define SPI2_IOMUX_PIN_NUM_MOSI 13
 #define SPI2_IOMUX_PIN_NUM_CLK  14
@@ -54,7 +54,7 @@ const spi_signal_conn_t spi_periph_signal[3] = {
        .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
        .irq = ETS_SPI2_INTR_SOURCE,
        .irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
        .hw = &SPI2
    }, {
        .spiclk_out = VSPICLK_OUT_IDX,
@@ -16,7 +16,7 @@
 #define MSPI_IOMUX_PIN_NUM_MISO     17

 // GPSPI2 IOMUX PINs
-#define SPI2_FUNC_NUM               2
+#define SPI2_FUNC_NUM_QUAD          2
 #define SPI2_IOMUX_PIN_NUM_MISO     2
 #define SPI2_IOMUX_PIN_NUM_HD       4
 #define SPI2_IOMUX_PIN_NUM_WP       5
@@ -57,6 +57,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_SPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    }
 };
@@ -16,7 +16,7 @@
 #define MSPI_IOMUX_PIN_NUM_MISO     17

 // GPSPI2 IOMUX PINs
-#define SPI2_FUNC_NUM               2
+#define SPI2_FUNC_NUM_QUAD          2
 #define SPI2_IOMUX_PIN_NUM_MISO     2
 #define SPI2_IOMUX_PIN_NUM_HD       4
 #define SPI2_IOMUX_PIN_NUM_WP       5
@@ -57,6 +57,6 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_SPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    }
 };
@@ -17,7 +17,7 @@
 #define MSPI_IOMUX_PIN_NUM_CS1      15

 // GPSPI2 IOMUX PINs
-#define SPI2_FUNC_NUM               2
+#define SPI2_FUNC_NUM_QUAD          2
 #define SPI2_IOMUX_PIN_NUM_MISO     2
 #define SPI2_IOMUX_PIN_NUM_HD       4
 #define SPI2_IOMUX_PIN_NUM_WP       5
@@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_GPSPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    },
 };

@@ -16,7 +16,7 @@
 #define MSPI_IOMUX_PIN_NUM_MISO     25

 // GPSPI2 IOMUX PINs
-#define SPI2_FUNC_NUM               2
+#define SPI2_FUNC_NUM_QUAD          2
 #define SPI2_IOMUX_PIN_NUM_MISO     2
 #define SPI2_IOMUX_PIN_NUM_HD       4
 #define SPI2_IOMUX_PIN_NUM_WP       5
@@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_GSPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    }
 };

@@ -17,7 +17,7 @@
 #define MSPI_IOMUX_PIN_NUM_HD       19

 // GPSPI2 IOMUX PINs
-#define SPI2_FUNC_NUM               2
+#define SPI2_FUNC_NUM_QUAD          2
 #define SPI2_IOMUX_PIN_NUM_MISO     2
 #define SPI2_IOMUX_PIN_NUM_HD       3
 #define SPI2_IOMUX_PIN_NUM_WP       4
@@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_GPSPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    },
 };

@@ -16,7 +16,7 @@
 #define MSPI_IOMUX_PIN_NUM_MISO     16

 // GPSPI2 IOMUX PINs
-#define SPI2_FUNC_NUM               2
+#define SPI2_FUNC_NUM_QUAD          2
 #define SPI2_IOMUX_PIN_NUM_MISO     0
 #define SPI2_IOMUX_PIN_NUM_HD       3
 #define SPI2_IOMUX_PIN_NUM_WP       2
@@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_GSPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    }
 };

@@ -17,7 +17,7 @@
 #define MSPI_IOMUX_PIN_NUM_MISO     21

 // GPSPI2 IOMUX PINs
-#define SPI2_FUNC_NUM               2
+#define SPI2_FUNC_NUM_QUAD          2
 #define SPI2_IOMUX_PIN_NUM_WP       0
 #define SPI2_IOMUX_PIN_NUM_HD       1
 #define SPI2_IOMUX_PIN_NUM_CLK      2
@@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_GPSPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    }
 };

@@ -15,7 +15,7 @@
 #define MSPI_IOMUX_PIN_NUM_CLK   11
 #define MSPI_IOMUX_PIN_NUM_MOSI  12

-#define SPI2_FUNC_NUM           2
+#define SPI2_FUNC_NUM_QUAD      2
 #define SPI2_IOMUX_PIN_NUM_MISO 15
 #define SPI2_IOMUX_PIN_NUM_HD   19
 #define SPI2_IOMUX_PIN_NUM_WP   18
@@ -35,7 +35,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_GPSPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    }, {
        .spiclk_out = FSPI3CLK_OUT_IDX,
        .spiclk_in = FSPI3CLK_IN_IDX,
@@ -24,7 +24,7 @@
 #define MSPI_IOMUX_PIN_NUM_DQS      GPIO_NUM_INVALID

 // Normal IOMUX pins
-#define SPI2_FUNC_NUM               3
+#define SPI2_FUNC_NUM_QUAD          3
 #define SPI2_IOMUX_PIN_NUM_HD       6
 #define SPI2_IOMUX_PIN_NUM_CS       7
 #define SPI2_IOMUX_PIN_NUM_MOSI     8
@@ -43,7 +43,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_SPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    }, {
        .spiclk_out = SPI3_CK_PAD_OUT_IDX,
        .spiclk_in = SPI3_CK_PAD_IN_IDX,
@@ -23,8 +23,8 @@

 // There are 2 sets of GPIO pins which could be routed to FSPICS0, FSPICLK, FSPID, FSPIQ, FSPIHD, FSPIWP.
 // However, there is only one set of GPIO pins which could be routed to FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7.
-// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows.
-#define SPI2_FUNC_NUM               4
+// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM_QUAD to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows.
+#define SPI2_FUNC_NUM_QUAD          4
 #define SPI2_IOMUX_PIN_NUM_HD       9
 #define SPI2_IOMUX_PIN_NUM_CS       10
 #define SPI2_IOMUX_PIN_NUM_MOSI     11
@@ -65,7 +65,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_SPI2_INTR_SOURCE,
        .irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    }, {
        .spiclk_out = SPI3_CLK_OUT_MUX_IDX,
        .spiclk_in = SPI3_CLK_IN_IDX,
@@ -23,8 +23,8 @@

 // There are 2 sets of GPIO pins which could be routed to FSPICS0, FSPICLK, FSPID, FSPIQ, FSPIHD, FSPIWP.
 // However, there is only one set of GPIO pins which could be routed to FSPIIO4, FSPIIO5, FSPIIO6, FSPIIO7.
-// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows.
-#define SPI2_FUNC_NUM               4
+// As default (when we are not going to use Octal SPI), we make use of SPI2_FUNC_NUM_QUAD to route one of the 2 sets of GPIO pins to FSPICS0 ~ FSPIWP as follows.
+#define SPI2_FUNC_NUM_QUAD          4
 #define SPI2_IOMUX_PIN_NUM_HD       9
 #define SPI2_IOMUX_PIN_NUM_CS       10
 #define SPI2_IOMUX_PIN_NUM_MOSI     11
@@ -65,7 +65,7 @@ const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
        .irq = ETS_SPI2_INTR_SOURCE,
        .irq_dma = -1,
        .hw = &GPSPI2,
-        .func = SPI2_FUNC_NUM,
+        .func = SPI2_FUNC_NUM_QUAD,
    }, {
        .spiclk_out = SPI3_CLK_OUT_IDX,
        .spiclk_in = SPI3_CLK_IN_IDX,
@@ -1,16 +1,13 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

 #pragma once

-// TODO: to be checked IDF-14734
-
-// MSPI IOMUX PINs
+// MSPI IOMUX PINs Please check iomux_mspi_pin_struct/reg.h
 // On S31, SPI pins defined here are all wrong. these pins are individual pins, don't use normal GPIO pins anymore.
-// Please check iomux_mspi_pin_struct/reg.h
 #define GPIO_NUM_INVALID            -1
 #define MSPI_IOMUX_PIN_NUM_CS1      GPIO_NUM_INVALID
 #define MSPI_IOMUX_PIN_NUM_HD       GPIO_NUM_INVALID
@@ -25,26 +22,34 @@
 #define MSPI_IOMUX_PIN_NUM_D7       GPIO_NUM_INVALID
 #define MSPI_IOMUX_PIN_NUM_DQS      GPIO_NUM_INVALID

-// Normal IOMUX pins
-#define SPI2_FUNC_NUM               3
-#define SPI2_IOMUX_PIN_NUM_HD       6
-#define SPI2_IOMUX_PIN_NUM_CS       7
-#define SPI2_IOMUX_PIN_NUM_MOSI     8
-#define SPI2_IOMUX_PIN_NUM_CLK      9
-#define SPI2_IOMUX_PIN_NUM_MISO     10
-#define SPI2_IOMUX_PIN_NUM_WP       11
+// GPSPI2 has two sets of Qaud IOMUX pins
+#define SPI2_FUNC_NUM_QUAD          2
+#define SPI2_IOMUX_PIN_NUM_CLK      20
+#define SPI2_IOMUX_PIN_NUM_MOSI     21
+#define SPI2_IOMUX_PIN_NUM_MISO     22
+#define SPI2_IOMUX_PIN_NUM_CS       23
+#define SPI2_IOMUX_PIN_NUM_HD       24
+#define SPI2_IOMUX_PIN_NUM_WP       25
+
+#define SPI2_IOMUX_PIN_2_NUM_CS     52
+#define SPI2_IOMUX_PIN_2_NUM_CLK    53
+#define SPI2_IOMUX_PIN_2_NUM_MOSI   54
+#define SPI2_IOMUX_PIN_2_NUM_MISO   55
+#define SPI2_IOMUX_PIN_2_NUM_HD     56
+#define SPI2_IOMUX_PIN_2_NUM_WP     57

 // When using Octal SPI, we make use of SPI2_FUNC_NUM_OCT to route them as follows.
-#define SPI2_FUNC_NUM_OCT           2
-#define SPI2_IOMUX_PIN_NUM_HD_OCT   32
-#define SPI2_IOMUX_PIN_NUM_CS_OCT   28
-#define SPI2_IOMUX_PIN_NUM_MOSI_OCT 29
-#define SPI2_IOMUX_PIN_NUM_CLK_OCT  30
-#define SPI2_IOMUX_PIN_NUM_MISO_OCT 31
-#define SPI2_IOMUX_PIN_NUM_WP_OCT   33
-#define SPI2_IOMUX_PIN_NUM_IO4_OCT  34
-#define SPI2_IOMUX_PIN_NUM_IO5_OCT  35
-#define SPI2_IOMUX_PIN_NUM_IO6_OCT  36
-#define SPI2_IOMUX_PIN_NUM_IO7_OCT  37
+#define SPI2_FUNC_NUM_OCT           0
+#define SPI2_IOMUX_PIN_NUM_HD_OCT   9
+#define SPI2_IOMUX_PIN_NUM_CS_OCT   10
+#define SPI2_IOMUX_PIN_NUM_MOSI_OCT 11
+#define SPI2_IOMUX_PIN_NUM_CLK_OCT  12
+#define SPI2_IOMUX_PIN_NUM_MISO_OCT 13
+#define SPI2_IOMUX_PIN_NUM_WP_OCT   14
+#define SPI2_IOMUX_PIN_NUM_IO4_OCT  15
+#define SPI2_IOMUX_PIN_NUM_IO5_OCT  16
+#define SPI2_IOMUX_PIN_NUM_IO6_OCT  17
+#define SPI2_IOMUX_PIN_NUM_IO7_OCT  18
+#define SPI2_IOMUX_PIN_NUM_DQS_OCT  19

 //SPI3 have no iomux pins
@@ -0,0 +1,125 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include "soc/spi_periph.h"
+
+/*
+ Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = {
+    {
+        // MSPI on S31 has dedicated iomux pins
+    }, {
+        .spiclk_out = SPI2_CK_PAD_OUT_IDX,
+        .spiclk_in = SPI2_CK_PAD_IN_IDX,
+        .spid_out = SPI2_D_PAD_OUT_IDX,
+        .spiq_out = SPI2_Q_PAD_OUT_IDX,
+        .spiwp_out = SPI2_WP_PAD_OUT_IDX,
+        .spihd_out = SPI2_HOLD_PAD_OUT_IDX,
+        .spid4_out = SPI2_IO4_PAD_OUT_IDX,
+        .spid5_out = SPI2_IO5_PAD_OUT_IDX,
+        .spid6_out = SPI2_IO6_PAD_OUT_IDX,
+        .spid7_out = SPI2_IO7_PAD_OUT_IDX,
+        .spid_in = SPI2_D_PAD_IN_IDX,
+        .spiq_in = SPI2_Q_PAD_IN_IDX,
+        .spiwp_in = SPI2_WP_PAD_IN_IDX,
+        .spihd_in = SPI2_HOLD_PAD_IN_IDX,
+        .spid4_in = SPI2_IO4_PAD_IN_IDX,
+        .spid5_in = SPI2_IO5_PAD_IN_IDX,
+        .spid6_in = SPI2_IO6_PAD_IN_IDX,
+        .spid7_in = SPI2_IO7_PAD_IN_IDX,
+        .spics_out = {SPI2_CS_PAD_OUT_IDX, SPI2_CS1_PAD_OUT_IDX, SPI2_CS2_PAD_OUT_IDX, SPI2_CS3_PAD_OUT_IDX, SPI2_CS4_PAD_OUT_IDX, SPI2_CS5_PAD_OUT_IDX},
+        .spics_in = SPI2_CS_PAD_IN_IDX,
+        .spiclk_iomux_pin = SPI2_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI2_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI2_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI2_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI2_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI2_IOMUX_PIN_NUM_CS,
+        .irq = ETS_SPI2_INTR_SOURCE,
+        .irq_dma = -1,
+        .hw = &GPSPI2,
+        .func = SPI2_FUNC_NUM_QUAD,
+    }, {
+        .spiclk_out = SPI3_CK_PAD_OUT_IDX,
+        .spiclk_in = SPI3_CK_PAD_IN_IDX,
+        .spid_out = SPI3_D_PAD_OUT_IDX,
+        .spiq_out = SPI3_QO_PAD_OUT_IDX,
+        .spiwp_out = SPI3_WP_PAD_OUT_IDX,
+        .spihd_out = SPI3_HOLD_PAD_OUT_IDX,
+        .spid_in = SPI3_D_PAD_IN_IDX,
+        .spiq_in = SPI3_Q_PAD_IN_IDX,
+        .spiwp_in = SPI3_WP_PAD_IN_IDX,
+        .spihd_in = SPI3_HOLD_PAD_IN_IDX,
+        .spics_out = {SPI3_CS_PAD_OUT_IDX, SPI3_CS1_PAD_OUT_IDX, SPI3_CS2_PAD_OUT_IDX},
+        .spics_in = SPI3_CS_PAD_IN_IDX,
+        //SPI3 doesn't have iomux pins
+        .spiclk_iomux_pin = -1,
+        .spid_iomux_pin = -1,
+        .spiq_iomux_pin = -1,
+        .spiwp_iomux_pin = -1,
+        .spihd_iomux_pin = -1,
+        .spics0_iomux_pin = -1,
+        .irq = ETS_SPI3_INTR_SOURCE,
+        .irq_dma = -1,
+        .hw = &GPSPI3,
+        .func = -1,
+    }
+};
+
+#if SOC_PAU_SUPPORTED
+/**
+ * Backup registers in Light sleep: (total cnt 29)
+ *
+ * cmd
+ * addr
+ * ctrl
+ * clock
+ * user
+ * user1
+ * user2
+ * ms_dlen
+ * misc
+ * dma_conf
+ * dma_int_ena
+ * data_buf[0-15]   // slave driver only
+ * slave
+ * slave1
+ */
+#define SPI_RETENTION_REGS_CNT 29
+static const uint32_t spi_regs_map[4] = {0x31ff, 0x33fffc0, 0x0, 0x0};
+#define SPI_REG_RETENTION_ENTRIES(num) { \
+    [0] = { .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_GPSPI_LINK(0), \
+                                               REG_SPI_BASE(num), REG_SPI_BASE(num), \
+                                               SPI_RETENTION_REGS_CNT, 0, 0, \
+                                               spi_regs_map[0], spi_regs_map[1], \
+                                               spi_regs_map[2], spi_regs_map[3]), \
+            .owner = ENTRY(0) }, \
+    /* Additional interrupt setting is required by idf SPI drivers after register recovered */ \
+    [1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_GPSPI_LINK(1), \
+                                            SPI_DMA_INT_SET_REG(num), \
+                                            SPI_TRANS_DONE_INT_SET | SPI_DMA_SEG_TRANS_DONE_INT_SET | SPI_SLV_CMD7_INT_SET | SPI_SLV_CMD8_INT_SET , \
+                                            UINT32_MAX, 1, 0), \
+            .owner = ENTRY(0) }, \
+}
+
+static const regdma_entries_config_t spi2_regs_retention[] = SPI_REG_RETENTION_ENTRIES(2);   // '2' for GPSPI2
+static const regdma_entries_config_t spi3_regs_retention[] = SPI_REG_RETENTION_ENTRIES(3);
+
+const spi_reg_retention_info_t spi_reg_retention_info[SOC_SPI_PERIPH_NUM - 1] = {   // '-1' to except mspi
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI2,
+        .entry_array = spi2_regs_retention,
+        .array_size = ARRAY_SIZE(spi2_regs_retention),
+    },
+    {
+        .module_id = SLEEP_RETENTION_MODULE_GPSPI3,
+        .entry_array = spi3_regs_retention,
+        .array_size = ARRAY_SIZE(spi3_regs_retention),
+    },
+};
+#endif // SOC_PAU_SUPPORTED
@@ -58,3 +58,4 @@ components/esp_lcd/test_apps/spi_lcd:
    - esp_driver_spi
  disable:
    - if: SOC_GPSPI_SUPPORTED != 1
+    - if: CONFIG_NAME == "virt_flash_enc" and SOC_FLASH_ENC_SUPPORTED != 1
@@ -1,4 +1,4 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 This test app is used to test LCDs with SPI interface.
@@ -14,7 +14,6 @@ from pytest_embedded_idf.utils import idf_parametrize
    indirect=True,
 )
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
 def test_spi_lcd(dut: Dut) -> None:
    dut.run_all_single_board_cases()

@@ -28,7 +27,6 @@ def test_spi_lcd(dut: Dut) -> None:
    indirect=True,
 )
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
-@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
 def test_spi_lcd_with_virt_flash_enc(dut: Dut) -> None:
    print(' - Erase flash')
    dut.serial.erase_flash()
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 This test app runs a few FATFS test cases in a FAT-formatted SD card.

@@ -71,6 +71,10 @@ config SOC_SDM_SUPPORTED
    bool
    default y

+config SOC_GPSPI_SUPPORTED
+    bool
+    default y
+
 config SOC_LEDC_SUPPORTED
    bool
    default y
@@ -443,6 +447,18 @@ config SOC_SPI_MAXIMUM_BUFFER_SIZE
    int
    default 64

+config SOC_SPI_SUPPORT_SLEEP_RETENTION
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_SLAVE_HD_VER2
+    bool
+    default y
+
+config SOC_SPI_SUPPORT_OCT
+    bool
+    default y
+
 config SOC_SPIRAM_XIP_SUPPORTED
    bool
    default y
@@ -57,7 +57,7 @@
 #define SOC_RMT_SUPPORTED               1
 // #define SOC_I2S_SUPPORTED               1      // TODO: [ESP32S31] IDF-14771
 #define SOC_SDM_SUPPORTED               1
-// #define SOC_GPSPI_SUPPORTED             1      // TODO: [ESP32S31] IDF-14734
+#define SOC_GPSPI_SUPPORTED             1
 #define SOC_LEDC_SUPPORTED              1
 // #define SOC_ISP_SUPPORTED               1      // TODO: [ESP32S31] IDF-14769
 // #define SOC_I2C_SUPPORTED               1      // TODO: [ESP32S31] IDF-14726
@@ -237,11 +237,11 @@
 #define SOC_MMU_PER_EXT_MEM_TARGET            (1) /*!< MMU is per physical external memory target (flash, psram) */

 /*-------------------------- SPI CAPS ----------------------------------------*/
-// TODO: [ESP32S31] IDF-14734
-#define SOC_SPI_PERIPH_NUM              3
-#define SOC_SPI_PERIPH_CS_NUM(i)        (((i)==0)? 2: (((i)==1)? 6: 3))
-#define SOC_SPI_MAXIMUM_BUFFER_SIZE     64
-#define SOC_SPI_MAX_BITWIDTH(host_id)   ((host_id == 2) ? 4 : 8) // Supported line mode: SPI3: 1, 2, 4, SPI1/2: 1, 2, 4, 8
+#define SOC_SPI_PERIPH_NUM                  3
+#define SOC_SPI_MAXIMUM_BUFFER_SIZE         64
+#define SOC_SPI_SUPPORT_SLEEP_RETENTION     1
+#define SOC_SPI_SUPPORT_SLAVE_HD_VER2       1
+#define SOC_SPI_SUPPORT_OCT                 1

 /*-------------------------- SPIRAM CAPS ----------------------------------------*/
 #define SOC_SPIRAM_XIP_SUPPORTED        1
@@ -5,15 +5,17 @@
 */
 #pragma once

-#include "soc/soc.h"
+#include "soc/reg_base.h"
 #ifdef __cplusplus
 extern "C" {
 #endif

+#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_GPSPI2_BASE + (i-2) * 0x1000) : (0))  // GPSPI2 and GPSPI3
+
 /** SPI_CMD_REG register
 *  Command control register
 */
-#define SPI_CMD_REG (DR_REG_SPI_BASE + 0x0)
+#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
 /** SPI_CONF_BITLEN : R/W; bitpos: [17:0]; default: 0;
 *  Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
 */
@@ -42,7 +44,7 @@ extern "C" {
 /** SPI_ADDR_REG register
 *  Address value register
 */
-#define SPI_ADDR_REG (DR_REG_SPI_BASE + 0x4)
+#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x4)
 /** SPI_USR_ADDR_VALUE : R/W; bitpos: [31:0]; default: 0;
 *  Address to slave. Can be configured in CONF state.
 */
@@ -54,7 +56,7 @@ extern "C" {
 /** SPI_CTRL_REG register
 *  SPI control register
 */
-#define SPI_CTRL_REG (DR_REG_SPI_BASE + 0x8)
+#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x8)
 /** SPI_DUMMY_OUT : R/W; bitpos: [3]; default: 0;
 *  0: In the dummy phase, the FSPI bus signals are not output. 1: In the dummy phase,
 *  the FSPI bus signals are output. Can be configured in CONF state.
@@ -187,7 +189,7 @@ extern "C" {
 /** SPI_CLOCK_REG register
 *  SPI clock control register
 */
-#define SPI_CLOCK_REG (DR_REG_SPI_BASE + 0xc)
+#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0xc)
 /** SPI_CLKCNT_L : R/W; bitpos: [5:0]; default: 3;
 *  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be
 *  0. Can be configured in CONF state.
@@ -242,7 +244,7 @@ extern "C" {
 /** SPI_USER_REG register
 *  SPI USER control register
 */
-#define SPI_USER_REG (DR_REG_SPI_BASE + 0x10)
+#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x10)
 /** SPI_DOUTDIN : R/W; bitpos: [0]; default: 0;
 *  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
 *  configured in CONF state.
@@ -413,7 +415,7 @@ extern "C" {
 /** SPI_USER1_REG register
 *  SPI USER control register 1
 */
-#define SPI_USER1_REG (DR_REG_SPI_BASE + 0x14)
+#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x14)
 /** SPI_USR_DUMMY_CYCLELEN : R/W; bitpos: [7:0]; default: 7;
 *  The length in spi_clk cycles of dummy phase. The register value shall be
 *  (cycle_num-1). Can be configured in CONF state.
@@ -459,7 +461,7 @@ extern "C" {
 /** SPI_USER2_REG register
 *  SPI USER control register 2
 */
-#define SPI_USER2_REG (DR_REG_SPI_BASE + 0x18)
+#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x18)
 /** SPI_USR_COMMAND_VALUE : R/W; bitpos: [15:0]; default: 0;
 *  The value of  command. Can be configured in CONF state.
 */
@@ -488,7 +490,7 @@ extern "C" {
 /** SPI_MS_DLEN_REG register
 *  SPI data bit length control register
 */
-#define SPI_MS_DLEN_REG (DR_REG_SPI_BASE + 0x1c)
+#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x1c)
 /** SPI_MS_DATA_BITLEN : R/W; bitpos: [17:0]; default: 0;
 *  The value of these bits is the configured SPI transmission data bit length in
 *  master mode DMA controlled transfer or CPU controlled transfer. The value is also
@@ -503,7 +505,7 @@ extern "C" {
 /** SPI_MISC_REG register
 *  SPI misc register
 */
-#define SPI_MISC_REG (DR_REG_SPI_BASE + 0x20)
+#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x20)
 /** SPI_CS0_DIS : R/W; bitpos: [0]; default: 0;
 *  SPI CS$n pin enable, 1: disable CS$n, 0: spi_cs$n signal is from/to CS$n pin. Can
 *  be configured in CONF state.
@@ -644,7 +646,7 @@ extern "C" {
 /** SPI_DIN_MODE_REG register
 *  SPI input delay mode configuration
 */
-#define SPI_DIN_MODE_REG (DR_REG_SPI_BASE + 0x24)
+#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x24)
 /** SPI_DIN0_MODE : R/W; bitpos: [1:0]; default: 0;
 *  the input signals are delayed by SPI module clock cycles, 0: input without delayed,
 *  1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input
@@ -729,7 +731,7 @@ extern "C" {
 /** SPI_DIN_NUM_REG register
 *  SPI input delay number configuration
 */
-#define SPI_DIN_NUM_REG (DR_REG_SPI_BASE + 0x28)
+#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x28)
 /** SPI_DIN0_NUM : R/W; bitpos: [1:0]; default: 0;
 *  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1:
 *  delayed by 2 cycles,...  Can be configured in CONF state.
@@ -798,7 +800,7 @@ extern "C" {
 /** SPI_DOUT_MODE_REG register
 *  SPI output delay mode configuration
 */
-#define SPI_DOUT_MODE_REG (DR_REG_SPI_BASE + 0x2c)
+#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x2c)
 /** SPI_DOUT0_MODE : R/W; bitpos: [0]; default: 0;
 *  The output signal $n is delayed by the SPI module clock, 0: output without delayed,
 *  1: output delay for a SPI module clock cycle at its negative edge. Can be
@@ -884,7 +886,7 @@ extern "C" {
 /** SPI_DMA_CONF_REG register
 *  SPI DMA control register
 */
-#define SPI_DMA_CONF_REG (DR_REG_SPI_BASE + 0x30)
+#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x30)
 /** SPI_DMA_OUTFIFO_EMPTY : RO; bitpos: [0]; default: 1;
 *  Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0:
 *  DMA TX FIFO is ready for sending data.
@@ -976,7 +978,7 @@ extern "C" {
 /** SPI_DMA_INT_ENA_REG register
 *  SPI interrupt enable register
 */
-#define SPI_DMA_INT_ENA_REG (DR_REG_SPI_BASE + 0x34)
+#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x34)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W; bitpos: [0]; default: 0;
 *  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@@ -1128,7 +1130,7 @@ extern "C" {
 /** SPI_DMA_INT_CLR_REG register
 *  SPI interrupt clear register
 */
-#define SPI_DMA_INT_CLR_REG (DR_REG_SPI_BASE + 0x38)
+#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x38)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WT; bitpos: [0]; default: 0;
 *  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@@ -1280,7 +1282,7 @@ extern "C" {
 /** SPI_DMA_INT_RAW_REG register
 *  SPI interrupt raw register
 */
-#define SPI_DMA_INT_RAW_REG (DR_REG_SPI_BASE + 0x3c)
+#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x3c)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
 *  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the
 *  receive data.  0: Others.
@@ -1454,7 +1456,7 @@ extern "C" {
 /** SPI_DMA_INT_ST_REG register
 *  SPI interrupt status register
 */
-#define SPI_DMA_INT_ST_REG (DR_REG_SPI_BASE + 0x40)
+#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x40)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO; bitpos: [0]; default: 0;
 *  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@@ -1606,7 +1608,7 @@ extern "C" {
 /** SPI_DMA_INT_SET_REG register
 *  SPI interrupt software set register
 */
-#define SPI_DMA_INT_SET_REG (DR_REG_SPI_BASE + 0x44)
+#define SPI_DMA_INT_SET_REG(i) (REG_SPI_BASE(i) + 0x44)
 /** SPI_DMA_INFIFO_FULL_ERR_INT_SET : WT; bitpos: [0]; default: 0;
 *  The software set bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
 */
@@ -1758,7 +1760,7 @@ extern "C" {
 /** SPI_W0_REG register
 *  SPI CPU-controlled buffer0
 */
-#define SPI_W0_REG (DR_REG_SPI_BASE + 0x98)
+#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x98)
 /** SPI_BUF0 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1770,7 +1772,7 @@ extern "C" {
 /** SPI_W1_REG register
 *  SPI CPU-controlled buffer1
 */
-#define SPI_W1_REG (DR_REG_SPI_BASE + 0x9c)
+#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x9c)
 /** SPI_BUF1 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1782,7 +1784,7 @@ extern "C" {
 /** SPI_W2_REG register
 *  SPI CPU-controlled buffer2
 */
-#define SPI_W2_REG (DR_REG_SPI_BASE + 0xa0)
+#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0xa0)
 /** SPI_BUF2 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1794,7 +1796,7 @@ extern "C" {
 /** SPI_W3_REG register
 *  SPI CPU-controlled buffer3
 */
-#define SPI_W3_REG (DR_REG_SPI_BASE + 0xa4)
+#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0xa4)
 /** SPI_BUF3 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1806,7 +1808,7 @@ extern "C" {
 /** SPI_W4_REG register
 *  SPI CPU-controlled buffer4
 */
-#define SPI_W4_REG (DR_REG_SPI_BASE + 0xa8)
+#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0xa8)
 /** SPI_BUF4 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1818,7 +1820,7 @@ extern "C" {
 /** SPI_W5_REG register
 *  SPI CPU-controlled buffer5
 */
-#define SPI_W5_REG (DR_REG_SPI_BASE + 0xac)
+#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0xac)
 /** SPI_BUF5 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1830,7 +1832,7 @@ extern "C" {
 /** SPI_W6_REG register
 *  SPI CPU-controlled buffer6
 */
-#define SPI_W6_REG (DR_REG_SPI_BASE + 0xb0)
+#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0xb0)
 /** SPI_BUF6 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1842,7 +1844,7 @@ extern "C" {
 /** SPI_W7_REG register
 *  SPI CPU-controlled buffer7
 */
-#define SPI_W7_REG (DR_REG_SPI_BASE + 0xb4)
+#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0xb4)
 /** SPI_BUF7 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1854,7 +1856,7 @@ extern "C" {
 /** SPI_W8_REG register
 *  SPI CPU-controlled buffer8
 */
-#define SPI_W8_REG (DR_REG_SPI_BASE + 0xb8)
+#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0xb8)
 /** SPI_BUF8 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1866,7 +1868,7 @@ extern "C" {
 /** SPI_W9_REG register
 *  SPI CPU-controlled buffer9
 */
-#define SPI_W9_REG (DR_REG_SPI_BASE + 0xbc)
+#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0xbc)
 /** SPI_BUF9 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1878,7 +1880,7 @@ extern "C" {
 /** SPI_W10_REG register
 *  SPI CPU-controlled buffer10
 */
-#define SPI_W10_REG (DR_REG_SPI_BASE + 0xc0)
+#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0xc0)
 /** SPI_BUF10 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1890,7 +1892,7 @@ extern "C" {
 /** SPI_W11_REG register
 *  SPI CPU-controlled buffer11
 */
-#define SPI_W11_REG (DR_REG_SPI_BASE + 0xc4)
+#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0xc4)
 /** SPI_BUF11 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1902,7 +1904,7 @@ extern "C" {
 /** SPI_W12_REG register
 *  SPI CPU-controlled buffer12
 */
-#define SPI_W12_REG (DR_REG_SPI_BASE + 0xc8)
+#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0xc8)
 /** SPI_BUF12 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1914,7 +1916,7 @@ extern "C" {
 /** SPI_W13_REG register
 *  SPI CPU-controlled buffer13
 */
-#define SPI_W13_REG (DR_REG_SPI_BASE + 0xcc)
+#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0xcc)
 /** SPI_BUF13 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1926,7 +1928,7 @@ extern "C" {
 /** SPI_W14_REG register
 *  SPI CPU-controlled buffer14
 */
-#define SPI_W14_REG (DR_REG_SPI_BASE + 0xd0)
+#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0xd0)
 /** SPI_BUF14 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1938,7 +1940,7 @@ extern "C" {
 /** SPI_W15_REG register
 *  SPI CPU-controlled buffer15
 */
-#define SPI_W15_REG (DR_REG_SPI_BASE + 0xd4)
+#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0xd4)
 /** SPI_BUF15 : R/W/SS; bitpos: [31:0]; default: 0;
 *  data buffer
 */
@@ -1950,7 +1952,7 @@ extern "C" {
 /** SPI_SLAVE_REG register
 *  SPI slave control register
 */
-#define SPI_SLAVE_REG (DR_REG_SPI_BASE + 0xe0)
+#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0xe0)
 /** SPI_CLK_MODE : R/W; bitpos: [1:0]; default: 0;
 *  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed
 *  one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3:
@@ -2059,7 +2061,7 @@ extern "C" {
 /** SPI_SLAVE1_REG register
 *  SPI slave control register 1
 */
-#define SPI_SLAVE1_REG (DR_REG_SPI_BASE + 0xe4)
+#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0xe4)
 /** SPI_SLV_DATA_BITLEN : R/W/SS; bitpos: [17:0]; default: 0;
 *  The transferred data bit length in SPI slave FD and HD mode.
 */
@@ -2085,7 +2087,7 @@ extern "C" {
 /** SPI_CLK_GATE_REG register
 *  SPI module clock and register clock control
 */
-#define SPI_CLK_GATE_REG (DR_REG_SPI_BASE + 0xe8)
+#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0xe8)
 /** SPI_CLK_EN : R/W; bitpos: [0]; default: 0;
 *  Set this bit to enable clk gate
 */
@@ -2112,7 +2114,7 @@ extern "C" {
 /** SPI_DATE_REG register
 *  Version control
 */
-#define SPI_DATE_REG (DR_REG_SPI_BASE + 0xf0)
+#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0xf0)
 /** SPI_DATE : R/W; bitpos: [27:0]; default: 37761424;
 *  SPI register version.
 */
@@ -1,5 +1,5 @@
 /**
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
 *
 *  SPDX-License-Identifier: Apache-2.0 OR MIT
 */
@@ -1343,214 +1343,18 @@ typedef union {


 /** Group: CPU-controlled data buffer */
-/** Type of w0 register
- *  SPI CPU-controlled buffer0
+/** Type of wn register
+ *  SPI CPU-controlled buffer
 */
 typedef union {
    struct {
-        /** buf0 : R/W/SS; bitpos: [31:0]; default: 0;
+        /** buf : R/W/SS; bitpos: [31:0]; default: 0;
         *  data buffer
         */
-        uint32_t buf0:32;
+        uint32_t buf:32;
    };
    uint32_t val;
-} spi_w0_reg_t;
-
-/** Type of w1 register
- *  SPI CPU-controlled buffer1
- */
-typedef union {
-    struct {
-        /** buf1 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf1:32;
-    };
-    uint32_t val;
-} spi_w1_reg_t;
-
-/** Type of w2 register
- *  SPI CPU-controlled buffer2
- */
-typedef union {
-    struct {
-        /** buf2 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf2:32;
-    };
-    uint32_t val;
-} spi_w2_reg_t;
-
-/** Type of w3 register
- *  SPI CPU-controlled buffer3
- */
-typedef union {
-    struct {
-        /** buf3 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf3:32;
-    };
-    uint32_t val;
-} spi_w3_reg_t;
-
-/** Type of w4 register
- *  SPI CPU-controlled buffer4
- */
-typedef union {
-    struct {
-        /** buf4 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf4:32;
-    };
-    uint32_t val;
-} spi_w4_reg_t;
-
-/** Type of w5 register
- *  SPI CPU-controlled buffer5
- */
-typedef union {
-    struct {
-        /** buf5 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf5:32;
-    };
-    uint32_t val;
-} spi_w5_reg_t;
-
-/** Type of w6 register
- *  SPI CPU-controlled buffer6
- */
-typedef union {
-    struct {
-        /** buf6 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf6:32;
-    };
-    uint32_t val;
-} spi_w6_reg_t;
-
-/** Type of w7 register
- *  SPI CPU-controlled buffer7
- */
-typedef union {
-    struct {
-        /** buf7 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf7:32;
-    };
-    uint32_t val;
-} spi_w7_reg_t;
-
-/** Type of w8 register
- *  SPI CPU-controlled buffer8
- */
-typedef union {
-    struct {
-        /** buf8 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf8:32;
-    };
-    uint32_t val;
-} spi_w8_reg_t;
-
-/** Type of w9 register
- *  SPI CPU-controlled buffer9
- */
-typedef union {
-    struct {
-        /** buf9 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf9:32;
-    };
-    uint32_t val;
-} spi_w9_reg_t;
-
-/** Type of w10 register
- *  SPI CPU-controlled buffer10
- */
-typedef union {
-    struct {
-        /** buf10 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf10:32;
-    };
-    uint32_t val;
-} spi_w10_reg_t;
-
-/** Type of w11 register
- *  SPI CPU-controlled buffer11
- */
-typedef union {
-    struct {
-        /** buf11 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf11:32;
-    };
-    uint32_t val;
-} spi_w11_reg_t;
-
-/** Type of w12 register
- *  SPI CPU-controlled buffer12
- */
-typedef union {
-    struct {
-        /** buf12 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf12:32;
-    };
-    uint32_t val;
-} spi_w12_reg_t;
-
-/** Type of w13 register
- *  SPI CPU-controlled buffer13
- */
-typedef union {
-    struct {
-        /** buf13 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf13:32;
-    };
-    uint32_t val;
-} spi_w13_reg_t;
-
-/** Type of w14 register
- *  SPI CPU-controlled buffer14
- */
-typedef union {
-    struct {
-        /** buf14 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf14:32;
-    };
-    uint32_t val;
-} spi_w14_reg_t;
-
-/** Type of w15 register
- *  SPI CPU-controlled buffer15
- */
-typedef union {
-    struct {
-        /** buf15 : R/W/SS; bitpos: [31:0]; default: 0;
-         *  data buffer
-         */
-        uint32_t buf15:32;
-    };
-    uint32_t val;
-} spi_w15_reg_t;
-
+} spi_wn_reg_t;

 /** Group: Version register */
 /** Type of date register
@@ -1588,22 +1392,7 @@ typedef struct {
    volatile spi_dma_int_st_reg_t dma_int_st;
    volatile spi_dma_int_set_reg_t dma_int_set;
    uint32_t reserved_048[20];
-    volatile spi_w0_reg_t w0;
-    volatile spi_w1_reg_t w1;
-    volatile spi_w2_reg_t w2;
-    volatile spi_w3_reg_t w3;
-    volatile spi_w4_reg_t w4;
-    volatile spi_w5_reg_t w5;
-    volatile spi_w6_reg_t w6;
-    volatile spi_w7_reg_t w7;
-    volatile spi_w8_reg_t w8;
-    volatile spi_w9_reg_t w9;
-    volatile spi_w10_reg_t w10;
-    volatile spi_w11_reg_t w11;
-    volatile spi_w12_reg_t w12;
-    volatile spi_w13_reg_t w13;
-    volatile spi_w14_reg_t w14;
-    volatile spi_w15_reg_t w15;
+    volatile spi_wn_reg_t data_buf[16];
    uint32_t reserved_0d8[2];
    volatile spi_slave_reg_t slave;
    volatile spi_slave1_reg_t slave1;
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 # SPI LCD and Touch Panel Example

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 ## LCD tjpgd example

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 ## SPI master half duplex EEPROM example

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 # SPI Host Driver Example

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 ## SPI slave example

@@ -1,4 +1,4 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 See README.md in the parent directory
@@ -1,4 +1,4 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 See README.md in the parent directory
@@ -1,4 +1,4 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 See README.md in the parent directory
@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
@@ -58,6 +58,9 @@ examples/storage/perf_benchmark:
    - if: IDF_TARGET == "esp32p4" and CONFIG_NAME in ["sdmmc_1line", "sdmmc_4line", "sdspi_1line"]
      temporary: true
      reason: lack of runners, build only # TODO: IDF-8970
+    - if: IDF_TARGET == "esp32s31"
+      temporary: true
+      reason: lack of runners, but spi_flash not supported yet

 examples/storage/sd_card/sdmmc:
  depends_components:
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 # Storage performance benchmark example

@@ -50,7 +50,8 @@ def test_examples_perf_benchmark_sdcard_sdmmc(dut: Dut) -> None:


@pytest.mark.temp_skip_ci(targets=['esp32'], reason='IDFCI-2059, temporary lack runner')
-@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='C5 C61 GPSPI same, so testing on C5 is enough')
+@pytest.mark.temp_skip_ci(targets=['esp32c61'], reason='GPSPI is same, testing on C5 is enough')
+@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='GPSPI is same, testing on C5 is enough')
@pytest.mark.sdcard_spimode
@pytest.mark.parametrize(
    'config',
@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |

 # SD Card example (SDSPI)