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Merge branch 'feature/esp32p4_eco5_support_v5.5' into 'release/v5.5'

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feat(gpio/ledc/uart/2ddma/ppa): ESP32P4 ECO5 related updates (v5.5)

See merge request espressif/esp-idf!42816
This commit is contained in:
morris
2025-10-27 15:50:42 +08:00
parent d939ad7db7 37f2d25897
commit a0de5f7387
49 changed files with 4442 additions and 19666 deletions
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components/esp_driver_ledc/src/ledc.c
+1 -1
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@@ -874,7 +874,7 @@ esp_err_t ledc_channel_config(const ledc_channel_config_t *ledc_conf)
/*set channel parameters*/
/* channel parameters decide how the waveform looks like in one period */
/* set channel duty and hpoint value, duty range is [0, (2**duty_res)], hpoint range is [0, (2**duty_res)-1] */
/* Note: On ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4, due to a hardware bug,
/* Note: On ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 (rev < 3.0), due to a hardware bug,
* 100% duty cycle (i.e. 2**duty_res) is not reachable when the binded timer selects the maximum duty
* resolution. For example, the max duty resolution on ESP32C3 is 14-bit width, then set duty to (2**14)
* will mess up the duty calculation in hardware.
components/esp_driver_ppa/include/driver/ppa.h
+25 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -127,6 +127,7 @@ typedef struct {
};
ppa_color_range_t yuv_range; /*!< When the color mode is any YUV color space, this field is to describe its color range */
ppa_color_conv_std_rgb_yuv_t yuv_std; /*!< When the color mode is any YUV color space, this field is to describe its YUV<->RGB conversion standard */
color_yuv422_pack_order_t yuv422_pack_order; /*!< When the color mode is YUV422, this field is to describe its data pack order */
} ppa_in_pic_blk_config_t;
/**
@@ -268,7 +269,12 @@ typedef struct {
uint32_t fill_block_w; /*!< The width of the block to be filled (unit: pixel) */
uint32_t fill_block_h; /*!< The height of the block to be filled (unit: pixel) */
color_pixel_argb8888_data_t fill_argb_color; /*!< The color to be filled, in ARGB8888 format */
union {
color_pixel_argb8888_data_t fill_argb_color; /*!< For any ARGB/RGB format color to be filled, use this field to fill A (if applicable)/R/G/B components */
color_pixel_gray8_data_t fill_gray8_color; /*!< For GRAY8 format color to be filled */
color_macroblock_yuv_data_t fill_yuv_color; /*!< For any YUV format color to be filled, use this field to fill Y/U/V components */
uint32_t fill_color_val; /*!< The color to be filled, in a raw 32-bit value. The interpretation of the value depends on the selected `fill_cm` */
};
ppa_trans_mode_t mode; /*!< Determines whether to block inside the operation functions, see `ppa_trans_mode_t` */
void *user_data; /*!< User registered data to be passed into `done_cb` callback function */
@@ -287,6 +293,23 @@ typedef struct {
*/
esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config_t *config);
/**
* @brief Configure the RGB888 to GRAY8 color conversion coefficients for ppa_do_scale_rotate_mirror and ppa_do_fill
*
* The gray value is calculated as: gray = (r_weight * R + g_weight * G + b_weight * B) >> 8
* Note: (r_weight + g_weight + b_weight) should equal to 256.
*
* @param r_weight Coefficient for R component, range: [0, 255]
* @param g_weight Coefficient for G component, range: [0, 255]
* @param b_weight Coefficient for B component, range: [0, 255]
* @return
* - ESP_OK: Set the RGB888 to GRAY color conversion formula successfully
* - ESP_ERR_NOT_SUPPORTED: Set the RGB888 to GRAY color conversion formula failed because the PPA peripheral does not support this feature
* - ESP_ERR_INVALID_ARG: Set the RGB888 to GRAY color conversion formula failed because of invalid argument
* - ESP_ERR_INVALID_STATE: Set the RGB888 to GRAY color conversion formula failed because the PPA peripheral not initialized
*/
esp_err_t ppa_set_rgb2gray_formula(uint8_t r_weight, uint8_t g_weight, uint8_t b_weight);
#ifdef __cplusplus
}
#endif
components/esp_driver_ppa/src/ppa_blend.c
+51 -10
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -140,6 +140,13 @@ bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_chann
// Configure PPA Blending engine
ppa_ll_blend_set_rx_bg_color_mode(platform->hal.dev, blend_trans_desc->in_bg.blend_cm);
if (COLOR_SPACE_TYPE((uint32_t)blend_trans_desc->in_bg.blend_cm) == COLOR_SPACE_YUV) {
ppa_ll_blend_set_rx_bg_yuv_range(platform->hal.dev, blend_trans_desc->in_bg.yuv_range);
ppa_ll_blend_set_rx_bg_yuv2rgb_std(platform->hal.dev, blend_trans_desc->in_bg.yuv_std);
}
if ((uint32_t)blend_trans_desc->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) {
ppa_ll_blend_set_rx_bg_yuv422_pack_order(platform->hal.dev, blend_trans_desc->in_bg.yuv422_pack_order);
}
ppa_ll_blend_enable_rx_bg_byte_swap(platform->hal.dev, blend_trans_desc->bg_byte_swap);
ppa_ll_blend_enable_rx_bg_rgb_swap(platform->hal.dev, blend_trans_desc->bg_rgb_swap);
ppa_ll_blend_configure_rx_bg_alpha(platform->hal.dev, blend_trans_desc->bg_alpha_update_mode, blend_trans_desc->bg_alpha_value);
@@ -153,6 +160,10 @@ bool ppa_blend_transaction_on_picked(uint32_t num_chans, const dma2d_trans_chann
ppa_ll_blend_configure_rx_fg_alpha(platform->hal.dev, blend_trans_desc->fg_alpha_update_mode, blend_trans_desc->fg_alpha_value);
ppa_ll_blend_set_tx_color_mode(platform->hal.dev, blend_trans_desc->out.blend_cm);
if (COLOR_SPACE_TYPE((uint32_t)blend_trans_desc->out.blend_cm) == COLOR_SPACE_YUV) {
ppa_ll_blend_set_tx_yuv_range(platform->hal.dev, blend_trans_desc->out.yuv_range);
ppa_ll_blend_set_tx_rgb2yuv_std(platform->hal.dev, blend_trans_desc->out.yuv_std);
}
// Color keying
color_pixel_rgb888_data_t rgb888_min = {.b = 0x00, .g = 0x00, .r = 0x00};
@@ -182,6 +193,41 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf
uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size;
ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0,
ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size");
ESP_RETURN_ON_FALSE(ppa_ll_blend_is_color_mode_supported(config->in_bg.blend_cm) && ppa_ll_blend_is_color_mode_supported(config->in_fg.blend_cm) && ppa_ll_blend_is_color_mode_supported(config->out.blend_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode");
// For YUV420 input/output: in desc, ha/hb/va/vb/x/y must be even number
// For YUV422 input/output: in desc, ha/hb/x must be even number
if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV420) {
ESP_RETURN_ON_FALSE(config->in_bg.pic_h % 2 == 0 && config->in_bg.pic_w % 2 == 0 &&
config->in_bg.block_h % 2 == 0 && config->in_bg.block_w % 2 == 0 &&
config->in_bg.block_offset_x % 2 == 0 && config->in_bg.block_offset_y % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y");
} else if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) {
ESP_RETURN_ON_FALSE(config->in_bg.pic_w % 2 == 0 && config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x");
}
// TODO: Support CLUT to support L4/L8 color mode
// else if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_L4) {
// ESP_RETURN_ON_FALSE(config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0,
// ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w and in_bg.block_offset_x must be even");
// }
if (config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_A4) { // || config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_L4
ESP_RETURN_ON_FALSE(config->in_fg.block_w % 2 == 0 && config->in_fg.block_offset_x % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w and in_fg.block_offset_x must be even");
}
if (config->out.blend_cm == PPA_BLEND_COLOR_MODE_YUV420) {
ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 &&
config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y");
} else if (config->out.blend_cm == PPA_BLEND_COLOR_MODE_YUV422) {
ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x");
}
ESP_RETURN_ON_FALSE(config->in_bg.block_w <= (config->in_bg.pic_w - config->in_bg.block_offset_x) &&
config->in_bg.block_h <= (config->in_bg.pic_h - config->in_bg.block_offset_y),
ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w/h + in_bg.block_offset_x/y does not fit in the in pic");
ESP_RETURN_ON_FALSE(config->in_fg.block_w <= (config->in_fg.pic_w - config->in_fg.block_offset_x) &&
config->in_fg.block_h <= (config->in_fg.pic_h - config->in_fg.block_offset_y),
ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w/h + in_fg.block_offset_x/y does not fit in the in pic");
color_space_pixel_format_t out_pixel_format = {
.color_type_id = config->out.blend_cm,
};
@@ -190,6 +236,9 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf
ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size");
ESP_RETURN_ON_FALSE(config->in_bg.block_w == config->in_fg.block_w && config->in_bg.block_h == config->in_fg.block_h,
ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w/h must be equal to in_fg.block_w/h");
ESP_RETURN_ON_FALSE(config->in_fg.block_w <= (config->out.pic_w - config->out.block_offset_x) &&
config->in_fg.block_h <= (config->out.pic_h - config->out.block_offset_y),
ESP_ERR_INVALID_ARG, TAG, "block does not fit in the out pic");
if (config->bg_byte_swap) {
PPA_CHECK_CM_SUPPORT_BYTE_SWAP("in_bg.blend", (uint32_t)config->in_bg.blend_cm);
}
@@ -218,15 +267,7 @@ esp_err_t ppa_do_blend(ppa_client_handle_t ppa_client, const ppa_blend_oper_conf
ESP_RETURN_ON_FALSE(config->fg_alpha_scale_ratio > 0 && config->fg_alpha_scale_ratio < 1, ESP_ERR_INVALID_ARG, TAG, "invalid fg_alpha_scale_ratio");
new_fg_alpha_value = (uint32_t)(config->fg_alpha_scale_ratio * 256);
}
// if (config->in_bg.blend_cm == PPA_BLEND_COLOR_MODE_L4) {
// ESP_RETURN_ON_FALSE(config->in_bg.block_w % 2 == 0 && config->in_bg.block_offset_x % 2 == 0,
// ESP_ERR_INVALID_ARG, TAG, "in_bg.block_w and in_bg.block_offset_x must be even");
// }
if (config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_A4) { // || config->in_fg.blend_cm == PPA_BLEND_COLOR_MODE_L4
ESP_RETURN_ON_FALSE(config->in_fg.block_w % 2 == 0 && config->in_fg.block_offset_x % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "in_fg.block_w and in_fg.block_offset_x must be even");
}
// To reduce complexity, color_mode, alpha_update_mode correctness are checked in their corresponding LL functions
// To reduce complexity, specific color_mode, alpha_update_mode correctness are checked in their corresponding LL functions
// Write back and invalidate necessary data (note that the window content is not continuous in the buffer)
// Write back in_bg_buffer, in_fg_buffer extended windows (alignment not necessary on C2M direction)
components/esp_driver_ppa/src/ppa_core.c
+13 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -513,3 +513,15 @@ bool ppa_transaction_done_cb(dma2d_channel_handle_t dma2d_chan, dma2d_event_data
return need_yield;
}
esp_err_t ppa_set_rgb2gray_formula(uint8_t r_weight, uint8_t g_weight, uint8_t b_weight)
{
ESP_RETURN_ON_FALSE(ppa_ll_srm_is_color_mode_supported(PPA_SRM_COLOR_MODE_GRAY8) || ppa_ll_blend_is_color_mode_supported(PPA_BLEND_COLOR_MODE_GRAY8), ESP_ERR_NOT_SUPPORTED, TAG, "GRAY color mode not supported");
ESP_RETURN_ON_FALSE((r_weight + g_weight + b_weight) == 256, ESP_ERR_INVALID_ARG, TAG, "invalid rgb2gray formula");
ESP_RETURN_ON_FALSE(s_platform.hal.dev, ESP_ERR_INVALID_STATE, TAG, "no PPA client registered yet");
_lock_acquire(&s_platform.mutex);
ppa_ll_set_rgb2gray_coeff(s_platform.hal.dev, r_weight, g_weight, b_weight);
_lock_release(&s_platform.mutex);
return ESP_OK;
}
components/esp_driver_ppa/src/ppa_fill.c
+18 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -77,7 +77,7 @@ bool ppa_fill_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channe
dma2d_start(dma2d_rx_chan);
// Configure PPA Blending engine
ppa_ll_blend_configure_filling_block(platform->hal.dev, &fill_trans_desc->fill_argb_color, fill_trans_desc->fill_block_w, fill_trans_desc->fill_block_h);
ppa_ll_blend_configure_filling_block(platform->hal.dev, fill_trans_desc->out.fill_cm, (void *)&fill_trans_desc->fill_color_val, fill_trans_desc->fill_block_w, fill_trans_desc->fill_block_h);
ppa_ll_blend_set_tx_color_mode(platform->hal.dev, fill_trans_desc->out.fill_cm);
ppa_ll_blend_start(platform->hal.dev, PPA_LL_BLEND_TRANS_MODE_FILL);
@@ -96,13 +96,28 @@ esp_err_t ppa_do_fill(ppa_client_handle_t ppa_client, const ppa_fill_oper_config
uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size;
ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0,
ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size");
ESP_RETURN_ON_FALSE(ppa_ll_blend_is_color_mode_supported((ppa_blend_color_mode_t)config->out.fill_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode");
// For YUV420 output: in desc, ha/hb/va/vb/x/y must be even number
// For YUV422 output: in desc, ha/hb/x must be even number
// if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV420) {
// ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 &&
// config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0,
// ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y");
// } else
if (config->out.fill_cm == PPA_FILL_COLOR_MODE_YUV422) {
ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x");
}
color_space_pixel_format_t out_pixel_format = {
.color_type_id = config->out.fill_cm,
};
uint32_t out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format);
uint32_t out_pic_len = config->out.pic_w * config->out.pic_h * out_pixel_depth / 8;
ESP_RETURN_ON_FALSE(out_pic_len <= config->out.buffer_size, ESP_ERR_INVALID_ARG, TAG, "out.pic_w/h mismatch with out.buffer_size");
// To reduce complexity, color_mode, fill_block_w/h correctness are checked in their corresponding LL functions
ESP_RETURN_ON_FALSE(config->fill_block_w <= (config->out.pic_w - config->out.block_offset_x) &&
config->fill_block_h <= (config->out.pic_h - config->out.block_offset_y),
ESP_ERR_INVALID_ARG, TAG, "block does not fit in the out pic");
// To reduce complexity, specific color_mode, fill_block_w/h correctness are checked in their corresponding LL functions
// Write back and invalidate necessary data (note that the window content is not continuous in the buffer)
// Write back and invalidate buffer extended window (alignment not necessary on C2M direction, but alignment strict on M2C direction)
components/esp_driver_ppa/src/ppa_priv.h
+7 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -174,7 +174,12 @@ typedef struct {
uint32_t fill_block_w;
uint32_t fill_block_h;
color_pixel_argb8888_data_t fill_argb_color;
union {
color_pixel_argb8888_data_t fill_argb_color;
color_pixel_gray8_data_t fill_gray8_color;
color_macroblock_yuv_data_t fill_yuv_color;
uint32_t fill_color_val;
};
ppa_trans_mode_t mode;
void *user_data;
components/esp_driver_ppa/src/ppa_srm.c
+23 -13
View File
@@ -100,13 +100,6 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel
dma2d_set_transfer_ability(dma2d_tx_chan, &dma_transfer_ability);
dma2d_set_transfer_ability(dma2d_rx_chan, &dma_transfer_ability);
// Configure the block size to be received by the SRM engine, which is passed from the 2D-DMA TX channel (i.e. 2D-DMA dscr-port mode)
dma2d_dscr_port_mode_config_t dma_dscr_port_mode_config = {
.block_h = (srm_trans_desc->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) ? PPA_LL_SRM_YUV420_BLOCK_SIZE : PPA_LL_SRM_DEFAULT_BLOCK_SIZE,
.block_v = (srm_trans_desc->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) ? PPA_LL_SRM_YUV420_BLOCK_SIZE : PPA_LL_SRM_DEFAULT_BLOCK_SIZE,
};
dma2d_configure_dscr_port_mode(dma2d_tx_chan, &dma_dscr_port_mode_config);
// YUV444 is not supported by PPA module, need to utilize 2D-DMA color space conversion feature to do a conversion
ppa_srm_color_mode_t ppa_in_color_mode = srm_trans_desc->in.srm_cm;
if (ppa_in_color_mode == PPA_SRM_COLOR_MODE_YUV444) {
@@ -129,6 +122,15 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel
dma2d_configure_color_space_conversion(dma2d_rx_chan, &dma_rx_csc);
}
// Configure the block size to be received by the SRM engine, which is passed from the 2D-DMA TX channel (i.e. 2D-DMA dscr-port mode)
uint32_t block_h = 0, block_v = 0;
ppa_ll_srm_get_dma_dscr_port_mode_block_size(platform->hal.dev, ppa_in_color_mode, ppa_ll_srm_get_mb_size(platform->hal.dev), &block_h, &block_v);
dma2d_dscr_port_mode_config_t dma_dscr_port_mode_config = {
.block_h = block_h,
.block_v = block_v,
};
dma2d_configure_dscr_port_mode(dma2d_tx_chan, &dma_dscr_port_mode_config);
dma2d_rx_event_callbacks_t dma_event_cbs = {
.on_recv_eof = ppa_transaction_done_cb,
};
@@ -145,6 +147,9 @@ bool ppa_srm_transaction_on_picked(uint32_t num_chans, const dma2d_trans_channel
ppa_ll_srm_set_rx_yuv_range(platform->hal.dev, srm_trans_desc->in.yuv_range);
ppa_ll_srm_set_rx_yuv2rgb_std(platform->hal.dev, srm_trans_desc->in.yuv_std);
}
if ((uint32_t)ppa_in_color_mode == COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422)) {
ppa_ll_srm_set_rx_yuv422_pack_order(platform->hal.dev, srm_trans_desc->in.yuv422_pack_order);
}
ppa_ll_srm_enable_rx_byte_swap(platform->hal.dev, srm_trans_desc->byte_swap);
ppa_ll_srm_enable_rx_rgb_swap(platform->hal.dev, srm_trans_desc->rgb_swap);
ppa_ll_srm_configure_rx_alpha(platform->hal.dev, srm_trans_desc->alpha_update_mode, srm_trans_desc->alpha_value);
@@ -177,22 +182,25 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s
uint32_t buf_alignment_size = (uint32_t)ppa_client->engine->platform->buf_alignment_size;
ESP_RETURN_ON_FALSE(((uint32_t)config->out.buffer & (buf_alignment_size - 1)) == 0 && (config->out.buffer_size & (buf_alignment_size - 1)) == 0,
ESP_ERR_INVALID_ARG, TAG, "out.buffer addr or out.buffer_size not aligned to cache line size");
ESP_RETURN_ON_FALSE(ppa_ll_srm_is_color_mode_supported(config->in.srm_cm) && ppa_ll_srm_is_color_mode_supported(config->out.srm_cm), ESP_ERR_INVALID_ARG, TAG, "unsupported color mode");
// For YUV420 input/output: in desc, ha/hb/va/vb/x/y must be even number
// For YUV422 input/output: in desc, ha/hb/x must be even number
if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV420) {
ESP_RETURN_ON_FALSE(config->in.pic_h % 2 == 0 && config->in.pic_w % 2 == 0 &&
config->in.block_h % 2 == 0 && config->in.block_w % 2 == 0 &&
config->in.block_offset_x % 2 == 0 && config->in.block_offset_y % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "YUV420 input does not support odd h/w/offset_x/offset_y");
} else if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV422) {
ESP_RETURN_ON_FALSE(config->in.pic_w % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x");
}
// TODO: P4 ECO2 support YUV422
// else if (config->in.srm_cm == PPA_SRM_COLOR_MODE_YUV422) {
// ESP_RETURN_ON_FALSE(config->in.pic_w % 2 == 0 && config->in.block_w % 2 == 0 && config->in.block_offset_x % 2 == 0,
// ESP_ERR_INVALID_ARG, TAG, "YUV422 input does not support odd w/offset_x");
// }
if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV420) {
ESP_RETURN_ON_FALSE(config->out.pic_h % 2 == 0 && config->out.pic_w % 2 == 0 &&
config->out.block_offset_x % 2 == 0 && config->out.block_offset_y % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "YUV420 output does not support odd h/w/offset_x/offset_y");
} else if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV422) {
ESP_RETURN_ON_FALSE(config->out.pic_w % 2 == 0 && config->out.block_offset_x % 2 == 0,
ESP_ERR_INVALID_ARG, TAG, "YUV422 output does not support odd w/offset_x");
}
ESP_RETURN_ON_FALSE(config->in.block_w <= (config->in.pic_w - config->in.block_offset_x) &&
config->in.block_h <= (config->in.pic_h - config->in.block_offset_y),
@@ -232,7 +240,7 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s
ESP_RETURN_ON_FALSE(config->alpha_scale_ratio > 0 && config->alpha_scale_ratio < 1, ESP_ERR_INVALID_ARG, TAG, "invalid alpha_scale_ratio");
new_alpha_value = (uint32_t)(config->alpha_scale_ratio * 256);
}
// To reduce complexity, rotation_angle, color_mode, alpha_update_mode correctness are checked in their corresponding LL functions
// To reduce complexity, rotation_angle, alpha_update_mode correctness are checked in their corresponding LL functions
// Write back and invalidate necessary data (note that the window content is not continuous in the buffer)
// Write back in_buffer extended window (alignment not necessary on C2M direction)
@@ -270,6 +278,8 @@ esp_err_t ppa_do_scale_rotate_mirror(ppa_client_handle_t ppa_client, const ppa_s
if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV420) {
srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1;
srm_trans_desc->scale_y_frag = srm_trans_desc->scale_y_frag & ~1;
} else if (config->out.srm_cm == PPA_SRM_COLOR_MODE_YUV422) {
srm_trans_desc->scale_x_frag = srm_trans_desc->scale_x_frag & ~1;
}
srm_trans_desc->alpha_value = new_alpha_value;
srm_trans_desc->data_burst_length = ppa_client->data_burst_length;
components/esp_driver_ppa/test_apps/main/ppa_performance.h
+31
View File
@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "sdkconfig.h"
/*
* The time spend (T) to complete a PPA transaction is proportional to the amount of pixels (x) need to be processed.
* T = k * x + b
* k = (T - b) / x
*/
#if CONFIG_IDF_TARGET_ESP32P4
#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (21000 * 1000) // k_min
#define PPA_SRM_TIME_OFFSET (-26000) // b_approx
#else
#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (35000 * 1000) // k_min
#define PPA_SRM_TIME_OFFSET (-37000) // b_approx
#endif
#define PPA_BLEND_MIN_PERFORMANCE_PX_PER_SEC (31500 * 1000) // k_min
#define PPA_BLEND_TIME_OFFSET (-37150) // b_approx
#define PPA_FILL_MIN_PERFORMANCE_PX_PER_SEC (150000 * 1000) // k_min
#define PPA_FILL_TIME_OFFSET (-106000) // b_approx
#endif
components/esp_driver_ppa/test_apps/main/test_ppa.c
+49 -10
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -17,6 +17,7 @@
#include "ccomp_timer.h"
#include "hal/color_hal.h"
#include "esp_cache.h"
#include "ppa_performance.h"
#define ALIGN_UP(num, align) (((num) + ((align) - 1)) & ~((align) - 1))
@@ -350,6 +351,39 @@ TEST_CASE("ppa_srm_basic_data_correctness_check", "[PPA]")
printf("\n");
TEST_ASSERT_EQUAL_UINT8_ARRAY((void *)out_buf_expected, (void *)out_buf, buf_len);
#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
// Test a rgb2gray color conversion
memset(out_buf, 0, out_buf_size);
esp_cache_msync((void *)out_buf, out_buf_size, ESP_CACHE_MSYNC_FLAG_DIR_C2M);
const uint8_t r_weight = 100;
const uint8_t g_weight = 56;
const uint8_t b_weight = 100;
TEST_ESP_OK(ppa_set_rgb2gray_formula(r_weight, g_weight, b_weight));
oper_config.out.srm_cm = PPA_SRM_COLOR_MODE_GRAY8;
oper_config.rotation_angle = PPA_SRM_ROTATION_ANGLE_0;
uint8_t out_buf_expected_gray[16] = {};
for (int i = 0; i < block_w * block_h; i++) {
const uint16_t pix = in_buf[(i / block_w + in_block_offset_y) * w + (i % block_w + in_block_offset_x)];
uint8_t _r = ((pix >> 8) & 0xF8);
uint8_t _g = ((pix >> 3) & 0xFC);
uint8_t _b = ((pix << 3) & 0xF8);
out_buf_expected_gray[(i / block_w + out_block_offset_y) * w + (i % block_w + out_block_offset_x)] = (_r * r_weight + _g * g_weight + _b * b_weight) >> 8;
}
TEST_ESP_OK(ppa_do_scale_rotate_mirror(ppa_client_handle, &oper_config));
// Check result
for (int i = 0; i < w * h; i++) {
if (i % 4 == 0) {
printf("\n");
}
printf("0x%02X ", out_buf[i]);
}
printf("\n");
TEST_ASSERT_EQUAL_UINT8_ARRAY((void *)out_buf_expected_gray, (void *)out_buf, w * h);
#endif // !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
TEST_ESP_OK(ppa_unregister_client(ppa_client_handle));
free(out_buf);
@@ -526,6 +560,20 @@ TEST_CASE("ppa_fill_basic_data_correctness_check", "[PPA]")
};
TEST_ASSERT_EACH_EQUAL_UINT16(fill_pixel_expected.val, (void *)((uint32_t)out_buf + w * block_offset_y * out_pixel_depth / 8), block_w * block_h);
#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
// Test a yuv color fill
oper_config.out.fill_cm = PPA_FILL_COLOR_MODE_YUV422; // output YUV422 is with YVYU packed order
const color_macroblock_yuv_data_t fill_yuv_color = {.y = 0xFF, .u = 0x55, .v = 0xAA};
oper_config.fill_yuv_color = fill_yuv_color;
out_pixel_format.color_type_id = PPA_FILL_COLOR_MODE_YUV422;
out_pixel_depth = color_hal_pixel_format_get_bit_depth(out_pixel_format); // bits
TEST_ESP_OK(ppa_do_fill(ppa_client_handle, &oper_config));
// Check result (2 pixels per macro pixel)
const uint32_t fill_pixel_expected_yuv422 = ((fill_yuv_color.y << 24) | (fill_yuv_color.v << 16) | (fill_yuv_color.y << 8) | (fill_yuv_color.u));
TEST_ASSERT_EACH_EQUAL_UINT32(fill_pixel_expected_yuv422, (void *)((uint32_t)out_buf + w * block_offset_y * out_pixel_depth / 8), block_w * block_h / 2);
#endif // !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
TEST_ESP_OK(ppa_unregister_client(ppa_client_handle));
free(out_buf);
@@ -542,15 +590,6 @@ TEST_CASE("ppa_fill_basic_data_correctness_check", "[PPA]")
* k = (T - b) / x
*/
#define PPA_SRM_MIN_PERFORMANCE_PX_PER_SEC (21000 * 1000) // k_min
#define PPA_SRM_TIME_OFFSET (-26000) // b_approx
#define PPA_BLEND_MIN_PERFORMANCE_PX_PER_SEC (31500 * 1000) // k_min
#define PPA_BLEND_TIME_OFFSET (-37150) // b_approx
#define PPA_FILL_MIN_PERFORMANCE_PX_PER_SEC (150000 * 1000) // k_min
#define PPA_FILL_TIME_OFFSET (-106000) // b_approx
TEST_CASE("ppa_srm_performance", "[PPA]")
{
// Configurable parameters
components/esp_driver_sdmmc/test_apps/sdmmc/main/test_app_main.c
+1 -1
View File
@@ -10,7 +10,7 @@
#include "esp_newlib.h"
#include "sdkconfig.h"
#define TEST_MEMORY_LEAK_THRESHOLD (300)
#define TEST_MEMORY_LEAK_THRESHOLD (350)
void setUp(void)
{
components/esp_hw_support/dma/dma2d.c
+11 -12
View File
@@ -23,7 +23,6 @@
#include "hal/dma2d_ll.h"
#include "soc/dma2d_channel.h"
#include "soc/dma2d_periph.h"
#include "soc/soc_caps.h"
#include "esp_bit_defs.h"
/**
@@ -365,20 +364,20 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
_lock_acquire(&s_platform.mutex);
if (!s_platform.groups[group_id]) {
dma2d_group_t *pre_alloc_group = heap_caps_calloc(1, sizeof(dma2d_group_t), DMA2D_MEM_ALLOC_CAPS);
dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(SOC_DMA2D_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS);
dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(SOC_DMA2D_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS);
dma2d_tx_channel_t *pre_alloc_tx_channels = heap_caps_calloc(DMA2D_LL_TX_CHANNELS_PER_GROUP, sizeof(dma2d_tx_channel_t), DMA2D_MEM_ALLOC_CAPS);
dma2d_rx_channel_t *pre_alloc_rx_channels = heap_caps_calloc(DMA2D_LL_RX_CHANNELS_PER_GROUP, sizeof(dma2d_rx_channel_t), DMA2D_MEM_ALLOC_CAPS);
if (pre_alloc_group && pre_alloc_tx_channels && pre_alloc_rx_channels) {
pre_alloc_group->group_id = group_id;
pre_alloc_group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
TAILQ_INIT(&pre_alloc_group->pending_trans_tailq);
pre_alloc_group->tx_channel_free_mask = (1 << SOC_DMA2D_TX_CHANNELS_PER_GROUP) - 1;
pre_alloc_group->rx_channel_free_mask = (1 << SOC_DMA2D_RX_CHANNELS_PER_GROUP) - 1;
pre_alloc_group->tx_channel_free_mask = (1 << DMA2D_LL_TX_CHANNELS_PER_GROUP) - 1;
pre_alloc_group->rx_channel_free_mask = (1 << DMA2D_LL_RX_CHANNELS_PER_GROUP) - 1;
pre_alloc_group->tx_channel_reserved_mask = dma2d_tx_channel_reserved_mask[group_id];
pre_alloc_group->rx_channel_reserved_mask = dma2d_rx_channel_reserved_mask[group_id];
pre_alloc_group->tx_periph_m2m_free_id_mask = DMA2D_LL_TX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK;
pre_alloc_group->rx_periph_m2m_free_id_mask = DMA2D_LL_RX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK;
pre_alloc_group->intr_priority = -1;
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
pre_alloc_group->tx_chans[i] = &pre_alloc_tx_channels[i];
dma2d_tx_channel_t *tx_chan = pre_alloc_group->tx_chans[i];
tx_chan->base.group = pre_alloc_group;
@@ -386,7 +385,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
tx_chan->base.direction = DMA2D_CHANNEL_DIRECTION_TX;
tx_chan->base.spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
}
for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
pre_alloc_group->rx_chans[i] = &pre_alloc_rx_channels[i];
dma2d_rx_channel_t *rx_chan = pre_alloc_group->rx_chans[i];
rx_chan->base.group = pre_alloc_group;
@@ -435,7 +434,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
// Allocate TX and RX interrupts
if (s_platform.groups[group_id]) {
for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
dma2d_rx_channel_t *rx_chan = s_platform.groups[group_id]->rx_chans[i];
if (rx_chan->base.intr == NULL) {
ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].rx_irq_id[i],
@@ -450,7 +449,7 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
}
}
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
dma2d_tx_channel_t *tx_chan = s_platform.groups[group_id]->tx_chans[i];
if (tx_chan->base.intr == NULL) {
ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].tx_irq_id[i],
@@ -510,12 +509,12 @@ esp_err_t dma2d_release_pool(dma2d_pool_handle_t dma2d_pool)
}
if (do_deinitialize) {
for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
if (dma2d_group->rx_chans[i]->base.intr) {
esp_intr_free(dma2d_group->rx_chans[i]->base.intr);
}
}
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
if (dma2d_group->tx_chans[i]->base.intr) {
esp_intr_free(dma2d_group->tx_chans[i]->base.intr);
}
@@ -983,7 +982,7 @@ esp_err_t dma2d_force_end(dma2d_trans_t *trans, bool *need_yield)
// Stop the RX channel and its bundled TX channels first
dma2d_stop(&rx_chan->base);
uint32_t tx_chans = rx_chan->bundled_tx_channel_mask;
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
if (tx_chans & (1 << i)) {
dma2d_stop(&group->tx_chans[i]->base);
}
components/esp_hw_support/dma/dma2d_priv.h
+2 -2
View File
@@ -57,8 +57,8 @@ struct dma2d_group_t {
uint8_t rx_channel_reserved_mask; // Bit mask indicating the being reserved RX channels
uint32_t tx_periph_m2m_free_id_mask; // Bit mask indicating the available TX M2M peripheral selelction IDs at the moment
uint32_t rx_periph_m2m_free_id_mask; // Bit mask indicating the available RX M2M peripheral selelction IDs at the moment
dma2d_tx_channel_t *tx_chans[SOC_DMA2D_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels
dma2d_rx_channel_t *rx_chans[SOC_DMA2D_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels
dma2d_tx_channel_t *tx_chans[DMA2D_LL_TX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA TX channels
dma2d_rx_channel_t *rx_chans[DMA2D_LL_RX_CHANNELS_PER_GROUP]; // Handles of 2D-DMA RX channels
int intr_priority; // All channels in the same group should share the same interrupt priority
};
components/esp_hw_support/intr_alloc.c
+2 -2
View File
@@ -66,7 +66,7 @@ typedef struct vector_desc_t vector_desc_t;
struct shared_vector_desc_t {
int disabled: 1;
int source: 8;
int source: 16;
volatile uint32_t *statusreg;
uint32_t statusmask;
intr_handler_t isr;
@@ -94,7 +94,7 @@ struct vector_desc_t {
int flags: 16; //OR of VECDESC_FL_* defines
unsigned int cpu: 1;
unsigned int intno: 5;
int source: 8; //Interrupt mux flags, used when not shared
int source: 16; //Interrupt mux flags, used when not shared
shared_vector_desc_t *shared_vec_info; //used when VECDESC_FL_SHARED
vector_desc_t *next;
};
components/esp_hw_support/test_apps/dma2d/main/test_dma2d.c
+1 -1
View File
@@ -22,7 +22,7 @@
// This tests the hardware capability of multiple 2D-DMA transactions running together, and the driver capbility of
// transactions being send to a queue, and waiting for free channels becoming available, and being picked to start the
// real hardware operation.
#define M2M_TRANS_TIMES (8)
#define M2M_TRANS_TIMES (12)
// Descriptor and buffer address and size should aligned to 64 bytes (the cacheline size alignment restriction) to be used by CPU
components/esp_system/port/soc/esp32p4/Kconfig.cpu
+1
View File
@@ -14,6 +14,7 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
depends on ESP32P4_SELECTS_REV_LESS_V3
config ESP_DEFAULT_CPU_FREQ_MHZ_400
bool "400 MHz"
depends on !ESP32P4_SELECTS_REV_LESS_V3
endchoice
config ESP_DEFAULT_CPU_FREQ_MHZ
components/esp_system/port/soc/esp32p4/system_internal.c
+2 -2
View File
@@ -53,11 +53,11 @@ void esp_system_reset_modules_on_exit(void)
}
}
if (dma2d_ll_is_bus_clock_enabled(0)) {
for (int i = 0; i < SOC_DMA2D_RX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_RX_CHANNELS_PER_GROUP; i++) {
dma2d_ll_rx_abort(DMA2D_LL_GET_HW(0), i, true);
while (!dma2d_ll_rx_is_reset_avail(DMA2D_LL_GET_HW(0), i));
}
for (int i = 0; i < SOC_DMA2D_TX_CHANNELS_PER_GROUP; i++) {
for (int i = 0; i < DMA2D_LL_TX_CHANNELS_PER_GROUP; i++) {
dma2d_ll_tx_abort(DMA2D_LL_GET_HW(0), i, true);
while (!dma2d_ll_tx_is_reset_avail(DMA2D_LL_GET_HW(0), i));
}
components/hal/esp32p4/include/hal/dma2d_ll.h
+80 -104
View File
@@ -11,8 +11,10 @@
#include "hal/dma2d_types.h"
#include "soc/dma2d_channel.h"
#include "soc/dma2d_struct.h"
#include "soc/soc_caps.h"
#include "hal/misc.h"
#include "hal/assert.h"
#include "hal/config.h"
#include "soc/soc.h"
#include "soc/hp_sys_clkrst_struct.h"
@@ -22,6 +24,14 @@ extern "C" {
#define DMA2D_LL_GET_HW(id) (((id) == 0) ? (&DMA2D) : NULL)
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define DMA2D_LL_TX_CHANNELS_PER_GROUP SOC_DMA2D_TX_CHANNELS_PER_GROUP // Number of 2D-DMA TX (OUT) channels in each group
#define DMA2D_LL_RX_CHANNELS_PER_GROUP SOC_DMA2D_RX_CHANNELS_PER_GROUP // Number of 2D-DMA RX (IN) channels in each group
#else
#define DMA2D_LL_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group
#define DMA2D_LL_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group
#endif
// 2D-DMA interrupts
#define DMA2D_LL_RX_EVENT_MASK (0x3FFF)
#define DMA2D_LL_TX_EVENT_MASK (0x1FFF)
@@ -57,8 +67,11 @@ extern "C" {
// Bit masks that are used to indicate availability of some sub-features in the channels
#define DMA2D_LL_TX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // TX channels that support reorder feature
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
#define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2 | BIT3) // TX channels that support color space conversion feature
#else
#define DMA2D_LL_TX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0 | BIT1 | BIT2) // TX channels that support color space conversion feature
#endif
#define DMA2D_LL_RX_CHANNEL_SUPPORT_RO_MASK (0U | BIT0) // RX channels that support reorder feature
#define DMA2D_LL_RX_CHANNEL_SUPPORT_CSC_MASK (0U | BIT0) // RX channels that support color space conversion feature
@@ -158,16 +171,13 @@ static inline uint32_t dma2d_ll_get_scramble_order_sel(dma2d_scramble_order_t or
}
/////////////////////////////////////// RX ///////////////////////////////////////////
#define DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, ch, reg) ((volatile void*[]){&dev->in_channel0.reg, &dev->in_channel1.reg}[(ch)])
/**
* @brief Get 2D-DMA RX channel interrupt status word
*/
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_int_st_chn_reg_t *reg = (volatile dma2d_in_int_st_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st);
return reg->val;
return dev->in_channel[channel].in_int_st.val & DMA2D_LL_RX_EVENT_MASK;
}
/**
@@ -176,11 +186,10 @@ static inline uint32_t dma2d_ll_rx_get_interrupt_status(dma2d_dev_t *dev, uint32
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t channel, uint32_t mask, bool enable)
{
volatile dma2d_in_int_ena_chn_reg_t *reg = (volatile dma2d_in_int_ena_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_ena);
if (enable) {
reg->val = reg->val | (mask & DMA2D_LL_RX_EVENT_MASK);
dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val | (mask & DMA2D_LL_RX_EVENT_MASK);
} else {
reg->val = reg->val & ~(mask & DMA2D_LL_RX_EVENT_MASK);
dev->in_channel[channel].in_int_ena.val = dev->in_channel[channel].in_int_ena.val & ~(mask & DMA2D_LL_RX_EVENT_MASK);
}
}
@@ -190,8 +199,7 @@ static inline void dma2d_ll_rx_enable_interrupt(dma2d_dev_t *dev, uint32_t chann
__attribute__((always_inline))
static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t channel, uint32_t mask)
{
volatile dma2d_in_int_clr_chn_reg_t *reg = (volatile dma2d_in_int_clr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_clr);
reg->val = (mask & DMA2D_LL_RX_EVENT_MASK);
dev->in_channel[channel].in_int_clr.val = (mask & DMA2D_LL_RX_EVENT_MASK);
}
/**
@@ -199,7 +207,7 @@ static inline void dma2d_ll_rx_clear_interrupt_status(dma2d_dev_t *dev, uint32_t
*/
static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *dev, uint32_t channel)
{
return (volatile void *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_int_st);
return (volatile void *)(&dev->in_channel[channel].in_int_st);
}
/**
@@ -208,8 +216,7 @@ static inline volatile void *dma2d_ll_rx_get_interrupt_status_reg(dma2d_dev_t *d
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_check_owner_chn = enable;
dev->in_channel[channel].in_conf0.in_check_owner_chn = enable;
}
/**
@@ -218,8 +225,7 @@ static inline void dma2d_ll_rx_enable_owner_check(dma2d_dev_t *dev, uint32_t cha
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_page_bound_wrap(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_page_bound_en_chn = enable;
dev->in_channel[channel].in_conf0.in_page_bound_en_chn = enable;
}
/**
@@ -249,8 +255,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t
// Unsupported data burst length
abort();
}
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_mem_burst_length_chn = sel;
dev->in_channel[channel].in_conf0.in_mem_burst_length_chn = sel;
}
/**
@@ -259,8 +264,7 @@ static inline void dma2d_ll_rx_set_data_burst_length(dma2d_dev_t *dev, uint32_t
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->indscr_burst_en_chn = enable;
dev->in_channel[channel].in_conf0.indscr_burst_en_chn = enable;
}
/**
@@ -269,9 +273,8 @@ static inline void dma2d_ll_rx_enable_descriptor_burst(dma2d_dev_t *dev, uint32_
__attribute__((always_inline))
static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_rst_chn = 1;
reg->in_rst_chn = 0;
dev->in_channel[channel].in_conf0.in_rst_chn = 1;
dev->in_channel[channel].in_conf0.in_rst_chn = 0;
}
/**
@@ -280,8 +283,7 @@ static inline void dma2d_ll_rx_reset_channel(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state);
return reg->in_reset_avail_chn;
return dev->in_channel[channel].in_state.in_reset_avail_chn;
}
/**
@@ -290,8 +292,7 @@ static inline bool dma2d_ll_rx_is_reset_avail(dma2d_dev_t *dev, uint32_t channel
__attribute__((always_inline))
static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool disable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_cmd_disable_chn = disable;
dev->in_channel[channel].in_conf0.in_cmd_disable_chn = disable;
}
/**
@@ -300,8 +301,7 @@ static inline void dma2d_ll_rx_abort(dma2d_dev_t *dev, uint32_t channel, bool di
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_dscr_port(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_dscr_port_en_chn = enable;
dev->in_channel[channel].in_conf0.in_dscr_port_en_chn = enable;
}
/**
@@ -328,8 +328,7 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c
// Unsupported macro block size
abort();
}
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_macro_block_size_chn = sel;
dev->in_channel[channel].in_conf0.in_macro_block_size_chn = sel;
}
/**
@@ -338,9 +337,8 @@ static inline void dma2d_ll_rx_set_macro_block_size(dma2d_dev_t *dev, uint32_t c
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_pop_chn_reg_t *reg = (volatile dma2d_in_pop_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_pop);
reg->infifo_pop_chn = 1;
return reg->infifo_rdata_chn;
dev->in_channel[channel].in_pop.infifo_pop_chn = 1;
return dev->in_channel[channel].in_pop.infifo_rdata_chn;
}
/**
@@ -349,8 +347,7 @@ static inline uint32_t dma2d_ll_rx_pop_data(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel, uint32_t addr)
{
volatile dma2d_in_link_addr_chn_reg_t *reg = (volatile dma2d_in_link_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_addr);
reg->inlink_addr_chn = addr;
dev->in_channel[channel].in_link_addr.inlink_addr_chn = addr;
}
/**
@@ -359,8 +356,7 @@ static inline void dma2d_ll_rx_set_desc_addr(dma2d_dev_t *dev, uint32_t channel,
__attribute__((always_inline))
static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_start_chn = 1;
dev->in_channel[channel].in_link_conf.inlink_start_chn = 1;
}
/**
@@ -369,8 +365,7 @@ static inline void dma2d_ll_rx_start(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_stop_chn = 1;
dev->in_channel[channel].in_link_conf.inlink_stop_chn = 1;
}
/**
@@ -379,8 +374,7 @@ static inline void dma2d_ll_rx_stop(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_restart_chn = 1;
dev->in_channel[channel].in_link_conf.inlink_restart_chn = 1;
}
/**
@@ -389,8 +383,7 @@ static inline void dma2d_ll_rx_restart(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t channel, int owner)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
reg->inlink_auto_ret_chn = owner;
dev->in_channel[channel].in_link_conf.inlink_auto_ret_chn = owner;
}
/**
@@ -399,8 +392,7 @@ static inline void dma2d_ll_rx_set_auto_return_owner(dma2d_dev_t *dev, uint32_t
__attribute__((always_inline))
static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_link_conf_chn_reg_t *reg = (volatile dma2d_in_link_conf_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_link_conf);
return reg->inlink_park_chn;
return dev->in_channel[channel].in_link_conf.inlink_park_chn;
}
/**
@@ -409,8 +401,7 @@ static inline bool dma2d_ll_rx_is_desc_fsm_idle(dma2d_dev_t *dev, uint32_t chann
__attribute__((always_inline))
static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_state_chn_reg_t *reg = (volatile dma2d_in_state_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_state);
return (reg->in_state_chn == 0);
return (dev->in_channel[channel].in_state.in_state_chn == 0);
}
/**
@@ -419,8 +410,7 @@ static inline bool dma2d_ll_rx_is_fsm_idle(dma2d_dev_t *dev, uint32_t channel)
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_suc_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_suc_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_suc_eof_des_addr);
return reg->val;
return dev->in_channel[channel].in_suc_eof_des_addr.val;
}
/**
@@ -429,8 +419,7 @@ static inline uint32_t dma2d_ll_rx_get_success_eof_desc_addr(dma2d_dev_t *dev, u
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_err_eof_des_addr_chn_reg_t *reg = (volatile dma2d_in_err_eof_des_addr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_err_eof_des_addr);
return reg->val;
return dev->in_channel[channel].in_err_eof_des_addr.val;
}
/**
@@ -439,18 +428,7 @@ static inline uint32_t dma2d_ll_rx_get_error_eof_desc_addr(dma2d_dev_t *dev, uin
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_prefetched_desc_addr(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_dscr_chn_reg_t *reg = (volatile dma2d_in_dscr_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_dscr);
return reg->val;
}
/**
* @brief Set priority for 2D-DMA RX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
reg->in_arb_priority_chn = prio;
return dev->in_channel[channel].in_dscr.val;
}
/**
@@ -459,10 +437,8 @@ static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel,
__attribute__((always_inline))
static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t channel, dma2d_trigger_peripheral_t periph, int periph_id)
{
volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel);
peri_sel_reg->in_peri_sel_chn = periph_id;
volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
conf0_reg->in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M);
dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = periph_id;
dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = (periph == DMA2D_TRIG_PERIPH_M2M);
}
/**
@@ -471,10 +447,8 @@ static inline void dma2d_ll_rx_connect_to_periph(dma2d_dev_t *dev, uint32_t chan
__attribute__((always_inline))
static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_peri_sel_chn_reg_t *peri_sel_reg = (volatile dma2d_in_peri_sel_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_peri_sel);
peri_sel_reg->in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE;
volatile dma2d_in_conf0_chn_reg_t *conf0_reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
conf0_reg->in_mem_trans_en_chn = false;
dev->in_channel[channel].in_peri_sel.in_peri_sel_chn = DMA2D_LL_CHANNEL_PERIPH_NO_CHOICE;
dev->in_channel[channel].in_conf0.in_mem_trans_en_chn = false;
}
// REORDER FUNCTION (Only CH0 supports this feature)
@@ -485,8 +459,7 @@ static inline void dma2d_ll_rx_disconnect_from_periph(dma2d_dev_t *dev, uint32_t
__attribute__((always_inline))
static inline void dma2d_ll_rx_enable_reorder(dma2d_dev_t *dev, uint32_t channel, bool enable)
{
volatile dma2d_in_conf0_chn_reg_t *reg = (volatile dma2d_in_conf0_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_conf0);
reg->in_reorder_en_chn = enable;
dev->in_channel[channel].in_conf0.in_reorder_en_chn = enable;
}
// COLOR SPACE CONVERSION FUNCTION
@@ -524,6 +497,17 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
proc_en = false;
output_sel = 1;
break;
case DMA2D_CSC_RX_YUV444_TO_YUV422:
input_sel = 0;
proc_en = false;
output_sel = 2;
break;
case DMA2D_CSC_RX_YUV444_TO_YUV420:
case DMA2D_CSC_RX_YUV422_TO_YUV420:
input_sel = 0;
proc_en = false;
output_sel = 3;
break;
case DMA2D_CSC_RX_YUV420_TO_RGB888_601:
case DMA2D_CSC_RX_YUV422_TO_RGB888_601:
input_sel = 0;
@@ -581,13 +565,13 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
abort();
}
dev->in_channel0.in_color_convert.in_color_input_sel_chn = input_sel;
dev->in_channel0.in_color_convert.in_color_3b_proc_en_chn = proc_en;
dev->in_channel0.in_color_convert.in_color_output_sel_chn = output_sel;
dev->in_channel[channel].in_color_convert.in_color_input_sel_chn = input_sel;
dev->in_channel[channel].in_color_convert.in_color_3b_proc_en_chn = proc_en;
dev->in_channel[channel].in_color_convert.in_color_output_sel_chn = output_sel;
if (proc_en) {
HAL_ASSERT(table);
typeof(dev->in_channel0.in_color_param_group) color_param_group;
typeof(dev->in_channel[channel].in_color_param_group) color_param_group;
color_param_group.param_h.a = table[0][0];
color_param_group.param_h.b = table[0][1];
@@ -604,12 +588,12 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
color_param_group.param_l.c = table[2][2];
color_param_group.param_l.d = table[2][3];
dev->in_channel0.in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0];
dev->in_channel0.in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1];
dev->in_channel0.in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0];
dev->in_channel0.in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1];
dev->in_channel0.in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0];
dev->in_channel0.in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1];
dev->in_channel[channel].in_color_param_group.param_h.val[0] = color_param_group.param_h.val[0];
dev->in_channel[channel].in_color_param_group.param_h.val[1] = color_param_group.param_h.val[1];
dev->in_channel[channel].in_color_param_group.param_m.val[0] = color_param_group.param_m.val[0];
dev->in_channel[channel].in_color_param_group.param_m.val[1] = color_param_group.param_m.val[1];
dev->in_channel[channel].in_color_param_group.param_l.val[0] = color_param_group.param_l.val[0];
dev->in_channel[channel].in_color_param_group.param_l.val[1] = color_param_group.param_l.val[1];
}
}
@@ -620,7 +604,7 @@ __attribute__((always_inline))
static inline void dma2d_ll_rx_set_csc_pre_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order)
{
HAL_ASSERT(channel == 0); // Only channel 0 supports scramble
dev->in_channel0.in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order);
dev->in_channel[channel].in_scramble.in_scramble_sel_pre_chn = dma2d_ll_get_scramble_order_sel(order);
}
/**
@@ -630,7 +614,7 @@ __attribute__((always_inline))
static inline void dma2d_ll_rx_set_csc_post_scramble(dma2d_dev_t *dev, uint32_t channel, dma2d_scramble_order_t order)
{
HAL_ASSERT(channel == 0); // Only channel 0 supports scramble
dev->in_channel0.in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order);
dev->in_channel[channel].in_scramble.in_scramble_sel_post_chn = dma2d_ll_get_scramble_order_sel(order);
}
// Arbiter
@@ -659,8 +643,7 @@ static inline void dma2d_ll_rx_set_arb_timeout(dma2d_dev_t *dev, uint32_t timeou
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t channel, uint32_t token_num)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
reg->in_arb_token_num_chn = token_num;
dev->in_channel[channel].in_arb.in_arb_token_num_chn = token_num;
}
/**
@@ -669,20 +652,22 @@ static inline void dma2d_ll_rx_set_arb_token_num(dma2d_dev_t *dev, uint32_t chan
__attribute__((always_inline))
static inline uint32_t dma2d_ll_rx_get_arb_token_num(dma2d_dev_t *dev, uint32_t channel)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
return reg->in_arb_token_num_chn;
return dev->in_channel[channel].in_arb.in_arb_token_num_chn;
}
/**
* @brief Set 2D-DMA RX channel arbiter priority
* @brief Set priority for 2D-DMA RX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_rx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
static inline void dma2d_ll_rx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
{
volatile dma2d_in_arb_chn_reg_t *reg = (volatile dma2d_in_arb_chn_reg_t *)DMA2D_LL_IN_CHANNEL_GET_REG_ADDR(dev, channel, in_arb);
reg->in_arb_priority_chn = priority;
dev->in_channel[channel].in_arb.in_arb_priority_chn = priority;
}
// ETM
// note that in_ch1 in_etm_conf register addr is different before and after rev3 chip!
/////////////////////////////////////// TX ///////////////////////////////////////////
/**
* @brief Get 2D-DMA TX channel interrupt status word
@@ -954,15 +939,6 @@ static inline uint32_t dma2d_ll_tx_get_prefetched_desc_addr(dma2d_dev_t *dev, ui
return dev->out_channel[channel].out_dscr.val;
}
/**
* @brief Set priority for 2D-DMA TX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t prio)
{
dev->out_channel[channel].out_arb.out_arb_priority_chn = prio;
}
/**
* @brief Connect 2D-DMA TX channel to a given peripheral
*/
@@ -1165,10 +1141,10 @@ static inline uint32_t dma2d_ll_tx_get_arb_token_num(dma2d_dev_t *dev, uint32_t
}
/**
* @brief Set 2D-DMA TX channel arbiter priority
* @brief Set priority for 2D-DMA TX channel
*/
__attribute__((always_inline))
static inline void dma2d_ll_tx_set_arb_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
static inline void dma2d_ll_tx_set_priority(dma2d_dev_t *dev, uint32_t channel, uint32_t priority)
{
dev->out_channel[channel].out_arb.out_arb_priority_chn = priority;
}
components/hal/esp32p4/include/hal/ledc_ll.h
+3 -4
View File
@@ -245,7 +245,6 @@ static inline void ledc_ll_get_clock_divider(ledc_dev_t *hw, ledc_mode_t speed_m
static inline void ledc_ll_get_clock_source(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_timer_t timer_sel, ledc_clk_src_t *clk_src)
{
// The target has no timer-specific clock source option
HAL_ASSERT(hw->timer_group[speed_mode].timer[timer_sel].conf.tick_sel == 0);
*clk_src = LEDC_SCLK;
}
@@ -365,7 +364,7 @@ static inline void ledc_ll_set_duty_int_part(ledc_dev_t *hw, ledc_mode_t speed_m
*/
static inline void ledc_ll_get_duty(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *duty_val)
{
*duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty >> 4);
*duty_val = (hw->channel_group[speed_mode].channel[channel_num].duty_r.duty_r >> 4);
}
/**
@@ -406,7 +405,7 @@ static inline void ledc_ll_set_fade_param_range(ledc_dev_t *hw, ledc_mode_t spee
*/
static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t range_num)
{
hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num = range_num;
hw->chn_gamma_conf[channel_num].gamma_entry_num = range_num;
}
/**
@@ -421,7 +420,7 @@ static inline void ledc_ll_set_range_number(ledc_dev_t *hw, ledc_mode_t speed_mo
*/
static inline void ledc_ll_get_range_number(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint32_t *range_num)
{
*range_num = hw->chn_gamma_conf[channel_num].ch0_gamma_entry_num;
*range_num = hw->chn_gamma_conf[channel_num].gamma_entry_num;
}
/**
components/hal/esp32p4/include/hal/ppa_ll.h
+428 -6
View File
@@ -14,6 +14,7 @@
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/config.h"
#ifdef __cplusplus
extern "C" {
@@ -27,9 +28,15 @@ extern "C" {
#define PPA_LL_SRM_SCALING_INT_MAX (PPA_SR_SCAL_X_INT_V + 1)
#define PPA_LL_SRM_SCALING_FRAG_MAX (PPA_SR_SCAL_X_FRAG_V + 1)
// TODO: On P4 ECO2, SRM block size needs update
#define PPA_LL_SRM_DEFAULT_BLOCK_SIZE 18 // 18 x 18 block size
#define PPA_LL_SRM_YUV420_BLOCK_SIZE 20 // 20 x 20 block size
/**
* @brief Enumeration of PPA SRM macro block size options
*/
typedef enum {
PPA_LL_SRM_MB_SIZE_16_16, /*!< SRM engine processes with a macro block size of 16 x 16 */
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
PPA_LL_SRM_MB_SIZE_32_32, /*!< SRM engine processes with a macro block size of 32 x 32 */
#endif
} ppa_ll_srm_mb_size_t;
/**
* @brief Enumeration of PPA blending mode
@@ -68,6 +75,29 @@ static inline void ppa_ll_reset_register(void)
/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
#define ppa_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; ppa_ll_reset_register(__VA_ARGS__)
/**
* @brief Configure the RGB888 to GRAY8 color conversion coefficients for SRM and Blending (excluding Fill)
*
* The gray value is calculated as: gray = (r_coeff * R + g_coeff * G + b_coeff * B) >> 8
*
* @param dev Peripheral instance address
* @param r_coeff Coefficient for Red channel, range 0-255
* @param g_coeff Coefficient for Green channel, range 0-255
* @param b_coeff Coefficient for Blue channel, range 0-255
*/
static inline void ppa_ll_set_rgb2gray_coeff(ppa_dev_t *dev, uint8_t r_coeff, uint8_t g_coeff, uint8_t b_coeff)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
HAL_ASSERT((r_coeff + g_coeff + b_coeff == 256) && "Sum of RGB to GRAY coefficients must be 256");
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_r, r_coeff);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_g, g_coeff);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->rgb2gray, rgb2gray_b, b_coeff);
#else
// GRAY8 color mode is not supported by PPA hardware before P4 ECO5
abort();
#endif
}
///////////////////////// Scaling, Rotating, Mirroring (SRM) //////////////////////////////
/**
* @brief Reset PPA scaling-rotating-mirroring engine
@@ -169,6 +199,30 @@ static inline void ppa_ll_srm_start(ppa_dev_t *dev)
dev->sr_scal_rotate.scal_rotate_start = 1;
}
/**
* @brief Check if the given color mode is supported by PPA SRM engine
*
* @param color_mode One of the values in ppa_srm_color_mode_t
* @return true if supported; false if not supported
*/
static inline bool ppa_ll_srm_is_color_mode_supported(ppa_srm_color_mode_t color_mode)
{
switch (color_mode) {
case PPA_SRM_COLOR_MODE_ARGB8888:
case PPA_SRM_COLOR_MODE_RGB888:
case PPA_SRM_COLOR_MODE_RGB565:
case PPA_SRM_COLOR_MODE_YUV420:
case PPA_SRM_COLOR_MODE_YUV444: // YUV444 not supported by PPA hardware, but can be converted by 2D-DMA before/after PPA
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_SRM_COLOR_MODE_YUV422:
case PPA_SRM_COLOR_MODE_GRAY8:
#endif
return true;
default:
return false;
}
}
/**
* @brief Set the source image color mode for PPA Scaling-Rotating-Mirroring engine RX
*
@@ -191,6 +245,14 @@ static inline void ppa_ll_srm_set_rx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo
case PPA_SRM_COLOR_MODE_YUV420:
val = 8;
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_SRM_COLOR_MODE_YUV422:
val = 9;
break;
case PPA_SRM_COLOR_MODE_GRAY8:
val = 12;
break;
#endif
default:
// Unsupported SRM rx color mode
abort();
@@ -220,6 +282,14 @@ static inline void ppa_ll_srm_set_tx_color_mode(ppa_dev_t *dev, ppa_srm_color_mo
case PPA_SRM_COLOR_MODE_YUV420:
val = 8;
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_SRM_COLOR_MODE_YUV422:
val = 9;
break;
case PPA_SRM_COLOR_MODE_GRAY8:
val = 12;
break;
#endif
default:
// Unsupported SRM tx color mode
abort();
@@ -311,6 +381,38 @@ static inline void ppa_ll_srm_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t
}
}
/**
* @brief Set PPA SRM input side YUV422 data format packing order
*
* @param dev Peripheral instance address
* @param pack_order One of the pack order options in color_yuv422_pack_order_t
*/
static inline void ppa_ll_srm_set_rx_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (pack_order) {
case COLOR_YUV422_PACK_ORDER_YVYU:
dev->sr_color_mode.yuv422_rx_byte_order = 0;
break;
case COLOR_YUV422_PACK_ORDER_YUYV:
dev->sr_color_mode.yuv422_rx_byte_order = 1;
break;
case COLOR_YUV422_PACK_ORDER_VYUY:
dev->sr_color_mode.yuv422_rx_byte_order = 2;
break;
case COLOR_YUV422_PACK_ORDER_UYVY:
dev->sr_color_mode.yuv422_rx_byte_order = 3;
break;
default:
// Unsupported YUV422 pack order
abort();
}
#else
// YUV422 not supported by PPA SRM hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Enable PPA SRM input data swap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR)
*
@@ -371,6 +473,112 @@ static inline void ppa_ll_srm_configure_rx_alpha(ppa_dev_t *dev, ppa_alpha_updat
}
}
/**
* @brief Get the current configured PPA SRM macro block size
*
* @param dev Peripheral instance address
* @return The current configured macro block size, one of the values in ppa_ll_srm_mb_size_t
*/
static inline ppa_ll_srm_mb_size_t ppa_ll_srm_get_mb_size(ppa_dev_t *dev)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
return (dev->sr_byte_order.sr_bk_size_sel == 0) ? PPA_LL_SRM_MB_SIZE_32_32 : PPA_LL_SRM_MB_SIZE_16_16;
#else
return PPA_LL_SRM_MB_SIZE_16_16;
#endif
}
/**
* @brief Set PPA SRM macro block size
*
* @param dev Peripheral instance address
* @param mb_size Macro block size to be set, one of the values in ppa_ll_srm_mb_size_t
*/
static inline void ppa_ll_srm_set_mb_size(ppa_dev_t *dev, ppa_ll_srm_mb_size_t mb_size)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (mb_size) {
case PPA_LL_SRM_MB_SIZE_16_16:
dev->sr_byte_order.sr_bk_size_sel = 1;
break;
case PPA_LL_SRM_MB_SIZE_32_32:
dev->sr_byte_order.sr_bk_size_sel = 0;
break;
default:
// Unsupported SRM macro block size
abort();
}
#else
HAL_ASSERT(mb_size == PPA_LL_SRM_MB_SIZE_16_16);
#endif
}
/**
* @brief Retrieve the 2D-DMA descriptor port mode block size (in pixel) according to the PPA SRM input color mode and configured macro block size
*
* @param dev Peripheral instance address
* @param in_color_mode Input color mode, one of the values in ppa_srm_color_mode_t
* @param mb_size SRM macro block size, one of the values in ppa_ll_srm_mb_size_t
* @param[out] block_h Returned block horizontal width
* @param[out] block_v Returned block wvertical height
*/
static inline void ppa_ll_srm_get_dma_dscr_port_mode_block_size(ppa_dev_t *dev, ppa_srm_color_mode_t in_color_mode, ppa_ll_srm_mb_size_t mb_size, uint32_t *block_h, uint32_t *block_v)
{
if (mb_size == PPA_LL_SRM_MB_SIZE_16_16) {
switch (in_color_mode) {
case PPA_SRM_COLOR_MODE_ARGB8888:
case PPA_SRM_COLOR_MODE_RGB888:
case PPA_SRM_COLOR_MODE_RGB565:
case PPA_SRM_COLOR_MODE_GRAY8:
*block_h = 18;
*block_v = 18;
break;
case PPA_SRM_COLOR_MODE_YUV420:
*block_h = 20;
*block_v = 18;
break;
case PPA_SRM_COLOR_MODE_YUV422:
*block_h = 20;
*block_v = 20;
break;
default:
// Unsupported SRM input color mode
*block_h = 0;
*block_v = 0;
}
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
else if (mb_size == PPA_LL_SRM_MB_SIZE_32_32) {
switch (in_color_mode) {
case PPA_SRM_COLOR_MODE_ARGB8888:
case PPA_SRM_COLOR_MODE_RGB888:
case PPA_SRM_COLOR_MODE_RGB565:
case PPA_SRM_COLOR_MODE_GRAY8:
*block_h = 34;
*block_v = 34;
break;
case PPA_SRM_COLOR_MODE_YUV420:
*block_h = 36;
*block_v = 34;
break;
case PPA_SRM_COLOR_MODE_YUV422:
*block_h = 36;
*block_v = 36;
break;
default:
// Unsupported SRM input color mode
*block_h = 0;
*block_v = 0;
}
}
#endif
else {
// Unsupported SRM macro block size
*block_h = 0;
*block_v = 0;
}
}
//////////////////////////////////// Blending ////////////////////////////////////////
/*
* Alpha Blending Calculation:
@@ -420,6 +628,33 @@ static inline void ppa_ll_blend_start(ppa_dev_t *dev, ppa_ll_blend_trans_mode_t
dev->blend_trans_mode.blend_trans_mode_update = 1;
}
/**
* @brief Check if the given color mode is supported by PPA blending engine
*
* @param color_mode One of the values in ppa_blend_color_mode_t
* @return true if supported (by any of rx_bg, rx_fg, tx); false if not supported
*/
static inline bool ppa_ll_blend_is_color_mode_supported(ppa_blend_color_mode_t color_mode)
{
switch (color_mode) {
case PPA_BLEND_COLOR_MODE_ARGB8888:
case PPA_BLEND_COLOR_MODE_RGB888:
case PPA_BLEND_COLOR_MODE_RGB565:
case PPA_BLEND_COLOR_MODE_A8:
case PPA_BLEND_COLOR_MODE_A4:
// case PPA_BLEND_COLOR_MODE_L8:
// case PPA_BLEND_COLOR_MODE_L4:
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_BLEND_COLOR_MODE_YUV420:
case PPA_BLEND_COLOR_MODE_YUV422:
case PPA_BLEND_COLOR_MODE_GRAY8:
#endif
return true;
default:
return false;
}
}
/**
* @brief Set the source image color mode for background for PPA blending engine RX
*
@@ -445,6 +680,17 @@ static inline void ppa_ll_blend_set_rx_bg_color_mode(ppa_dev_t *dev, ppa_blend_c
// case PPA_BLEND_COLOR_MODE_L4:
// val = 5;
// break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_BLEND_COLOR_MODE_YUV420:
val = 8;
break;
case PPA_BLEND_COLOR_MODE_YUV422:
val = 9;
break;
case PPA_BLEND_COLOR_MODE_GRAY8:
val = 12;
break;
#endif
default:
// Unsupported blending rx background color mode
abort();
@@ -509,6 +755,17 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo
case PPA_BLEND_COLOR_MODE_RGB565:
val = 2;
break;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
case PPA_BLEND_COLOR_MODE_YUV420:
val = 8;
break;
case PPA_BLEND_COLOR_MODE_YUV422:
val = 9;
break;
case PPA_BLEND_COLOR_MODE_GRAY8:
val = 12;
break;
#endif
default:
// Unsupported blending tx color mode
abort();
@@ -516,6 +773,142 @@ static inline void ppa_ll_blend_set_tx_color_mode(ppa_dev_t *dev, ppa_blend_colo
dev->blend_color_mode.blend_tx_cm = val;
}
/**
* @brief Set YUV to RGB protocol when PPA blending source image background pixel color space is YUV
*
* @param dev Peripheral instance address
* @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t
*/
static inline void ppa_ll_blend_set_rx_bg_yuv2rgb_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (std) {
case PPA_COLOR_CONV_STD_RGB_YUV_BT601:
dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 0;
break;
case PPA_COLOR_CONV_STD_RGB_YUV_BT709:
dev->blend_color_mode.blend0_rx_yuv2rgb_protocol = 1;
break;
default:
// Unsupported RGB-YUV conversion standard
abort();
}
#else
// YUV not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Set RGB to YUV protocol when PPA blending destination image pixel color space is YUV
*
* @param dev Peripheral instance address
* @param std One of the RGB-YUV conversion standards in ppa_color_conv_std_rgb_yuv_t
*/
static inline void ppa_ll_blend_set_tx_rgb2yuv_std(ppa_dev_t *dev, ppa_color_conv_std_rgb_yuv_t std)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (std) {
case PPA_COLOR_CONV_STD_RGB_YUV_BT601:
dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 0;
break;
case PPA_COLOR_CONV_STD_RGB_YUV_BT709:
dev->blend_color_mode.blend_tx_rgb2yuv_protocol = 1;
break;
default:
// Unsupported RGB-YUV conversion standard
abort();
}
#else
// YUV not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Set PPA blending source image background YUV input range
*
* @param dev Peripheral instance address
* @param range One of color range options in ppa_color_range_t
*/
static inline void ppa_ll_blend_set_rx_bg_yuv_range(ppa_dev_t *dev, ppa_color_range_t range)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (range) {
case PPA_COLOR_RANGE_LIMIT:
dev->blend_color_mode.blend0_rx_yuv_range = 0;
break;
case PPA_COLOR_RANGE_FULL:
dev->blend_color_mode.blend0_rx_yuv_range = 1;
break;
default:
// Unsupported color range
abort();
}
#else
// YUV not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Set PPA blending destination image YUV output range
*
* @param dev Peripheral instance address
* @param range One of color range options in ppa_color_range_t
*/
static inline void ppa_ll_blend_set_tx_yuv_range(ppa_dev_t *dev, ppa_color_range_t range)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (range) {
case PPA_COLOR_RANGE_LIMIT:
dev->blend_color_mode.blend_tx_yuv_range = 0;
break;
case PPA_COLOR_RANGE_FULL:
dev->blend_color_mode.blend_tx_yuv_range = 1;
break;
default:
// Unsupported color range
abort();
}
#else
// YUV not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Set PPA blending source image background YUV422 data format packing order
*
* @param dev Peripheral instance address
* @param pack_order One of the pack order options in color_yuv422_pack_order_t
*/
static inline void ppa_ll_blend_set_rx_bg_yuv422_pack_order(ppa_dev_t *dev, color_yuv422_pack_order_t pack_order)
{
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
switch (pack_order) {
case COLOR_YUV422_PACK_ORDER_YVYU:
dev->blend_color_mode.blend0_rx_yuv422_byte_order = 0;
break;
case COLOR_YUV422_PACK_ORDER_YUYV:
dev->blend_color_mode.blend0_rx_yuv422_byte_order = 1;
break;
case COLOR_YUV422_PACK_ORDER_VYUY:
dev->blend_color_mode.blend0_rx_yuv422_byte_order = 2;
break;
case COLOR_YUV422_PACK_ORDER_UYVY:
dev->blend_color_mode.blend0_rx_yuv422_byte_order = 3;
break;
default:
// Unsupported YUV422 pack order
abort();
}
#else
// YUV422 not supported by PPA blending hardware before P4 ECO5
abort();
#endif
}
/**
* @brief Enable PPA blending input background data wrap in RGB (e.g. ARGB becomes BGRA, RGB becomes BGR)
*
@@ -639,15 +1032,44 @@ static inline void ppa_ll_blend_configure_rx_fg_alpha(ppa_dev_t *dev, ppa_alpha_
/**
* @brief Configure PPA blending pixel filling image block
*
* The color to be filled is directly relying on the blend_tx_fix_pixel register field value.
* For fill operation, the data does not go through any color space conversion in the blending engine.
*
* @param dev Peripheral instance address
* @param data The fix data to be filled to the image block pixels in ARGB8888 format
* @param color_mode One of the values in ppa_fill_color_mode_t
* @param data The point of the fix data to be filled to the image block pixels
* @param hb The horizontal width of image block that would be filled in fix pixel filling mode. The unit is pixel.
* @param vb The vertical height of image block that would be filled in fix pixel filling mode. The unit is pixel.
*/
static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, color_pixel_argb8888_data_t *data, uint32_t hb, uint32_t vb)
static inline void ppa_ll_blend_configure_filling_block(ppa_dev_t *dev, ppa_fill_color_mode_t color_mode, void *data, uint32_t hb, uint32_t vb)
{
HAL_ASSERT(hb <= PPA_BLEND_HB_V && vb <= PPA_BLEND_VB_V);
dev->blend_fix_pixel.blend_tx_fix_pixel = data->val;
uint32_t fill_color_data = 0;
switch (color_mode) {
case PPA_FILL_COLOR_MODE_ARGB8888:
case PPA_FILL_COLOR_MODE_RGB888:
case PPA_FILL_COLOR_MODE_RGB565:
case PPA_FILL_COLOR_MODE_GRAY8:
fill_color_data = *(uint32_t *)data;
break;
case PPA_FILL_COLOR_MODE_YUV422: {
color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data;
fill_color_data = ((yuv_data->y) << 24) | ((yuv_data->v) << 16) | ((yuv_data->y) << 8) | (yuv_data->u);
break;
}
// case PPA_FILL_COLOR_MODE_YUV420: {
// color_macroblock_yuv_data_t *yuv_data = (color_macroblock_yuv_data_t *)data;
// if (yuv_data->u != yuv_data->v) {
// abort();
// }
// fill_color_data = ((yuv_data->y) << 16) | ((yuv_data->y) << 8) | (yuv_data->v);
// break;
// }
default:
// Unsupported filling color mode
abort();
}
dev->blend_fix_pixel.blend_tx_fix_pixel = fill_color_data;
dev->blend_tx_size.blend_hb = hb;
dev->blend_tx_size.blend_vb = vb;
}
components/hal/include/hal/color_types.h
+31 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -179,10 +179,13 @@ typedef union {
/**
* @brief Data structure for RGB888 pixel unit
*/
typedef struct {
uint8_t b; /*!< B component [0, 255] */
uint8_t g; /*!< G component [0, 255] */
uint8_t r; /*!< R component [0, 255] */
typedef union {
struct {
uint8_t b; /*!< B component [0, 255] */
uint8_t g; /*!< G component [0, 255] */
uint8_t r; /*!< R component [0, 255] */
};
uint32_t val; /*!< 32-bit RGB888 value */
} color_pixel_rgb888_data_t;
/**
@@ -197,6 +200,29 @@ typedef union {
uint16_t val; /*!< 16-bit RGB565 value */
} color_pixel_rgb565_data_t;
/**
* @brief Data structure for GRAY8 pixel unit
*/
typedef union {
struct {
uint8_t gray; /*!< Gray component [0, 255] */
};
uint8_t val; /*!< 8-bit GRAY8 value */
} color_pixel_gray8_data_t;
/**
* @brief Data structure for YUV macroblock unit
*
* For YUV420, a macroblock is 2x2 pixels
* For YUV422, a macroblock is 2x1 pixels
* For YUV444, a macro block is a 1x1 pixel
*/
typedef struct {
uint8_t y; /*!< Y component [0, 255] */
uint8_t u; /*!< U component [0, 255] */
uint8_t v; /*!< V component [0, 255] */
} color_macroblock_yuv_data_t;
/*---------------------------------------------------------------
Color Components
---------------------------------------------------------------*/
components/hal/include/hal/dma2d_types.h
+18 -15
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -236,20 +236,23 @@ typedef enum {
typedef enum {
DMA2D_CSC_RX_NONE, /*!< 2D-DMA RX perform no CSC */
DMA2D_CSC_RX_SCRAMBLE, /*!< 2D-DMA RX perform only data scramble */
DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422 to YUV444 conversion */
DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420 to YUV444 conversion */
DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420 to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420 to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB888_601, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422 to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422 to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444 to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444 to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV422_TO_YUV444, /*!< 2D-DMA RX perform YUV422-JPEG to YUV444 conversion */
DMA2D_CSC_RX_YUV422_TO_YUV420, /*!< 2D-DMA RX perform YUV422-JPEG to YUV420 conversion */
DMA2D_CSC_RX_YUV420_TO_YUV444, /*!< 2D-DMA RX perform YUV420-JPEG to YUV444 conversion */
DMA2D_CSC_RX_YUV420_TO_RGB888_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB565_601, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB888_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV420_TO_RGB565_709, /*!< 2D-DMA RX perform YUV420-JPEG to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB888_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB565_601, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB888_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV422_TO_RGB565_709, /*!< 2D-DMA RX perform YUV422-JPEG to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV444_TO_YUV422, /*!< 2D-DMA RX perform YUV444-JPEG to YUV422-MIPI conversion */
DMA2D_CSC_RX_YUV444_TO_YUV420, /*!< 2D-DMA RX perform YUV444-JPEG to YUV420 conversion */
DMA2D_CSC_RX_YUV444_TO_RGB888_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB565_601, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT601 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB888_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB888 conversion (follow BT709 standard) */
DMA2D_CSC_RX_YUV444_TO_RGB565_709, /*!< 2D-DMA RX perform YUV444-JPEG to RGB565 conversion (follow BT709 standard) */
DMA2D_CSC_RX_INVALID, /*!< Invalid 2D-DMA RX color space conversion */
} dma2d_csc_rx_option_t;
components/hal/include/hal/ppa_types.h
+11 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -44,8 +44,8 @@ typedef enum {
// YUV444 not supported by PPA hardware, but we can use 2D-DMA to do conversion before sending into and after coming out from the PPA module
// If in_pic is YUV444, then TX DMA channel could do DMA2D_CSC_TX_YUV444_TO_RGB888_601/709, so PPA in_color_mode is RGB888
// If out_pic is YUV444, then RX DMA channel could do DMA2D_CSC_RX_YUV420_TO_YUV444, so PPA out_color_mode is YUV420
// TODO: P4 ECO2 supports YUV422
// PPA_SRM_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA SRM color mode: YUV422 (input only, limited range only) */
PPA_SRM_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA SRM color mode: YUV422 (input data pack order all supported, but output data format is fixed to YVYU) */
PPA_SRM_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA SRM color mode: GRAY8 */
} ppa_srm_color_mode_t;
/**
@@ -57,9 +57,12 @@ typedef enum {
PPA_BLEND_COLOR_MODE_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< PPA blend color mode: RGB565 */
PPA_BLEND_COLOR_MODE_A8 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A8), /*!< PPA blend color mode: A8, only available on blend foreground input */
PPA_BLEND_COLOR_MODE_A4 = COLOR_TYPE_ID(COLOR_SPACE_ALPHA, COLOR_PIXEL_A4), /*!< PPA blend color mode: A4, only available on blend foreground input */
PPA_BLEND_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA blend color mode: YUV420, only available on blend background input or on output */
PPA_BLEND_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA blend color mode: YUV422, only available on blend background input (all pack order supported) or on output (fixed to YVYU) */
PPA_BLEND_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA blend color mode: GRAY8, only available on blend background input or on output */
// TODO: Support CLUT to support L4/L8 color mode
// PPA_BLEND_COLOR_MODE_L8 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L8), /*!< PPA blend color mode: L8, only available on blend inputs */
// PPA_BLEND_COLOR_MODE_L4 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L4), /*!< PPA blend color mode: L4, only available on blend inputs */
// PPA_BLEND_COLOR_MODE_L8 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L8), /*!< PPA blend color mode: L8, only available on blend input */
// PPA_BLEND_COLOR_MODE_L4 = COLOR_TYPE_ID(COLOR_SPACE_CLUT, COLOR_PIXEL_L4), /*!< PPA blend color mode: L4, only available on blend input */
} ppa_blend_color_mode_t;
/**
@@ -69,6 +72,9 @@ typedef enum {
PPA_FILL_COLOR_MODE_ARGB8888 = COLOR_TYPE_ID(COLOR_SPACE_ARGB, COLOR_PIXEL_ARGB8888), /*!< PPA fill color mode: ARGB8888 */
PPA_FILL_COLOR_MODE_RGB888 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB888), /*!< PPA fill color mode: RGB888 */
PPA_FILL_COLOR_MODE_RGB565 = COLOR_TYPE_ID(COLOR_SPACE_RGB, COLOR_PIXEL_RGB565), /*!< PPA fill color mode: RGB565 */
// PPA_FILL_COLOR_MODE_YUV420 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV420), /*!< PPA fill color mode: YUV420 */ // Non-typical YUV420, U and V components have to be the same value
PPA_FILL_COLOR_MODE_YUV422 = COLOR_TYPE_ID(COLOR_SPACE_YUV, COLOR_PIXEL_YUV422), /*!< PPA fill color mode: YUV422 (w/ YVYU pack order) */
PPA_FILL_COLOR_MODE_GRAY8 = COLOR_TYPE_ID(COLOR_SPACE_GRAY, COLOR_PIXEL_GRAY8), /*!< PPA fill color mode: GRAY8 */
} ppa_fill_color_mode_t;
/**
components/soc/esp32p4/dma2d_periph.c
+2
View File
@@ -14,10 +14,12 @@ const dma2d_signal_conn_t dma2d_periph_signals = {
[0] = ETS_DMA2D_OUT_CH0_INTR_SOURCE,
[1] = ETS_DMA2D_OUT_CH1_INTR_SOURCE,
[2] = ETS_DMA2D_OUT_CH2_INTR_SOURCE,
[3] = ETS_DMA2D_OUT_CH3_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0
},
.rx_irq_id = {
[0] = ETS_DMA2D_IN_CH0_INTR_SOURCE,
[1] = ETS_DMA2D_IN_CH1_INTR_SOURCE,
[2] = ETS_DMA2D_IN_CH2_INTR_SOURCE, // This channel only exists on P4 ver. >= 3.0
}
}
}
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+2 -2
View File
@@ -629,11 +629,11 @@ config SOC_DMA2D_GROUPS
config SOC_DMA2D_TX_CHANNELS_PER_GROUP
int
default 3
default 4
config SOC_DMA2D_RX_CHANNELS_PER_GROUP
int
default 2
default 3
config SOC_ETM_GROUPS
int
components/soc/esp32p4/include/soc/interrupts.h
+9 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -152,7 +152,14 @@ typedef enum {
ETS_H264_REG_INTR_SOURCE,
ETS_ASSIST_DEBUG_INTR_SOURCE,
ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */
// The following sources' int_map_reg addr are not continuous with previous ones (check interrupt_core0/1_struct.h),
// but esp_rom_route_intr_matrix and interrupt_clic_ll_route assume all int_map_reg addr are continuous.
// Therefore, the workaround is to give the three new interrupt sources ID numbers that match with the corresponding correct addresses.
ETS_DMA2D_IN_CH2_INTR_SOURCE = 133, /**< This interrupt source only exists on chip ver. >= 3.0 */
ETS_DMA2D_OUT_CH3_INTR_SOURCE, /**< This interrupt source only exists on chip ver. >= 3.0 */
ETS_AXI_PERF_MON_INTR_SOURCE, /**< This interrupt source only exists on chip ver. >= 3.0 */
ETS_MAX_INTR_SOURCE, /**< number of interrupt sources (this value is larger than the real number of sources on ver. less than 3.0, but it should be fine)*/
} periph_interrupt_t;
typedef periph_interrupt_t periph_interrput_t __attribute__((deprecated("in favor of periph_interrupt_t")));
components/soc/esp32p4/include/soc/soc_caps.h
+2 -2
View File
@@ -225,8 +225,8 @@
/*-------------------------- 2D-DMA CAPS -------------------------------------*/
#define SOC_DMA2D_GROUPS (1U) // Number of 2D-DMA groups
#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA TX (OUT) channels in each group
#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (2) // Number of 2D-DMA RX (IN) channels in each group
#define SOC_DMA2D_TX_CHANNELS_PER_GROUP (4) // Number of 2D-DMA TX (OUT) channels in each group (4th channel only exists on P4 ver. >= 3.0)
#define SOC_DMA2D_RX_CHANNELS_PER_GROUP (3) // Number of 2D-DMA RX (IN) channels in each group (3rd channel only exists on P4 ver. >= 3.0)
// #define SOC_DMA2D_SUPPORT_ETM (1) // Support ETM submodule
/*-------------------------- ETM CAPS --------------------------------------*/
components/soc/esp32p4/interrupts.c
+3
View File
@@ -135,4 +135,7 @@ const char *const esp_isr_names[] = {
[ETS_H264_DMA2D_IN_CH5_INTR_SOURCE] = "H264_DMA2D_IN_CH5",
[ETS_H264_REG_INTR_SOURCE] = "H264_REG",
[ETS_ASSIST_DEBUG_INTR_SOURCE] = "ASSIST_DEBUG",
[ETS_DMA2D_IN_CH2_INTR_SOURCE] = "DMA2D_IN_CH2", /* This interrupt source only exists on chip ver. >= 3.0 */
[ETS_DMA2D_OUT_CH3_INTR_SOURCE] = "DMA2D_OUT_CH3", /* This interrupt source only exists on chip ver. >= 3.0 */
[ETS_AXI_PERF_MON_INTR_SOURCE] = "AXI_PERF_MON", /* This interrupt source only exists on chip ver. >= 3.0 */
};
components/soc/esp32p4/ld/esp32p4.peripherals.ld
+1 -1
View File
@@ -26,7 +26,7 @@ PROVIDE ( LP2HP_PERI_PMS = 0x500A5800 );
PROVIDE ( DMA_PMS = 0x500A6000 );
PROVIDE ( AXI_PERF_MON = 0x500A8000 );
PROVIDE ( LEDC = 0x500D3000 );
PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 );
PROVIDE ( LEDC_GAMMA_RAM = 0x500D3400 );
PROVIDE ( TIMERG0 = 0x500C2000 );
PROVIDE ( TIMERG1 = 0x500C3000 );
PROVIDE ( SYSTIMER = 0x500E2000 );
components/soc/esp32p4/register/hw_ver1/soc/dma2d_struct.h
+12 -33
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -1763,42 +1763,21 @@ typedef struct {
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
volatile dma2d_in_arb_chn_reg_t in_arb;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf;
volatile dma2d_in_color_convert_chn_reg_t in_color_convert;
volatile dma2d_in_scramble_chn_reg_t in_scramble;
volatile dma2d_color_param_group_chn_reg_t in_color_param_group;
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
uint32_t reserved_570[36];
} dma2d_in_ch0_reg_t;
typedef struct {
volatile dma2d_in_conf0_chn_reg_t in_conf0;
volatile dma2d_in_int_raw_chn_reg_t in_int_raw;
volatile dma2d_in_int_ena_chn_reg_t in_int_ena;
volatile dma2d_in_int_st_chn_reg_t in_int_st;
volatile dma2d_in_int_clr_chn_reg_t in_int_clr;
volatile dma2d_infifo_status_chn_reg_t infifo_status;
volatile dma2d_in_pop_chn_reg_t in_pop;
volatile dma2d_in_link_conf_chn_reg_t in_link_conf;
volatile dma2d_in_link_addr_chn_reg_t in_link_addr;
volatile dma2d_in_state_chn_reg_t in_state;
volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
volatile dma2d_in_dscr_chn_reg_t in_dscr;
volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0;
volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1;
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
volatile dma2d_in_arb_chn_reg_t in_arb;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
uint32_t reserved_64c[45];
} dma2d_in_ch1_reg_t;
union {
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */
volatile dma2d_in_etm_conf_chn_reg_t in1_etm_conf; /* specific for channel1 */
};
volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */
volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */
volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf; /* On ver. less than 3.0, channel 1 in_etm_conf register is at the in_ro_pd_conf addr. Here is to only be compatible with new ECOs. Workaround should be done in LL layer. */
uint32_t reserved_in[36];
} dma2d_in_chn_reg_t;
typedef struct dma2d_dev_t {
volatile dma2d_out_chn_reg_t out_channel[3];
uint32_t reserved_300[128];
volatile dma2d_in_ch0_reg_t in_channel0;
volatile dma2d_in_ch1_reg_t in_channel1;
volatile dma2d_in_chn_reg_t in_channel[2];
uint32_t reserved_700[192];
volatile dma2d_axi_err_reg_t axi_err;
volatile dma2d_rst_conf_reg_t rst_conf;
components/soc/esp32p4/register/hw_ver1/soc/ledc_struct.h
+8 -8
View File
@@ -106,10 +106,10 @@ typedef union {
*/
typedef union {
struct {
/** duty_ch0_r : RO; bitpos: [24:0]; default: 0;
/** duty_r : RO; bitpos: [24:0]; default: 0;
* Represents the current duty of output signal on channel n.
*/
uint32_t duty:25;
uint32_t duty_r:25;
uint32_t reserved_25:7;
};
uint32_t val;
@@ -577,20 +577,20 @@ typedef union {
*/
typedef union {
struct {
/** ch0_gamma_entry_num : R/W; bitpos: [4:0]; default: 0;
/** gamma_entry_num : R/W; bitpos: [4:0]; default: 0;
* Configures the number of duty cycle fading rages for LEDC chn.
*/
uint32_t ch0_gamma_entry_num:5;
/** ch0_gamma_pause : WT; bitpos: [5]; default: 0;
uint32_t gamma_entry_num:5;
/** gamma_pause : WT; bitpos: [5]; default: 0;
* Configures whether or not to pause duty cycle fading of LEDC chn.\\0: Invalid. No
* effect\\1: Pause
*/
uint32_t ch0_gamma_pause:1;
/** ch0_gamma_resume : WT; bitpos: [6]; default: 0;
uint32_t gamma_pause:1;
/** gamma_resume : WT; bitpos: [6]; default: 0;
* Configures whether or nor to resume duty cycle fading of LEDC chn.\\0: Invalid. No
* effect\\1: Resume
*/
uint32_t ch0_gamma_resume:1;
uint32_t gamma_resume:1;
uint32_t reserved_7:25;
};
uint32_t val;
components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_reg.h
-7537
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32p4/register/hw_ver3/soc/dma2d_eco5_struct.h
-2085
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32p4/register/hw_ver3/soc/dma2d_reg.h
+2024 -104
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32p4/register/hw_ver3/soc/dma2d_struct.h
+83 -113
View File
@@ -10,11 +10,8 @@
extern "C" {
#endif
//TODO: IDF-13427
/** Group: out */
/** Type of out_conf0_chn register
* Configures the tx direction of channel 0
* Configures the tx direction of channel n
*/
typedef union {
struct {
@@ -48,7 +45,7 @@ typedef union {
*/
uint32_t out_loop_test_chn:1;
/** out_mem_burst_length_chn : R/W; bitpos: [8:6]; default: 0;
* Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64
* Block size of Tx channel 0. 0: 8 bytes 1: 16 bytes 2: 32 bytes 3: 64
* bytes 4: 128 bytes
*/
uint32_t out_mem_burst_length_chn:3;
@@ -92,7 +89,7 @@ typedef union {
} dma2d_out_conf0_chn_reg_t;
/** Type of out_int_raw_chn register
* Raw interrupt status of TX channel 0
* Raw interrupt status of TX channel n
*/
typedef union {
struct {
@@ -160,7 +157,7 @@ typedef union {
} dma2d_out_int_raw_chn_reg_t;
/** Type of out_int_ena_chn register
* Interrupt enable bits of TX channel 0
* Interrupt enable bits of TX channel n
*/
typedef union {
struct {
@@ -222,7 +219,7 @@ typedef union {
} dma2d_out_int_ena_chn_reg_t;
/** Type of out_int_st_chn register
* Masked interrupt status of TX channel 0
* Masked interrupt status of TX channel n
*/
typedef union {
struct {
@@ -284,7 +281,7 @@ typedef union {
} dma2d_out_int_st_chn_reg_t;
/** Type of out_int_clr_chn register
* Interrupt clear bits of TX channel 0
* Interrupt clear bits of TX channel n
*/
typedef union {
struct {
@@ -346,20 +343,20 @@ typedef union {
} dma2d_out_int_clr_chn_reg_t;
/** Type of outfifo_status_chn register
* Represents the status of the tx fifo of channel 0
* Represents the status of the tx fifo of channel n
*/
typedef union {
struct {
/** outfifo_full_l2_chn : RO; bitpos: [0]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Tx FIFO full signal for Tx channel n.
*/
uint32_t outfifo_full_l2_chn:1;
/** outfifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Tx FIFO empty signal for Tx channel n.
*/
uint32_t outfifo_empty_l2_chn:1;
/** outfifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Tx FIFO for Tx channel n.
*/
uint32_t outfifo_cnt_l2_chn:4;
uint32_t reserved_6:1;
@@ -396,27 +393,27 @@ typedef union {
*/
uint32_t out_remain_under_8b_chn:1;
/** outfifo_full_l1_chn : RO; bitpos: [15]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Tx FIFO full signal for Tx channel n.
*/
uint32_t outfifo_full_l1_chn:1;
/** outfifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Tx FIFO empty signal for Tx channel n.
*/
uint32_t outfifo_empty_l1_chn:1;
/** outfifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Tx FIFO for Tx channel n.
*/
uint32_t outfifo_cnt_l1_chn:5;
/** outfifo_full_l3_chn : RO; bitpos: [22]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Tx FIFO full signal for Tx channel n.
*/
uint32_t outfifo_full_l3_chn:1;
/** outfifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Tx FIFO empty signal for Tx channel n.
*/
uint32_t outfifo_empty_l3_chn:1;
/** outfifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Tx FIFO for Tx channel n.
*/
uint32_t outfifo_cnt_l3_chn:5;
uint32_t reserved_29:3;
@@ -425,7 +422,7 @@ typedef union {
} dma2d_outfifo_status_chn_reg_t;
/** Type of out_push_chn register
* Configures the tx fifo of channel 0
* Configures the tx fifo of channel n
*/
typedef union {
struct {
@@ -443,7 +440,7 @@ typedef union {
} dma2d_out_push_chn_reg_t;
/** Type of out_link_conf_chn register
* Configures the tx descriptor operations of channel 0
* Configures the tx descriptor operations of channel n
*/
typedef union {
struct {
@@ -471,7 +468,7 @@ typedef union {
} dma2d_out_link_conf_chn_reg_t;
/** Type of out_link_addr_chn register
* Configures the tx descriptor address of channel 0
* Configures the tx descriptor address of channel n
*/
typedef union {
struct {
@@ -484,7 +481,7 @@ typedef union {
} dma2d_out_link_addr_chn_reg_t;
/** Type of out_state_chn register
* Represents the working status of the tx descriptor of channel 0
* Represents the working status of the tx descriptor of channel n
*/
typedef union {
struct {
@@ -510,7 +507,7 @@ typedef union {
} dma2d_out_state_chn_reg_t;
/** Type of out_eof_des_addr_chn register
* Represents the address associated with the outlink descriptor of channel 0
* Represents the address associated with the outlink descriptor of channel n
*/
typedef union {
struct {
@@ -524,7 +521,7 @@ typedef union {
} dma2d_out_eof_des_addr_chn_reg_t;
/** Type of out_dscr_chn register
* Represents the address associated with the outlink descriptor of channel 0
* Represents the address associated with the outlink descriptor of channel n
*/
typedef union {
struct {
@@ -537,7 +534,7 @@ typedef union {
} dma2d_out_dscr_chn_reg_t;
/** Type of out_dscr_bf0_chn register
* Represents the address associated with the outlink descriptor of channel 0
* Represents the address associated with the outlink descriptor of channel n
*/
typedef union {
struct {
@@ -550,7 +547,7 @@ typedef union {
} dma2d_out_dscr_bf0_chn_reg_t;
/** Type of out_dscr_bf1_chn register
* Represents the address associated with the outlink descriptor of channel 0
* Represents the address associated with the outlink descriptor of channel n
*/
typedef union {
struct {
@@ -563,7 +560,7 @@ typedef union {
} dma2d_out_dscr_bf1_chn_reg_t;
/** Type of out_peri_sel_chn register
* Configures the tx peripheral of channel 0
* Configures the tx peripheral of channel n
*/
typedef union {
struct {
@@ -578,7 +575,7 @@ typedef union {
} dma2d_out_peri_sel_chn_reg_t;
/** Type of out_arb_chn register
* Configures the tx arbiter of channel 0
* Configures the tx arbiter of channel n
*/
typedef union {
struct {
@@ -586,17 +583,17 @@ typedef union {
* Set the max number of token count of arbiter
*/
uint32_t out_arb_token_num_chn:4;
/** out_arb_priority_chn : R/W; bitpos: [5:4]; default: 1;
/** out_arb_priority_chn : R/W; bitpos: [7:4]; default: 1;
* Set the priority of channel
*/
uint32_t out_arb_priority_chn:2;
uint32_t reserved_6:26;
uint32_t out_arb_priority_chn:4;
uint32_t reserved_8:24;
};
uint32_t val;
} dma2d_out_arb_chn_reg_t;
/** Type of out_ro_status_chn register
* Represents the status of the tx reorder module of channel 0
* Represents the status of the tx reorder module of channel n
*/
typedef union {
struct {
@@ -628,7 +625,7 @@ typedef union {
} dma2d_out_ro_status_chn_reg_t;
/** Type of out_ro_pd_conf_chn register
* Configures the tx reorder memory of channel 0
* Configures the tx reorder memory of channel n
*/
typedef union {
struct {
@@ -652,7 +649,7 @@ typedef union {
} dma2d_out_ro_pd_conf_chn_reg_t;
/** Type of out_color_convert_chn register
* Configures the tx color convert of channel 0
* Configures the tx color convert of channel n
*/
typedef union {
struct {
@@ -678,7 +675,7 @@ typedef union {
} dma2d_out_color_convert_chn_reg_t;
/** Type of out_scramble_chn register
* Configures the tx scramble of channel 0
* Configures the tx scramble of channel n
*/
typedef union {
struct {
@@ -693,7 +690,7 @@ typedef union {
} dma2d_out_scramble_chn_reg_t;
/** Type of out_etm_conf_chn register
* Configures the tx etm of channel 0
* Configures the tx etm of channel n
*/
typedef union {
struct {
@@ -732,10 +729,8 @@ typedef union {
uint32_t val;
} dma2d_out_dscr_port_blk_chn_reg_t;
/** Group: in */
/** Type of in_conf0_chn register
* Configures the rx direction of channel 0
* Configures the rx direction of channel n
*/
typedef union {
struct {
@@ -808,7 +803,7 @@ typedef union {
} dma2d_in_conf0_chn_reg_t;
/** Type of in_int_raw_chn register
* Raw interrupt status of RX channel 0
* Raw interrupt status of RX channel n
*/
typedef union {
struct {
@@ -880,7 +875,7 @@ typedef union {
} dma2d_in_int_raw_chn_reg_t;
/** Type of in_int_ena_chn register
* Interrupt enable bits of RX channel 0
* Interrupt enable bits of RX channel n
*/
typedef union {
struct {
@@ -946,7 +941,7 @@ typedef union {
} dma2d_in_int_ena_chn_reg_t;
/** Type of in_int_st_chn register
* Masked interrupt status of RX channel 0
* Masked interrupt status of RX channel n
*/
typedef union {
struct {
@@ -1012,7 +1007,7 @@ typedef union {
} dma2d_in_int_st_chn_reg_t;
/** Type of in_int_clr_chn register
* Interrupt clear bits of RX channel 0
* Interrupt clear bits of RX channel n
*/
typedef union {
struct {
@@ -1078,20 +1073,20 @@ typedef union {
} dma2d_in_int_clr_chn_reg_t;
/** Type of infifo_status_chn register
* Represents the status of the rx fifo of channel 0
* Represents the status of the rx fifo of channel n
*/
typedef union {
struct {
/** infifo_full_l2_chn : RO; bitpos: [0]; default: 0;
* Rx FIFO full signal for Rx channel.
* Rx FIFO full signal for Rx channel n.
*/
uint32_t infifo_full_l2_chn:1;
/** infifo_empty_l2_chn : RO; bitpos: [1]; default: 1;
* Rx FIFO empty signal for Rx channel.
* Rx FIFO empty signal for Rx channel n.
*/
uint32_t infifo_empty_l2_chn:1;
/** infifo_cnt_l2_chn : RO; bitpos: [5:2]; default: 0;
* The register stores the byte number of the data in Rx FIFO for Rx channel.
* The register stores the byte number of the data in Rx FIFO for Rx channel n.
*/
uint32_t infifo_cnt_l2_chn:4;
uint32_t reserved_6:1;
@@ -1128,27 +1123,27 @@ typedef union {
*/
uint32_t in_remain_under_8b_chn:1;
/** infifo_full_l1_chn : RO; bitpos: [15]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Rx FIFO full signal for Tx channel n.
*/
uint32_t infifo_full_l1_chn:1;
/** infifo_empty_l1_chn : RO; bitpos: [16]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Rx FIFO empty signal for Tx channel n.
*/
uint32_t infifo_empty_l1_chn:1;
/** infifo_cnt_l1_chn : RO; bitpos: [21:17]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Rx FIFO for Rx channel n.
*/
uint32_t infifo_cnt_l1_chn:5;
/** infifo_full_l3_chn : RO; bitpos: [22]; default: 0;
* Tx FIFO full signal for Tx channel 0.
* Rx FIFO full signal for Rx channel n.
*/
uint32_t infifo_full_l3_chn:1;
/** infifo_empty_l3_chn : RO; bitpos: [23]; default: 1;
* Tx FIFO empty signal for Tx channel 0.
* Rx FIFO empty signal for Rx channel n.
*/
uint32_t infifo_empty_l3_chn:1;
/** infifo_cnt_l3_chn : RO; bitpos: [28:24]; default: 0;
* The register stores the byte number of the data in Tx FIFO for Tx channel 0.
* The register stores the byte number of the data in Rx FIFO for Rx channel n.
*/
uint32_t infifo_cnt_l3_chn:5;
uint32_t reserved_29:3;
@@ -1157,7 +1152,7 @@ typedef union {
} dma2d_infifo_status_chn_reg_t;
/** Type of in_pop_chn register
* Configures the rx fifo of channel 0
* Configures the rx fifo of channel n
*/
typedef union {
struct {
@@ -1175,7 +1170,7 @@ typedef union {
} dma2d_in_pop_chn_reg_t;
/** Type of in_link_conf_chn register
* Configures the rx descriptor operations of channel 0
* Configures the rx descriptor operations of channel n
*/
typedef union {
struct {
@@ -1208,7 +1203,7 @@ typedef union {
} dma2d_in_link_conf_chn_reg_t;
/** Type of in_link_addr_chn register
* Configures the rx descriptor address of channel 0
* Configures the rx descriptor address of channel n
*/
typedef union {
struct {
@@ -1221,7 +1216,7 @@ typedef union {
} dma2d_in_link_addr_chn_reg_t;
/** Type of in_state_chn register
* Represents the working status of the rx descriptor of channel 0
* Represents the working status of the rx descriptor of channel n
*/
typedef union {
struct {
@@ -1247,7 +1242,7 @@ typedef union {
} dma2d_in_state_chn_reg_t;
/** Type of in_suc_eof_des_addr_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1261,7 +1256,7 @@ typedef union {
} dma2d_in_suc_eof_des_addr_chn_reg_t;
/** Type of in_err_eof_des_addr_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1275,7 +1270,7 @@ typedef union {
} dma2d_in_err_eof_des_addr_chn_reg_t;
/** Type of in_dscr_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1288,7 +1283,7 @@ typedef union {
} dma2d_in_dscr_chn_reg_t;
/** Type of in_dscr_bf0_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1301,7 +1296,7 @@ typedef union {
} dma2d_in_dscr_bf0_chn_reg_t;
/** Type of in_dscr_bf1_chn register
* Represents the address associated with the inlink descriptor of channel 0
* Represents the address associated with the inlink descriptor of channel n
*/
typedef union {
struct {
@@ -1314,7 +1309,7 @@ typedef union {
} dma2d_in_dscr_bf1_chn_reg_t;
/** Type of in_peri_sel_chn register
* Configures the rx peripheral of channel 0
* Configures the rx peripheral of channel n
*/
typedef union {
struct {
@@ -1329,7 +1324,7 @@ typedef union {
} dma2d_in_peri_sel_chn_reg_t;
/** Type of in_arb_chn register
* Configures the rx arbiter of channel 0
* Configures the rx arbiter of channel n
*/
typedef union {
struct {
@@ -1337,17 +1332,17 @@ typedef union {
* Set the max number of token count of arbiter
*/
uint32_t in_arb_token_num_chn:4;
/** in_arb_priority_chn : R/W; bitpos: [4]; default: 1;
/** in_arb_priority_chn : R/W; bitpos: [7:4]; default: 1;
* Set the priority of channel
*/
uint32_t in_arb_priority_chn:1;
uint32_t reserved_5:27;
uint32_t in_arb_priority_chn:4;
uint32_t reserved_8:24;
};
uint32_t val;
} dma2d_in_arb_chn_reg_t;
/** Type of in_ro_status_chn register
* Represents the status of the rx reorder module of channel 0
* Represents the status of the rx reorder module of channel n
*/
typedef union {
struct {
@@ -1379,7 +1374,7 @@ typedef union {
} dma2d_in_ro_status_chn_reg_t;
/** Type of in_ro_pd_conf_chn register
* Configures the rx reorder memory of channel 0
* Configures the rx reorder memory of channel n
*/
typedef union {
struct {
@@ -1403,13 +1398,13 @@ typedef union {
} dma2d_in_ro_pd_conf_chn_reg_t;
/** Type of in_color_convert_chn register
* Configures the tx color convert of channel 0
* Configures the Rx color convert of channel n
*/
typedef union {
struct {
/** in_color_output_sel_chn : R/W; bitpos: [1:0]; default: 0;
* Set final color convert process and output type 0: RGB888 to RGB565 1:
* output directly
* output directly 2: YUV444 to YUV422 3: YUV444 to YUV420
*/
uint32_t in_color_output_sel_chn:2;
/** in_color_3b_proc_en_chn : R/W; bitpos: [2]; default: 0;
@@ -1428,7 +1423,7 @@ typedef union {
} dma2d_in_color_convert_chn_reg_t;
/** Type of in_scramble_chn register
* Configures the rx scramble of channel 0
* Configures the rx scramble of channel n
*/
typedef union {
struct {
@@ -1448,7 +1443,7 @@ typedef union {
} dma2d_in_scramble_chn_reg_t;
/** Type of in_etm_conf_chn register
* Configures the rx etm of channel 0
* Configures the rx etm of channel n
*/
typedef union {
struct {
@@ -1469,8 +1464,6 @@ typedef union {
uint32_t val;
} dma2d_in_etm_conf_chn_reg_t;
/** Group: Status Registers */
/** Type of axi_err register
* Represents the status of th axi bus
*/
@@ -1514,7 +1507,7 @@ typedef union {
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 36716816;
/** date : R/W; bitpos: [31:0]; default: 37822864;
* register version.
*/
uint32_t date:32;
@@ -1522,8 +1515,6 @@ typedef union {
uint32_t val;
} dma2d_date_reg_t;
/** Group: Configuration Registers */
/** Type of rst_conf register
* Configures the reset of axi
*/
@@ -1681,7 +1672,6 @@ typedef union {
uint32_t val;
} dma2d_rdn_eco_low_reg_t;
/** Type of in/out_color_param_h/m/l_chn register
* Configures the rx/tx color convert parameter of channel n
*/
@@ -1713,12 +1703,14 @@ typedef union {
uint32_t val[2];
} dma2d_color_param_reg_t;
typedef struct {
volatile dma2d_color_param_reg_t param_h;
volatile dma2d_color_param_reg_t param_m;
volatile dma2d_color_param_reg_t param_l;
} dma2d_color_param_group_chn_reg_t;
typedef struct {
volatile dma2d_out_conf0_chn_reg_t out_conf0;
volatile dma2d_out_int_raw_chn_reg_t out_int_raw;
@@ -1746,32 +1738,6 @@ typedef struct {
uint32_t reserved_out[36];
} dma2d_out_chn_reg_t;
typedef struct {
volatile dma2d_in_conf0_chn_reg_t in_conf0;
volatile dma2d_in_int_raw_chn_reg_t in_int_raw;
volatile dma2d_in_int_ena_chn_reg_t in_int_ena;
volatile dma2d_in_int_st_chn_reg_t in_int_st;
volatile dma2d_in_int_clr_chn_reg_t in_int_clr;
volatile dma2d_infifo_status_chn_reg_t infifo_status;
volatile dma2d_in_pop_chn_reg_t in_pop;
volatile dma2d_in_link_conf_chn_reg_t in_link_conf;
volatile dma2d_in_link_addr_chn_reg_t in_link_addr;
volatile dma2d_in_state_chn_reg_t in_state;
volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
volatile dma2d_in_dscr_chn_reg_t in_dscr;
volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0;
volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1;
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
volatile dma2d_in_arb_chn_reg_t in_arb;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf;
volatile dma2d_in_color_convert_chn_reg_t in_color_convert;
volatile dma2d_in_scramble_chn_reg_t in_scramble;
volatile dma2d_color_param_group_chn_reg_t in_color_param_group;
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
uint32_t reserved_570[36];
} dma2d_in_ch0_reg_t;
typedef struct {
volatile dma2d_in_conf0_chn_reg_t in_conf0;
@@ -1792,16 +1758,20 @@ typedef struct {
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
volatile dma2d_in_arb_chn_reg_t in_arb;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */
volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */
volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */
volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
uint32_t reserved_64c[45];
} dma2d_in_ch1_reg_t;
uint32_t reserved_in[36];
} dma2d_in_chn_reg_t;
typedef struct dma2d_dev_t {
volatile dma2d_out_chn_reg_t out_channel[3];
uint32_t reserved_300[128];
volatile dma2d_in_ch0_reg_t in_channel0;
volatile dma2d_in_ch1_reg_t in_channel1;
uint32_t reserved_700[192];
volatile dma2d_out_chn_reg_t out_channel[4];
uint32_t reserved_400[64];
volatile dma2d_in_chn_reg_t in_channel[3];
uint32_t reserved_800[128];
volatile dma2d_axi_err_reg_t axi_err;
volatile dma2d_rst_conf_reg_t rst_conf;
volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr;
components/soc/esp32p4/register/hw_ver3/soc/interrupts.h
-157
View File
@@ -1,157 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdint.h>
#ifdef __cplusplus
extern "C"
{
#endif
//Interrupt hardware source table
//This table is decided by hardware, don't touch this.
typedef enum {
ETS_LP_RTC_INT_SOURCE,
ETS_LP_WDT_INT_SOURCE,
ETS_LP_TIMER_REG_0_INT_SOURCE,
ETS_LP_TIMER_REG_1_INT_SOURCE,
ETS_MB_HP_INT_SOURCE,
ETS_MB_LP_INT_SOURCE,
ETS_PMU_REG_0_INT_SOURCE,
ETS_PMU_REG_1_INT_SOURCE,
ETS_LP_ANAPERI_INT_SOURCE,
ETS_LP_ADC_INT_SOURCE,
ETS_LP_GPIO_INT_SOURCE,
ETS_LP_I2C_INT_SOURCE,
ETS_LP_I2S_INT_SOURCE,
ETS_LP_SPI_INT_SOURCE,
ETS_LP_TOUCH_INT_SOURCE,
ETS_LP_TSENS_INT_SOURCE,
ETS_LP_UART_INT_SOURCE,
ETS_LP_EFUSE_INT_SOURCE,
ETS_LP_SW_INT_SOURCE,
ETS_LP_SYSREG_INT_SOURCE,
ETS_LP_HUK_INT_SOURCE,
ETS_SYS_ICM_INT_SOURCE,
ETS_USB_DEVICE_INT_SOURCE,
ETS_SDIO_HOST_INT_SOURCE,
ETS_GDMA_INT_SOURCE,
ETS_SPI2_INT_SOURCE,
ETS_SPI3_INT_SOURCE,
ETS_I2S0_INT_SOURCE,
ETS_I2S1_INT_SOURCE,
ETS_I2S2_INT_SOURCE,
ETS_UHCI0_INT_SOURCE,
ETS_UART0_INT_SOURCE,
ETS_UART1_INT_SOURCE,
ETS_UART2_INT_SOURCE,
ETS_UART3_INT_SOURCE,
ETS_UART4_INT_SOURCE,
ETS_LCD_CAM_INT_SOURCE,
ETS_ADC_INT_SOURCE,
ETS_PWM0_INT_SOURCE,
ETS_PWM1_INT_SOURCE,
ETS_TWAI0_INT_SOURCE,
ETS_TWAI1_INT_SOURCE,
ETS_TWAI2_INT_SOURCE,
ETS_RMT_INT_SOURCE,
ETS_I2C0_INT_SOURCE,
ETS_I2C1_INT_SOURCE,
ETS_TIMERGRP0_T0_INT_SOURCE,
ETS_TIMERGRP0_T1_INT_SOURCE,
ETS_TIMERGRP0_WDT_INT_SOURCE,
ETS_TIMERGRP1_T0_INT_SOURCE,
ETS_TIMERGRP1_T1_INT_SOURCE,
ETS_TIMERGRP1_WDT_INT_SOURCE,
ETS_LEDC_INT_SOURCE,
ETS_SYSTIMER_TARGET0_INT_SOURCE,
ETS_SYSTIMER_TARGET1_INT_SOURCE,
ETS_SYSTIMER_TARGET2_INT_SOURCE,
ETS_AHB_PDMA_IN_CH0_INT_SOURCE,
ETS_AHB_PDMA_IN_CH1_INT_SOURCE,
ETS_AHB_PDMA_IN_CH2_INT_SOURCE,
ETS_AHB_PDMA_OUT_CH0_INT_SOURCE,
ETS_AHB_PDMA_OUT_CH1_INT_SOURCE,
ETS_AHB_PDMA_OUT_CH2_INT_SOURCE,
ETS_AXI_PDMA_IN_CH0_INT_SOURCE,
ETS_AXI_PDMA_IN_CH1_INT_SOURCE,
ETS_AXI_PDMA_IN_CH2_INT_SOURCE,
ETS_AXI_PDMA_OUT_CH0_INT_SOURCE,
ETS_AXI_PDMA_OUT_CH1_INT_SOURCE,
ETS_AXI_PDMA_OUT_CH2_INT_SOURCE,
ETS_RSA_INT_SOURCE,
ETS_AES_INT_SOURCE,
ETS_SHA_INT_SOURCE,
ETS_ECC_INT_SOURCE,
ETS_ECDSA_INT_SOURCE,
ETS_KM_INT_SOURCE,
ETS_GPIO_INT0_SOURCE,
ETS_GPIO_INT1_SOURCE,
ETS_GPIO_INT2_SOURCE,
ETS_GPIO_INT3_SOURCE,
ETS_GPIO_PAD_COMP_INT_SOURCE,
ETS_CPU_INT_FROM_CPU_0_SOURCE,
ETS_CPU_INT_FROM_CPU_1_SOURCE,
ETS_CPU_INT_FROM_CPU_2_SOURCE,
ETS_CPU_INT_FROM_CPU_3_SOURCE,
ETS_CACHE_INT_SOURCE,
ETS_FLASH_MSPI_INT_SOURCE,
ETS_CSI_BRIDGE_INT_SOURCE,
ETS_DSI_BRIDGE_INT_SOURCE,
ETS_CSI_INT_SOURCE,
ETS_DSI_INT_SOURCE,
ETS_GMII_PHY_INT_SOURCE,
ETS_LPI_INT_SOURCE,
ETS_PMT_INT_SOURCE,
ETS_SBD_INT_SOURCE,
ETS_USB_OTG_INT_SOURCE,
ETS_USB_OTG_ENDP_MULTI_PROC_INT_SOURCE,
ETS_JPEG_INT_SOURCE,
ETS_PPA_INT_SOURCE,
ETS_CORE0_TRACE_INT_SOURCE,
ETS_CORE1_TRACE_INT_SOURCE,
ETS_HP_CORE_CTRL_INT_SOURCE,
ETS_ISP_INT_SOURCE,
ETS_I3C_MST_INT_SOURCE,
ETS_I3C_SLV_INT_SOURCE,
ETS_USB_OTG11_INT_SOURCE,
ETS_DMA2D_IN_CH0_INT_SOURCE,
ETS_DMA2D_IN_CH1_INT_SOURCE,
ETS_DMA2D_OUT_CH0_INT_SOURCE,
ETS_DMA2D_OUT_CH1_INT_SOURCE,
ETS_DMA2D_OUT_CH2_INT_SOURCE,
ETS_PSRAM_MSPI_INT_SOURCE,
ETS_HP_SYSREG_INT_SOURCE,
ETS_PCNT_INT_SOURCE,
ETS_HP_PAU_INT_SOURCE,
ETS_HP_PARLIO_RX_INT_SOURCE,
ETS_HP_PARLIO_TX_INT_SOURCE,
ETS_H264_DMA2D_OUT_CH0_INT_SOURCE,
ETS_H264_DMA2D_OUT_CH1_INT_SOURCE,
ETS_H264_DMA2D_OUT_CH2_INT_SOURCE,
ETS_H264_DMA2D_OUT_CH3_INT_SOURCE,
ETS_H264_DMA2D_OUT_CH4_INT_SOURCE,
ETS_H264_DMA2D_IN_CH0_INT_SOURCE,
ETS_H264_DMA2D_IN_CH1_INT_SOURCE,
ETS_H264_DMA2D_IN_CH2_INT_SOURCE,
ETS_H264_DMA2D_IN_CH3_INT_SOURCE,
ETS_H264_DMA2D_IN_CH4_INT_SOURCE,
ETS_H264_DMA2D_IN_CH5_INT_SOURCE,
ETS_H264_REG_INT_SOURCE,
ETS_ASSIST_DEBUG_INT_SOURCE,
ETS_DMA2D_IN_CH2_INT_SOURCE,
ETS_DMA2D_OUT_CH3_INT_SOURCE,
ETS_AXI_PERF_MON_INT_SOURCE,
ETS_MAX_INTR_SOURCE,
} periph_interrupt_t;
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
#ifdef __cplusplus
}
#endif
components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_reg.h
-3116
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components/soc/esp32p4/register/hw_ver3/soc/ledc_eco5_struct.h
-1359
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components/soc/esp32p4/register/hw_ver3/soc/ledc_reg.h
+584 -384
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components/soc/esp32p4/register/hw_ver3/soc/ledc_struct.h
+722 -623
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components/soc/esp32p4/register/hw_ver3/soc/ppa_eco5_struct.h
-1025
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components/soc/esp32p4/register/hw_ver3/soc/ppa_reg.h
+26 -27
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@@ -43,10 +43,9 @@ extern "C" {
#define PPA_CLUT_CONF_REG (DR_REG_PPA_BASE + 0xc)
/** PPA_APB_FIFO_MASK : R/W; bitpos: [0]; default: 0;
* 1'b0: fifo mode to wr/rd clut0/clut1 RAM through register
* PPA_SR_CLUT_DATA_REG/PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1:
* memory mode to wr/rd sr/blend0/blend1 clut RAM. The bit 11 and 10 of the waddr
* should be 01 to access sr clut and should be 10 to access blend0 clut and should be
* 11 to access blend 1 clut in memory mode.
* PPA_BLEND0_CLUT_DATA_REG/PPA_BLEND1_CLUT_DATA_REG. 1'b1:
* memory mode to wr/rd blend0/blend1 clut RAM. The bit 11 and 10 of the waddr
* should be 01 to access blend0 clut and should be 10 to access blend1 clut in memory mode.
*/
#define PPA_APB_FIFO_MASK (BIT(0))
#define PPA_APB_FIFO_MASK_M (PPA_APB_FIFO_MASK_V << PPA_APB_FIFO_MASK_S)
@@ -225,7 +224,7 @@ extern "C" {
#define PPA_BLEND_EOF_INT_CLR_V 0x00000001U
#define PPA_BLEND_EOF_INT_CLR_S 1
/** PPA_SR_PARAM_CFG_ERR_INT_CLR : WT; bitpos: [2]; default: 0;
* Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt.
* Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt.
*/
#define PPA_SR_PARAM_CFG_ERR_INT_CLR (BIT(2))
#define PPA_SR_PARAM_CFG_ERR_INT_CLR_M (PPA_SR_PARAM_CFG_ERR_INT_CLR_V << PPA_SR_PARAM_CFG_ERR_INT_CLR_S)
@@ -273,20 +272,20 @@ extern "C" {
#define PPA_YUV_TX_RANGE_M (PPA_YUV_TX_RANGE_V << PPA_YUV_TX_RANGE_S)
#define PPA_YUV_TX_RANGE_V 0x00000001U
#define PPA_YUV_TX_RANGE_S 9
/** PPA_YUV2RGB_PROTOCAL : R/W; bitpos: [10]; default: 0;
/** PPA_YUV2RGB_PROTOCOL : R/W; bitpos: [10]; default: 0;
* YUV to RGB protocol when reg_sr_rx_cm is 4'd8. 0: BT601. 1: BT709
*/
#define PPA_YUV2RGB_PROTOCAL (BIT(10))
#define PPA_YUV2RGB_PROTOCAL_M (PPA_YUV2RGB_PROTOCAL_V << PPA_YUV2RGB_PROTOCAL_S)
#define PPA_YUV2RGB_PROTOCAL_V 0x00000001U
#define PPA_YUV2RGB_PROTOCAL_S 10
/** PPA_RGB2YUV_PROTOCAL : R/W; bitpos: [11]; default: 0;
#define PPA_YUV2RGB_PROTOCOL (BIT(10))
#define PPA_YUV2RGB_PROTOCOL_M (PPA_YUV2RGB_PROTOCOL_V << PPA_YUV2RGB_PROTOCOL_S)
#define PPA_YUV2RGB_PROTOCOL_V 0x00000001U
#define PPA_YUV2RGB_PROTOCOL_S 10
/** PPA_RGB2YUV_PROTOCOL : R/W; bitpos: [11]; default: 0;
* RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
*/
#define PPA_RGB2YUV_PROTOCAL (BIT(11))
#define PPA_RGB2YUV_PROTOCAL_M (PPA_RGB2YUV_PROTOCAL_V << PPA_RGB2YUV_PROTOCAL_S)
#define PPA_RGB2YUV_PROTOCAL_V 0x00000001U
#define PPA_RGB2YUV_PROTOCAL_S 11
#define PPA_RGB2YUV_PROTOCOL (BIT(11))
#define PPA_RGB2YUV_PROTOCOL_M (PPA_RGB2YUV_PROTOCOL_V << PPA_RGB2YUV_PROTOCOL_S)
#define PPA_RGB2YUV_PROTOCOL_V 0x00000001U
#define PPA_RGB2YUV_PROTOCOL_S 11
/** PPA_YUV422_RX_BYTE_ORDER : R/W; bitpos: [13:12]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
*/
@@ -337,20 +336,20 @@ extern "C" {
#define PPA_BLEND_TX_YUV_RANGE_M (PPA_BLEND_TX_YUV_RANGE_V << PPA_BLEND_TX_YUV_RANGE_S)
#define PPA_BLEND_TX_YUV_RANGE_V 0x00000001U
#define PPA_BLEND_TX_YUV_RANGE_S 13
/** PPA_BLEND0_RX_YUV2RGB_PROTOCAL : R/W; bitpos: [14]; default: 0;
/** PPA_BLEND0_RX_YUV2RGB_PROTOCOL : R/W; bitpos: [14]; default: 0;
* YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709
*/
#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL (BIT(14))
#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S)
#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_V 0x00000001U
#define PPA_BLEND0_RX_YUV2RGB_PROTOCAL_S 14
/** PPA_BLEND_TX_RGB2YUV_PROTOCAL : R/W; bitpos: [15]; default: 0;
#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL (BIT(14))
#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_M (PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V << PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S)
#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_V 0x00000001U
#define PPA_BLEND0_RX_YUV2RGB_PROTOCOL_S 14
/** PPA_BLEND_TX_RGB2YUV_PROTOCOL : R/W; bitpos: [15]; default: 0;
* RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709
*/
#define PPA_BLEND_TX_RGB2YUV_PROTOCAL (BIT(15))
#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_M (PPA_BLEND_TX_RGB2YUV_PROTOCAL_V << PPA_BLEND_TX_RGB2YUV_PROTOCAL_S)
#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_V 0x00000001U
#define PPA_BLEND_TX_RGB2YUV_PROTOCAL_S 15
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL (BIT(15))
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_M (PPA_BLEND_TX_RGB2YUV_PROTOCOL_V << PPA_BLEND_TX_RGB2YUV_PROTOCOL_S)
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_V 0x00000001U
#define PPA_BLEND_TX_RGB2YUV_PROTOCOL_S 15
/** PPA_BLEND0_RX_YUV422_BYTE_ORDER : R/W; bitpos: [17:16]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
*/
@@ -554,7 +553,7 @@ extern "C" {
#define PPA_BLEND1_RX_FIX_ALPHA_S 8
/** PPA_BLEND0_RX_ALPHA_MOD : R/W; bitpos: [17:16]; default: 0;
* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2:
* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
* Original alpha multiply with PPA_SR_BLEND0_ALPHA/256.
*/
#define PPA_BLEND0_RX_ALPHA_MOD 0x00000003U
#define PPA_BLEND0_RX_ALPHA_MOD_M (PPA_BLEND0_RX_ALPHA_MOD_V << PPA_BLEND0_RX_ALPHA_MOD_S)
@@ -562,7 +561,7 @@ extern "C" {
#define PPA_BLEND0_RX_ALPHA_MOD_S 16
/** PPA_BLEND1_RX_ALPHA_MOD : R/W; bitpos: [19:18]; default: 0;
* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2:
* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
* Original alpha multiply with PPA_SR_BLEND1_ALPHA/256.
*/
#define PPA_BLEND1_RX_ALPHA_MOD 0x00000003U
#define PPA_BLEND1_RX_ALPHA_MOD_M (PPA_BLEND1_RX_ALPHA_MOD_V << PPA_BLEND1_RX_ALPHA_MOD_S)
components/soc/esp32p4/register/hw_ver3/soc/ppa_struct.h
+144 -28
View File
@@ -91,12 +91,12 @@ typedef union {
struct {
/** sr_rx_cm : R/W; bitpos: [3:0]; default: 0;
* The source image color mode for Scaling and Rotating engine Rx. 0: ARGB8888. 1:
* RGB888. 2: RGB565. 8: YUV420. others: Reserved.
* RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved.
*/
uint32_t sr_rx_cm:4;
/** sr_tx_cm : R/W; bitpos: [7:4]; default: 0;
* The destination image color mode for Scaling and Rotating engine Tx. 0: ARGB8888.
* 1: RGB888. 2: RGB565. 8: YUV420. others: Reserved.
* 1: RGB888. 2: RGB565. 8: YUV420. 9: YUV422. 12: GRAY. others: Reserved.
*/
uint32_t sr_tx_cm:4;
/** yuv_rx_range : R/W; bitpos: [8]; default: 0;
@@ -115,7 +115,11 @@ typedef union {
* RGB to YUV protocol when reg_sr_tx_cm is 4'd8. 0: BT601. 1: BT709
*/
uint32_t rgb2yuv_protocol:1;
uint32_t reserved_12:20;
/** yuv422_rx_byte_order : R/W; bitpos: [13:12]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
*/
uint32_t yuv422_rx_byte_order:2;
uint32_t reserved_14:18;
};
uint32_t val;
} ppa_sr_color_mode_reg_t;
@@ -127,7 +131,7 @@ typedef union {
struct {
/** blend0_rx_cm : R/W; bitpos: [3:0]; default: 0;
* The source image color mode for background plane. 0: ARGB8888. 1: RGB888. 2:
* RGB565. 3: Reserved. 4: L8. 5: L4.
* RGB565. 3: Reserved. 4: L8. 5: L4. 8: YUV420. 9: YUV422. 12:GRAY
*/
uint32_t blend0_rx_cm:4;
/** blend1_rx_cm : R/W; bitpos: [7:4]; default: 0;
@@ -137,10 +141,30 @@ typedef union {
uint32_t blend1_rx_cm:4;
/** blend_tx_cm : R/W; bitpos: [11:8]; default: 0;
* The destination image color mode for output of blender. 0: ARGB8888. 1: RGB888. 2:
* RGB565. 3: Reserved..
* RGB565. 3: Reserved. 8: YUV420. 9: YUV422. 12:GRAY
*/
uint32_t blend_tx_cm:4;
uint32_t reserved_12:20;
/** blend0_rx_yuv_range : R/W; bitpos: [12]; default: 0;
* YUV input range when blend0 rx cm is yuv. 0: limit range. 1: full range
*/
uint32_t blend0_rx_yuv_range:1;
/** blend_tx_yuv_range : R/W; bitpos: [13]; default: 0;
* YUV output range when blend tx cm is yuv. 0: limit range. 1: full range
*/
uint32_t blend_tx_yuv_range:1;
/** blend0_rx_yuv2rgb_protocol : R/W; bitpos: [14]; default: 0;
* YUV to RGB protocol when blend0 rx cm is yuv. 0: BT601. 1: BT709
*/
uint32_t blend0_rx_yuv2rgb_protocol:1;
/** blend_tx_rgb2yuv_protocol : R/W; bitpos: [15]; default: 0;
* RGB to YUV protocol when blend tx cm is yuv. 0: BT601. 1: BT709
*/
uint32_t blend_tx_rgb2yuv_protocol:1;
/** blend0_rx_yuv422_byte_order : R/W; bitpos: [17:16]; default: 0;
* YUV422 input byte order when reg_sr_rx_cm is 4'd9. 0: YVYU, 1:YUYV, 2: VYUY, 3: UYVY
*/
uint32_t blend0_rx_yuv422_byte_order:2;
uint32_t reserved_18:14;
};
uint32_t val;
} ppa_blend_color_mode_reg_t;
@@ -165,7 +189,11 @@ typedef union {
* to improve efficient accessing external memory.
*/
uint32_t sr_macro_bk_ro_bypass:1;
uint32_t reserved_3:29;
/** sr_bk_size_sel : R/W; bitpos: [3]; default: 0;
* sel srm pix_blk size, 0:32x32, 1:16x16
*/
uint32_t sr_bk_size_sel:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ppa_sr_byte_order_reg_t;
@@ -227,7 +255,12 @@ typedef union {
* write 1 then write 0 to reset blending engine.
*/
uint32_t blend_rst:1;
uint32_t reserved_5:27;
/** blend_tx_inf_sel : R/W; bitpos: [6:5]; default: 0;
* unused ! Configures blend tx interface. 0: dma2d only, 1: le_enc only, 2: dma2d and
* ls_enc
*/
uint32_t blend_tx_inf_sel:2;
uint32_t reserved_7:25;
};
uint32_t val;
} ppa_blend_trans_mode_reg_t;
@@ -263,13 +296,13 @@ typedef union {
typedef union {
struct {
/** blend_hb : R/W; bitpos: [13:0]; default: 0;
* The horizontal width of image block that would be filled in fix pixel filling mode.
* The unit is pixel
* The horizontal width of image block that would be filled in fix pixel filling mode
* or blend mode. The unit is pixel. Must be even num when YUV422 or YUV420
*/
uint32_t blend_hb:14;
/** blend_vb : R/W; bitpos: [27:14]; default: 0;
* The vertical width of image block that would be filled in fix pixel filling mode.
* The unit is pixel
* The vertical width of image block that would be filled in fix pixel filling mode or
* blend mode. The unit is pixel. Must be even num when YUV420
*/
uint32_t blend_vb:14;
uint32_t reserved_28:4;
@@ -293,13 +326,13 @@ typedef union {
*/
uint32_t blend1_rx_fix_alpha:8;
/** blend0_rx_alpha_mod : R/W; bitpos: [17:16]; default: 0;
* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND0_FIX_ALPHA. 2:
* Original alpha multiply with PPA_BLEND0_FIX_ALPHA/256.
*/
uint32_t blend0_rx_alpha_mod:2;
/** blend1_rx_alpha_mod : R/W; bitpos: [19:18]; default: 0;
* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_SR_FIX_ALPHA. 2:
* Original alpha multiply with PPA_SR_FIX_ALPHA/256.
* Alpha mode. 0/3: not replace alpha. 1: replace alpha with PPA_BLEND1_FIX_ALPHA. 2:
* Original alpha multiply with PPA_BLEND1_FIX_ALPHA/256.
*/
uint32_t blend1_rx_alpha_mod:2;
/** blend0_rx_alpha_inv : R/W; bitpos: [20]; default: 0;
@@ -612,7 +645,12 @@ typedef union {
* PPA_SR_PARAM_ERR_ST_REG.
*/
uint32_t sr_param_cfg_err_int_raw:1;
uint32_t reserved_3:29;
/** blend_param_cfg_err_int_raw : R/WTC/SS; bitpos: [3]; default: 0;
* The raw interrupt bit turns to high level when the configured blending coefficient
* is wrong. User can check the reasons through register PPA_BLEND_ST_REG.
*/
uint32_t blend_param_cfg_err_int_raw:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ppa_int_raw_reg_t;
@@ -631,10 +669,14 @@ typedef union {
*/
uint32_t blend_eof_int_st:1;
/** sr_param_cfg_err_int_st : RO; bitpos: [2]; default: 0;
* The raw interrupt status bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
* The raw interrupt status bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt.
*/
uint32_t sr_param_cfg_err_int_st:1;
uint32_t reserved_3:29;
/** blend_param_cfg_err_int_st : RO; bitpos: [3]; default: 0;
* The raw interrupt status bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
*/
uint32_t blend_param_cfg_err_int_st:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ppa_int_st_reg_t;
@@ -653,10 +695,14 @@ typedef union {
*/
uint32_t blend_eof_int_ena:1;
/** sr_param_cfg_err_int_ena : R/W; bitpos: [2]; default: 0;
* The interrupt enable bit for the PPA_SR_RX_YSCAL_ERR_INT interrupt.
* The interrupt enable bit for the PPA_SR_PARAM_CFG_ERR_INT interrupt.
*/
uint32_t sr_param_cfg_err_int_ena:1;
uint32_t reserved_3:29;
/** blend_param_cfg_err_int_ena : R/W; bitpos: [3]; default: 0;
* The interrupt enable bit for the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
*/
uint32_t blend_param_cfg_err_int_ena:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ppa_int_ena_reg_t;
@@ -675,10 +721,14 @@ typedef union {
*/
uint32_t blend_eof_int_clr:1;
/** sr_param_cfg_err_int_clr : WT; bitpos: [2]; default: 0;
* Set this bit to clear the PPA_SR_RX_YSCAL_ERR_INT interrupt.
* Set this bit to clear the PPA_SR_PARAM_CFG_ERR_INT interrupt.
*/
uint32_t sr_param_cfg_err_int_clr:1;
uint32_t reserved_3:29;
/** blend_param_cfg_err_int_clr : WT; bitpos: [3]; default: 0;
* Set this bit to clear the PPA_BLEND_PARAM_CFG_ERR_INT interrupt.
*/
uint32_t blend_param_cfg_err_int_clr:1;
uint32_t reserved_4:28;
};
uint32_t val;
} ppa_int_clr_reg_t;
@@ -712,7 +762,15 @@ typedef union {
* 1: indicate the size of two image is different.
*/
uint32_t blend_size_diff_st:1;
uint32_t reserved_1:31;
/** blend_yuv_x_scale_err_st : RO; bitpos: [1]; default: 0;
* Represents that x param is an odd num when enable yuv422 or yuv420
*/
uint32_t blend_yuv_x_scale_err_st:1;
/** blend_yuv_y_scale_err_st : RO; bitpos: [2]; default: 0;
* Represents that y param is an odd num when enable yuv420
*/
uint32_t blend_yuv_y_scale_err_st:1;
uint32_t reserved_3:29;
};
uint32_t val;
} ppa_blend_st_reg_t;
@@ -773,7 +831,7 @@ typedef union {
uint32_t xdst_len_too_large_err_st:1;
/** x_yuv420_rx_scale_err_st : RO; bitpos: [10]; default: 0;
* The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
* yuv420 rx
* yuv422 or yuv420 rx
*/
uint32_t x_yuv420_rx_scale_err_st:1;
/** y_yuv420_rx_scale_err_st : RO; bitpos: [11]; default: 0;
@@ -783,7 +841,7 @@ typedef union {
uint32_t y_yuv420_rx_scale_err_st:1;
/** x_yuv420_tx_scale_err_st : RO; bitpos: [12]; default: 0;
* The error is that the ha/hb/x param in dma2d descriptor is an odd num when enable
* yuv420 tx
* yuv422 or yuv420 tx
*/
uint32_t x_yuv420_tx_scale_err_st:1;
/** y_yuv420_tx_scale_err_st : RO; bitpos: [13]; default: 0;
@@ -841,13 +899,68 @@ typedef union {
} ppa_eco_cell_ctrl_reg_t;
/** Group: Debug Register */
/** Type of debug_ctrl0 register
* debug register
*/
typedef union {
struct {
/** dbg_replace_sel : R/W; bitpos: [2:0]; default: 0;
* Configures the data replace location. 0: not replace, 1: srm rx input, 2: srm rx
* bilin interpolation, 3: srm tx output, 4: blend fg input, 5: blend bg input, 6:
* blend output
*/
uint32_t dbg_replace_sel:3;
uint32_t reserved_3:29;
};
uint32_t val;
} ppa_debug_ctrl0_reg_t;
/** Type of debug_ctrl1 register
* debug register
*/
typedef union {
struct {
/** dbg_replace_data : R/W; bitpos: [31:0]; default: 0;
* Configures the replace data
*/
uint32_t dbg_replace_data:32;
};
uint32_t val;
} ppa_debug_ctrl1_reg_t;
/** Group: Configuration Register */
/** Type of rgb2gray register
* rgb2gray register
*/
typedef union {
struct {
/** rgb2gray_b : R/W; bitpos: [7:0]; default: 85;
* Configures the b parameter for rgb2gray
*/
uint32_t rgb2gray_b:8;
/** rgb2gray_g : R/W; bitpos: [15:8]; default: 86;
* Configures the g parameter for rgb2gray
*/
uint32_t rgb2gray_g:8;
/** rgb2gray_r : R/W; bitpos: [23:16]; default: 85;
* Configures the r parameter for rgb2gray
*/
uint32_t rgb2gray_r:8;
uint32_t reserved_24:8;
};
uint32_t val;
} ppa_rgb2gray_reg_t;
/** Group: Version Register */
/** Type of date register
* PPA Version register
*/
typedef union {
struct {
/** date : R/W; bitpos: [31:0]; default: 36716609;
/** date : R/W; bitpos: [31:0]; default: 539234848;
* register version.
*/
uint32_t date:32;
@@ -893,7 +1006,10 @@ typedef struct ppa_dev_t {
volatile ppa_eco_high_reg_t eco_high;
volatile ppa_eco_cell_ctrl_reg_t eco_cell_ctrl;
volatile ppa_sram_ctrl_reg_t sram_ctrl;
uint32_t reserved_090[28];
volatile ppa_debug_ctrl0_reg_t debug_ctrl0;
volatile ppa_debug_ctrl1_reg_t debug_ctrl1;
volatile ppa_rgb2gray_reg_t rgb2gray;
uint32_t reserved_09c[25];
volatile ppa_date_reg_t date;
} ppa_dev_t;
components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_reg.h
-1579
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File diff suppressed because it is too large Load Diff
components/soc/esp32p4/register/hw_ver3/soc/uart_eco5_struct.h
-1274
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File diff suppressed because it is too large Load Diff
components/soc/esp32p4/register/hw_ver3/soc/uart_reg.h
-2
View File
@@ -11,8 +11,6 @@
extern "C" {
#endif
// TODO: IDF-13425
/** UART_FIFO_REG register
* FIFO data register
*/
components/soc/esp32p4/register/hw_ver3/soc/uart_struct.h
+2 -3
View File
@@ -10,8 +10,6 @@
extern "C" {
#endif
// TODO: IDF-13425
/** Group: FIFO Configuration */
/** Type of fifo register
* FIFO data register
@@ -21,7 +19,8 @@ typedef union {
/** rxfifo_rd_byte : RO; bitpos: [7:0]; default: 0;
* UART $n accesses FIFO via this register.
*/
uint32_t rxfifo_rd_byte:32;
uint32_t rxfifo_rd_byte:8;
uint32_t reserved_8:24;
};
uint32_t val;
} uart_fifo_reg_t;
docs/en/api-reference/peripherals/ledc.rst
+4
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@@ -279,6 +279,10 @@ The range of the duty cycle values passed to functions depends on selected ``dut
The hardware limitation above only applies to chip revision before v1.2.
.. only:: esp32p4
The hardware limitation above only applies to chip revision before v3.0.
Change PWM Duty Cycle Using Hardware
""""""""""""""""""""""""""""""""""""
docs/zh_CN/api-reference/peripherals/ledc.rst
+4
View File
@@ -279,6 +279,10 @@ LEDC 驱动提供了一个辅助函数 :cpp:func:`ledc_find_suitable_duty_resolu
以上硬件限制仅在芯片版本低于 v1.2 的 ESP32H2 上存在。
.. only:: esp32p4
以上硬件限制仅在芯片版本低于 v3.0 的 ESP32P4 上存在。
使用硬件改变 PWM 占空比
""""""""""""""""""""""""""""""""""""
examples/peripherals/ledc/ledc_basic/main/ledc_basic_example_main.c
+1 -1
View File
@@ -19,7 +19,7 @@
#define LEDC_FREQUENCY (4000) // Frequency in Hertz. Set frequency at 4 kHz
/* Warning:
* For ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 targets,
* For ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32C2, ESP32C6, ESP32H2 (rev < 1.2), ESP32P4 (rev < 3.0) targets,
* when LEDC_DUTY_RES selects the maximum duty resolution (i.e. value equal to SOC_LEDC_TIMER_BIT_WIDTH),
* 100% duty cycle is not reachable (duty cannot be set to (2 ** SOC_LEDC_TIMER_BIT_WIDTH)).
*/