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https://github.com/espressif/esp-idf.git
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change(esp_hw_support): allow rtc_periph pd when top pd for esp32h4 eco1
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@@ -2962,9 +2962,9 @@ static SLEEP_FN_ATTR uint32_t get_power_down_flags(void)
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}
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#endif
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#if CONFIG_IDF_TARGET_ESP32C6
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#if SOC_PM_TOP_DEPENDS_ON_RTC_PERIPH
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if (!(pd_flags & PMU_SLEEP_PD_TOP)) {
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// TOP power domain depends on the RTC_PERIPH power domain on ESP32C6, RTC_PERIPH should only be disabled when the TOP domain is down.
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// TOP power domain depends on the RTC_PERIPH power domain on ESP32C6 and ESP32H4, RTC_PERIPH should only be disabled when the TOP domain is down.
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pd_flags &= ~RTC_SLEEP_PD_RTC_PERIPH;
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}
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#endif
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@@ -1203,6 +1203,10 @@ config SOC_PM_RETENTION_MODULE_NUM
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int
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default 32
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config SOC_PM_TOP_DEPENDS_ON_RTC_PERIPH
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bool
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default y
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config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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bool
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default y
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@@ -497,6 +497,8 @@
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#define SOC_PM_RETENTION_MODULE_NUM (32)
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#define SOC_PM_TOP_DEPENDS_ON_RTC_PERIPH (1)
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
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@@ -1011,6 +1011,10 @@ config SOC_PM_SUPPORT_MAC_BB_PD
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bool
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default y
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config SOC_PM_SUPPORT_RTC_PERIPH_PD
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bool
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default y
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config SOC_PM_SUPPORT_PMU_CLK_ICG
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bool
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default y
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@@ -1051,6 +1055,10 @@ config SOC_PM_RETENTION_MODULE_NUM
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int
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default 64
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config SOC_PM_TOP_DEPENDS_ON_RTC_PERIPH
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bool
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default y
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config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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bool
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default y
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@@ -481,7 +481,7 @@
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#define SOC_PM_SUPPORT_TOP_PD (1)
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#define SOC_PM_SUPPORT_HP_AON_PD (1)
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#define SOC_PM_SUPPORT_MAC_BB_PD (1)
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// #define SOC_PM_SUPPORT_RTC_PERIPH_PD (1) // TODO: [ESP32H4] PM-484
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#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
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// #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1)
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// /* macro redefine for pass esp_wifi headers md5sum check */
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@@ -500,6 +500,8 @@
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#define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
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#define SOC_PM_RETENTION_MODULE_NUM (64)
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#define SOC_PM_TOP_DEPENDS_ON_RTC_PERIPH (1) // In ESP32H4, RTC_PERIPH should be pd only together with TOP, otherwise there is some current leak.
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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