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Merge branch 'bugfix/lp_io_clock_control' into 'master'

Browse Source 
fix(rtcio): RTC GPIO configuration should be written only if LP IO clock exists

Closes IDF-14951

See merge request espressif/esp-idf!46146
This commit is contained in:
Song Ruo Jing
2026-03-04 19:23:33 +08:00
parent d8df5d32fe d4005779e0
commit e3a2865606
49 changed files with 294 additions and 179 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_gpio/src/gpio.c
-3
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@@ -487,9 +487,6 @@ esp_err_t gpio_config_as_analog(gpio_num_t gpio_num)
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
if (rtc_gpio_is_valid_gpio(gpio_num)) {
rtc_gpio_deinit(gpio_num);
rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED);
rtc_gpio_pullup_dis(gpio_num);
rtc_gpio_pulldown_dis(gpio_num);
}
#endif
return ESP_OK;
components/esp_driver_gpio/src/rtc_io.c
+13 -7
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -64,13 +64,19 @@ esp_err_t rtc_gpio_deinit(gpio_num_t gpio_num)
{
ESP_RETURN_ON_FALSE(rtc_gpio_is_valid_gpio(gpio_num), ESP_ERR_INVALID_ARG, RTCIO_TAG, "RTCIO number error");
RTCIO_ENTER_CRITICAL();
// Select Gpio as Digital Gpio
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_DIGITAL);
// TODO: IDF-14951 Turning off the lp io clock might affect other lp peripherals. Temporary disabled.
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT && !CONFIG_IDF_TARGET_ESP32H4
io_mux_force_disable_lp_io_clock(gpio_num);
if (io_mux_is_lp_io_in_use(gpio_num)) {
// Select GPIO as Digital GPIO
rtcio_hal_function_select(rtc_io_number_get(gpio_num), RTCIO_LL_FUNC_DIGITAL);
#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
// Disable any configuration of the RTC IO that may affect the GPIO behavior
rtc_gpio_set_direction(gpio_num, RTC_GPIO_MODE_DISABLED);
rtc_gpio_pullup_dis(gpio_num);
rtc_gpio_pulldown_dis(gpio_num);
#endif
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
io_mux_force_disable_lp_io_clock(gpio_num);
#endif
}
RTCIO_EXIT_CRITICAL();
return ESP_OK;
components/esp_driver_uart/test_apps/uart/main/test_uart.c
+9 -7
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -730,10 +730,8 @@ IRAM_ATTR static void uart_signal_inject_glitch_task(void *param)
rtcio_ll_set_level(rtc_gpio_num, 1);
#endif
// esp_rom_delay_us(1000); // wait for uart write task to start sending data
while (1) {
// make sure the glitch is always less than 5us
// make sure the glitch is always less than 6us
portDISABLE_INTERRUPTS();
if (uart_num < SOC_UART_HP_NUM) {
esp_rom_gpio_connect_out_signal(tx_pin, SIG_GPIO_OUT_IDX, false, false);
@@ -761,10 +759,14 @@ TEST_CASE("uart rx glitch filter (read write test + auto baud rate detection tes
port_param.tx_pin_num = port_param.rx_pin_num; // let tx and rx use the same pin
uart_port_t uart_num = port_param.port_num;
// High speed clock source may not able to filter a 5us glitch, therefore, lower the source clock frequency
// High speed clock source may not able to filter a 6us glitch, therefore, lower the source clock frequency
if (uart_num < SOC_UART_HP_NUM) {
#if SOC_UART_SUPPORT_XTAL_CLK
#if SOC_UART_SUPPORT_XTAL_CLK && (CONFIG_XTAL_FREQ == 40)
port_param.default_src_clk = UART_SCLK_XTAL;
#elif SOC_UART_SUPPORT_RTC_CLK
port_param.default_src_clk = UART_SCLK_RTC;
#elif SOC_UART_SUPPORT_REF_TICK
port_param.default_src_clk = UART_SCLK_REF_TICK;
#endif
}
uart_config_t uart_config = {
@@ -775,7 +777,7 @@ TEST_CASE("uart rx glitch filter (read write test + auto baud rate detection tes
.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
.source_clk = port_param.default_src_clk,
#if !UART_LL_GLITCH_FILT_ONLY_ON_AUTOBAUD
.rx_glitch_filt_thresh = 5000, // filter all glitches with width less than 5us
.rx_glitch_filt_thresh = 6000, // filter all glitches with width less than 6us
#endif
};
components/esp_hal_gpio/esp32/include/hal/gpio_ll.h
+1
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@@ -739,6 +739,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32c2/include/hal/gpio_ll.h
+1
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@@ -545,6 +545,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32c3/include/hal/gpio_ll.h
+1
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@@ -542,6 +542,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32c5/include/hal/gpio_ll.h
+1
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@@ -529,6 +529,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32c5/include/hal/rtc_io_ll.h
+3 -1
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@@ -25,7 +25,9 @@
#include "hal/misc.h"
#include "hal/assert.h"
#define RTCIO_LL_PIN_FUNC 1
#define RTCIO_LL_PIN_FUNC 1
#define RTCIO_LL_GPIO_NUM_OFFSET 0 // rtcio 0-6 correspond to gpio 0-6
#ifdef __cplusplus
extern "C" {
components/esp_hal_gpio/esp32c6/include/hal/gpio_ll.h
+1
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@@ -493,6 +493,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32c6/include/hal/rtc_io_ll.h
+3 -1
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@@ -24,7 +24,9 @@
#include "hal/misc.h"
#include "hal/assert.h"
#define RTCIO_LL_PIN_FUNC 0
#define RTCIO_LL_PIN_FUNC 0
#define RTCIO_LL_GPIO_NUM_OFFSET 0 // rtcio 0-7 correspond to gpio 0-7
#ifdef __cplusplus
extern "C" {
components/esp_hal_gpio/esp32c61/include/hal/gpio_ll.h
+1
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@@ -529,6 +529,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->funcn_out_sel_cfg[gpio_num].funcn_oe_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32c61/include/hal/rtc_io_ll.h
+3 -1
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@@ -25,7 +25,9 @@
#include "hal/misc.h"
#include "hal/assert.h"
#define RTCIO_LL_PIN_FUNC 1
#define RTCIO_LL_PIN_FUNC 1
#define RTCIO_LL_GPIO_NUM_OFFSET 0 // rtcio 0-6 correspond to gpio 0-6
#ifdef __cplusplus
extern "C" {
components/esp_hal_gpio/esp32h2/include/hal/gpio_ll.h
+1
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@@ -539,6 +539,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32h21/include/hal/gpio_ll.h
+1
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@@ -520,6 +520,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->funcn_out_sel_cfg[gpio_num].funcn_oe_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32h4/include/hal/gpio_ll.h
+1
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@@ -538,6 +538,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->funcn_out_sel_cfg[gpio_num].oe_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32h4/include/hal/rtc_io_ll.h
+3 -1
View File
@@ -25,7 +25,9 @@
#include "hal/misc.h"
#include "hal/assert.h"
#define RTCIO_LL_PIN_FUNC 1
#define RTCIO_LL_PIN_FUNC 1
#define RTCIO_LL_GPIO_NUM_OFFSET 0 // rtcio 0-5 correspond to gpio 0-5
#ifdef __cplusplus
extern "C" {
components/esp_hal_gpio/esp32p4/include/hal/gpio_ll.h
+1
View File
@@ -655,6 +655,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32p4/include/hal/rtc_io_ll.h
+3 -1
View File
@@ -25,7 +25,9 @@
#include "hal/assert.h"
#include "hal/config.h"
#define RTCIO_LL_PIN_FUNC 1 // LP_GPIO function
#define RTCIO_LL_PIN_FUNC 1 // LP_GPIO function
#define RTCIO_LL_GPIO_NUM_OFFSET 0 // rtcio 0-15 correspond to gpio 0-15
#ifdef __cplusplus
extern "C" {
components/esp_hal_gpio/esp32s2/include/hal/gpio_ll.h
+1
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@@ -560,6 +560,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32s2/include/hal/rtc_io_ll.h
+3 -1
View File
@@ -22,7 +22,9 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/sens_struct.h"
#define RTCIO_LL_PIN_FUNC 0
#define RTCIO_LL_PIN_FUNC 0
#define RTCIO_LL_GPIO_NUM_OFFSET 0 // rtcio 0-21 correspond to gpio 0-21
#ifdef __cplusplus
extern "C" {
components/esp_hal_gpio/esp32s3/include/hal/gpio_ll.h
+1
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@@ -562,6 +562,7 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32s3/include/hal/rtc_io_ll.h
+3 -1
View File
@@ -26,7 +26,9 @@
#include "soc/sens_struct.h"
#include "soc/rtc_cntl_reg.h"
#define RTCIO_LL_PIN_FUNC 0
#define RTCIO_LL_PIN_FUNC 0
#define RTCIO_LL_GPIO_NUM_OFFSET 0 // rtcio 0-21 correspond to gpio 0-21
#ifdef __cplusplus
extern "C" {
components/esp_hal_gpio/esp32s31/include/hal/gpio_ll.h
+1
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@@ -582,6 +582,7 @@ static inline void gpio_ll_set_input_signal_matrix_source(gpio_dev_t *hw, uint32
* @param ctrl_by_periph True if use output enable signal from peripheral, false if force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG
* @param oen_inv True if the output enable needs to be inverted, otherwise False.
*/
__attribute__((always_inline))
static inline void gpio_ll_set_output_enable_ctrl(gpio_dev_t *hw, uint8_t gpio_num, bool ctrl_by_periph, bool oen_inv)
{
hw->func_out_sel_cfg[gpio_num].oen_inv_sel = oen_inv; // control valid only when using gpio matrix to route signal to the IO
components/esp_hal_gpio/esp32s31/include/hal/rtc_io_ll.h
+3 -1
View File
@@ -24,7 +24,9 @@
#include "hal/misc.h"
#include "hal/assert.h"
#define RTCIO_LL_PIN_FUNC 1
#define RTCIO_LL_PIN_FUNC 1
#define RTCIO_LL_GPIO_NUM_OFFSET 0 // rtcio 0-7 correspond to gpio 0-7
#ifdef __cplusplus
extern "C" {
components/esp_hw_support/include/esp_private/io_mux.h
+16 -5
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,7 +11,6 @@
#include "soc/clk_tree_defs.h"
#include "soc/gpio_num.h"
#include "soc/soc_caps.h"
#include "soc/io_mux_reg.h"
#ifdef __cplusplus
extern "C" {
@@ -32,8 +31,8 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src);
#if SOC_LP_IO_CLOCK_IS_INDEPENDENT
typedef struct {
uint8_t rtc_io_enabled_cnt[MAX_RTC_GPIO_NUM + 1];
uint32_t rtc_io_using_mask;
uint8_t rtc_io_enabled_cnt[SOC_RTCIO_PIN_COUNT];
uint32_t rtc_io_using_mask : SOC_RTCIO_PIN_COUNT;
} rtc_io_status_t;
/**
@@ -45,12 +44,24 @@ typedef struct {
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable);
/**
* Force disable one LP_IO to clock dependency
* @brief Force disable one LP_IO to clock dependency
*
* @param gpio_num GPIO number
*/
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num);
#endif
#if SOC_RTCIO_PIN_COUNT > 0
/**
* @brief Check if the LP_IO is in use
*
* @param gpio_num GPIO number
*
* @return true if the LP_IO is in use, false otherwise
*/
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num);
#endif
#ifdef __cplusplus
}
#endif
components/esp_hw_support/port/esp32/io_mux.c
+9 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,3 +11,11 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
// IO MUX clock source is not selectable
return ESP_OK;
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
// ESP32 does not have SOC_LP_IO_CLOCK_IS_INDEPENDENT
// which means we don't need LP_IO clock management
// So we just always return true here
return true;
}
components/esp_hw_support/port/esp32c5/io_mux.c
+21 -12
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -49,17 +49,18 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -74,10 +75,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -85,3 +87,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/esp_hw_support/port/esp32c6/io_mux.c
+21 -12
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -48,17 +48,18 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -73,10 +74,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -84,3 +86,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/esp_hw_support/port/esp32c61/io_mux.c
+21 -12
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -43,17 +43,18 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -68,10 +69,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -79,3 +81,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/esp_hw_support/port/esp32h2/io_mux.c
+21 -12
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -43,17 +43,18 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -68,10 +69,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -79,3 +81,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/esp_hw_support/port/esp32h21/io_mux.c
+21 -12
View File
@@ -1,6 +1,6 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -44,17 +44,18 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -69,10 +70,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -80,3 +82,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/esp_hw_support/port/esp32h4/io_mux.c
+21 -12
View File
@@ -1,6 +1,6 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -44,17 +44,18 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -69,10 +70,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -80,3 +82,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/esp_hw_support/port/esp32p4/io_mux.c
+21 -12
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -53,17 +53,18 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert((gpio_num != GPIO_NUM_NC) && (gpio_num <= MAX_RTC_GPIO_NUM) && "RTCIO number error");
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -78,10 +79,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert((gpio_num != GPIO_NUM_NC) && (gpio_num <= MAX_RTC_GPIO_NUM) && "RTCIO number error");
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -89,3 +91,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/esp_hw_support/port/esp32s2/io_mux.c
+21 -12
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -31,17 +31,18 @@ static rtc_io_status_t s_rtc_io_status = {
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -56,10 +57,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -67,3 +69,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/esp_hw_support/port/esp32s3/io_mux.c
+21 -12
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -31,17 +31,18 @@ static rtc_io_status_t s_rtc_io_status = {
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -56,10 +57,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert(gpio_num != GPIO_NUM_NC);
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -67,3 +69,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/esp_hw_support/port/esp32s31/io_mux.c
+21 -12
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -53,17 +53,18 @@ esp_err_t io_mux_set_clock_source(soc_module_clk_t clk_src)
void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
{
assert((gpio_num != GPIO_NUM_NC) && (gpio_num <= MAX_RTC_GPIO_NUM) && "RTCIO number error");
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
if (enable) {
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << gpio_num);
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask |= (1ULL << rtc_io_num);
}
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]++;
} else if (!enable && (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0)) {
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num]--;
if (s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] == 0) {
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
}
}
RTCIO_RCC_ATOMIC() {
@@ -78,10 +79,11 @@ void io_mux_enable_lp_io_clock(gpio_num_t gpio_num, bool enable)
void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
{
assert((gpio_num != GPIO_NUM_NC) && (gpio_num <= MAX_RTC_GPIO_NUM) && "RTCIO number error");
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
esp_os_enter_critical(&s_io_mux_spinlock);
s_rtc_io_status.rtc_io_enabled_cnt[gpio_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << gpio_num);
s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] = 0;
s_rtc_io_status.rtc_io_using_mask &= ~(1ULL << rtc_io_num);
if (s_rtc_io_status.rtc_io_using_mask == 0) {
RTCIO_RCC_ATOMIC() {
rtcio_ll_enable_io_clock(false);
@@ -89,3 +91,10 @@ void io_mux_force_disable_lp_io_clock(gpio_num_t gpio_num)
}
esp_os_exit_critical(&s_io_mux_spinlock);
}
bool io_mux_is_lp_io_in_use(gpio_num_t gpio_num)
{
uint32_t rtc_io_num = gpio_num - RTCIO_LL_GPIO_NUM_OFFSET;
assert(rtc_io_num < SOC_RTCIO_PIN_COUNT);
return s_rtc_io_status.rtc_io_enabled_cnt[rtc_io_num] > 0;
}
components/soc/esp32c2/register/soc/io_mux_reg.h
-2
View File
@@ -122,8 +122,6 @@
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define MAX_RTC_GPIO_NUM 5
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32c3/register/soc/io_mux_reg.h
-2
View File
@@ -133,8 +133,6 @@
#define USB_INT_PHY0_DM_GPIO_NUM 18
#define USB_INT_PHY0_DP_GPIO_NUM 19
#define MAX_RTC_GPIO_NUM 5
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
components/soc/esp32c5/register/soc/io_mux_reg.h
-2
View File
@@ -133,8 +133,6 @@ extern "C" {
#define USB_INT_PHY0_DM_GPIO_NUM 13
#define USB_INT_PHY0_DP_GPIO_NUM 14
#define MAX_RTC_GPIO_NUM 6
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32c6/register/soc/io_mux_reg.h
-2
View File
@@ -139,8 +139,6 @@
#define USB_INT_PHY0_DM_GPIO_NUM 12
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 7
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32c61/register/soc/io_mux_reg.h
-2
View File
@@ -109,8 +109,6 @@ extern "C" {
#define USB_INT_PHY0_DM_GPIO_NUM 12
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 6
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32h2/register/soc/io_mux_reg.h
-2
View File
@@ -151,8 +151,6 @@
#define USB_INT_PHY0_DM_GPIO_NUM 26
#define USB_INT_PHY0_DP_GPIO_NUM 27
#define MAX_RTC_GPIO_NUM 14 // GPIO7~14 are the pads with LP function
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32h21/register/soc/io_mux_reg.h
-2
View File
@@ -144,8 +144,6 @@ extern "C" {
#define USB_INT_PHY0_DM_GPIO_NUM 17
#define USB_INT_PHY0_DP_GPIO_NUM 18
#define MAX_RTC_GPIO_NUM 11 // GPIO5~11 are the pads with LP function
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32h4/register/soc/io_mux_reg.h
-2
View File
@@ -137,8 +137,6 @@ extern "C" {
#define USB_OTG_INT_PHY_DM_GPIO_NUM USB_INT_PHY1_DM_GPIO_NUM
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 5
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32p4/register/hw_ver1/soc/io_mux_reg.h
-2
View File
@@ -185,8 +185,6 @@
#define USB_OTG_INT_PHY_DM_GPIO_NUM USB_INT_PHY1_DM_GPIO_NUM
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 15
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
-2
View File
@@ -185,8 +185,6 @@
#define USB_OTG_INT_PHY_DM_GPIO_NUM USB_INT_PHY1_DM_GPIO_NUM
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 15
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32s2/register/soc/io_mux_reg.h
-2
View File
@@ -143,8 +143,6 @@
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define MAX_RTC_GPIO_NUM 21
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
components/soc/esp32s3/register/soc/io_mux_reg.h
-4
View File
@@ -151,10 +151,6 @@
#define SD_DATA3_GPIO_NUM 10
#define USB_INT_PHY0_DM_GPIO_NUM 19
#define USB_INT_PHY0_DP_GPIO_NUM 20
#define XTAL32K_P_GPIO_NUM 15
#define XTAL32K_N_GPIO_NUM 16
#define MAX_RTC_GPIO_NUM 21
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32s31/register/soc/io_mux_reg.h
-2
View File
@@ -139,8 +139,6 @@
#define PIN_FUNC_GPIO 1
#define MAX_RTC_GPIO_NUM 7
#define USB_INT_PHY0_DM_GPIO_NUM 33
#define USB_INT_PHY0_DP_GPIO_NUM 34