mirror of
https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
feat(esp32h4): remove esp32h4 beta5 support
This commit is contained in:
Chen Jichang
@@ -29,9 +29,5 @@ idf_component_register(SRCS ${srcs}
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# Link the ROM WDT HAL implementation linker script if selected
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if(CONFIG_HAL_WDT_USE_ROM_IMPL)
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if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/rom.beta5.wdt.ld")
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else()
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target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/rom.wdt.ld")
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endif()
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target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/rom.wdt.ld")
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endif()
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@@ -1,22 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/***************************************
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Group hal_wdt
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***************************************/
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/* Functions */
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wdt_hal_init = 0x40000370;
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wdt_hal_deinit = 0x40000374;
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wdt_hal_config_stage = 0x40000378;
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wdt_hal_write_protect_disable = 0x4000037c;
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wdt_hal_write_protect_enable = 0x40000380;
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wdt_hal_enable = 0x40000384;
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wdt_hal_disable = 0x40000388;
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wdt_hal_handle_intr = 0x4000038c;
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wdt_hal_feed = 0x40000390;
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wdt_hal_set_flashboot_en = 0x40000394;
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wdt_hal_is_enabled = 0x40000398;
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@@ -1,14 +1,6 @@
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comment "NOTE! Support of ESP32-H4 MP is mutually exclusive"
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comment "Read the help text of the option below for explanation"
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config ESP32H4_SELECTS_REV_MP
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bool "Select ESP32-H4 MP version"
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default y
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help
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Enable this option to select ESP32-H4 MP revision.
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MP revisions have some hardware differences with Beta revision.
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MP revisions is not compatible with Beta revision.
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choice ESP32H4_REV_MIN
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prompt "Minimum Supported ESP32-H4 Revision"
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default ESP32H4_REV_MIN_0
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@@ -122,7 +122,6 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_sys
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/* set dcdc ccm mode software enable */
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pmu_ll_set_dcdc_ccm_sw_en(ctx->hal->dev, true);
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#if CONFIG_ESP32H4_SELECTS_REV_MP
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/* set ble bandgap ocode */
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uint32_t ulp_ocode = 0;
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#if !CONFIG_IDF_ENV_FPGA
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@@ -135,7 +134,6 @@ void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, const pmu_hp_sys
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#endif
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REG_SET_FIELD(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_OCODE, ulp_ocode);
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SET_PERI_REG_MASK(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_FORCE_OCODE);
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#endif
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}
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void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, const pmu_lp_system_param_t *param)
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@@ -99,8 +99,6 @@ if(target STREQUAL "linux")
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else()
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if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
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target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.eco5.ld")
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elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.beta5.ld")
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else()
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target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld")
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endif()
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@@ -114,8 +112,6 @@ else()
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if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB)
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if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
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rom_linker_script("eco5.libgcc")
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elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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rom_linker_script("beta5.libgcc")
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else()
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rom_linker_script("libgcc")
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endif()
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@@ -131,11 +127,7 @@ endif()
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# Common API which is linked both for bootloader and app builds
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if(CONFIG_HAL_SYSTIMER_USE_ROM_IMPL)
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if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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rom_linker_script("beta5.systimer")
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else()
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rom_linker_script("systimer")
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endif()
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rom_linker_script("systimer")
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endif()
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if(CONFIG_ESP_ROM_HAS_VERSION)
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@@ -169,8 +161,6 @@ if(BOOTLOADER_BUILD)
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else()
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if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
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rom_linker_script("eco5.libc")
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elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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rom_linker_script("beta5.libc")
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else()
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rom_linker_script("libc")
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endif()
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@@ -181,8 +171,6 @@ if(BOOTLOADER_BUILD)
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if(CONFIG_LIBC_NEWLIB)
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if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
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rom_linker_script("eco5.newlib")
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elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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rom_linker_script("beta5.newlib")
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else()
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rom_linker_script("newlib")
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endif()
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@@ -340,8 +328,6 @@ else() # Regular app build
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# ESP32 and S2 are a bit different, keep them as special cases in the target specific include section
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if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
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rom_linker_script("eco5.libc")
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elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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rom_linker_script("beta5.libc")
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else()
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rom_linker_script("libc")
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endif()
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@@ -351,8 +337,6 @@ else() # Regular app build
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if(CONFIG_LIBC_NEWLIB)
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if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
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rom_linker_script("eco5.newlib")
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elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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rom_linker_script("beta5.newlib")
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else()
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rom_linker_script("newlib")
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endif()
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@@ -362,11 +346,7 @@ else() # Regular app build
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if(NOT CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME AND NOT CONFIG_ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG)
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# Newlib-nano functions contains time_t related functions
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# and cannot be used if they were compiled with 32 bit time_t
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if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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rom_linker_script("beta5.newlib-nano")
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else()
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rom_linker_script("newlib-nano")
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endif()
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rom_linker_script("newlib-nano")
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endif()
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endif()
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@@ -388,21 +368,13 @@ else() # Regular app build
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target_link_libraries(${COMPONENT_LIB} PRIVATE "-u esp_rom_include_multi_heap_patch")
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endif()
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if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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rom_linker_script("beta5.heap")
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else()
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rom_linker_script("heap")
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endif()
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rom_linker_script("heap")
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endif()
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if(CONFIG_SPI_FLASH_ROM_IMPL)
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# Older targets do not have a separate ld file for spiflash
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if(NOT target STREQUAL "esp32c3" AND NOT target STREQUAL "esp32s3" AND NOT target STREQUAL "esp32c2")
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if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
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rom_linker_script("beta5.spiflash")
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else()
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rom_linker_script("spiflash")
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endif()
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rom_linker_script("spiflash")
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endif()
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endif()
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@@ -1,79 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ROM function interface esp32h4.rom.heap.ld for esp32h4
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*
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*
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* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
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*
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* Compatible with ROM where ECO version equal or greater to 0.
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*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*/
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/***************************************
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Group heap
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***************************************/
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/* Functions */
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tlsf_create = 0x400003d8;
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tlsf_create_with_pool = 0x400003dc;
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tlsf_get_pool = 0x400003e0;
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tlsf_add_pool = 0x400003e4;
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tlsf_remove_pool = 0x400003e8;
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tlsf_malloc = 0x400003ec;
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tlsf_memalign = 0x400003f0;
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tlsf_memalign_offs = 0x400003f4;
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tlsf_malloc_addr = 0x400003f8;
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tlsf_realloc = 0x400003fc;
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tlsf_free = 0x40000400;
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tlsf_block_size = 0x40000404;
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tlsf_size = 0x40000408;
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tlsf_pool_overhead = 0x4000040c;
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tlsf_alloc_overhead = 0x40000410;
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tlsf_walk_pool = 0x40000414;
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tlsf_check = 0x40000418;
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tlsf_check_pool = 0x4000041c;
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tlsf_poison_fill_pfunc_set = 0x40000420;
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tlsf_poison_check_pfunc_set = 0x40000424;
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multi_heap_get_block_address_impl = 0x40000428;
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multi_heap_get_allocated_size_impl = 0x4000042c;
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multi_heap_register_impl = 0x40000430;
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multi_heap_set_lock = 0x40000434;
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multi_heap_os_funcs_init = 0x40000438;
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multi_heap_internal_lock = 0x4000043c;
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multi_heap_internal_unlock = 0x40000440;
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multi_heap_get_first_block = 0x40000444;
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multi_heap_get_next_block = 0x40000448;
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multi_heap_is_free = 0x4000044c;
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multi_heap_malloc_impl = 0x40000450;
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multi_heap_free_impl = 0x40000454;
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multi_heap_realloc_impl = 0x40000458;
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multi_heap_aligned_alloc_impl_offs = 0x4000045c;
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multi_heap_aligned_alloc_impl = 0x40000460;
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multi_heap_check = 0x40000464;
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multi_heap_dump = 0x40000468;
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multi_heap_free_size_impl = 0x4000046c;
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multi_heap_minimum_free_size_impl = 0x40000470;
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multi_heap_get_info_impl = 0x40000474;
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/* Data (.data, .bss, .rodata) */
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heap_tlsf_table_ptr = 0x4085ffd4;
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PROVIDE (multi_heap_malloc = multi_heap_malloc_impl);
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PROVIDE (multi_heap_free = multi_heap_free_impl);
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PROVIDE (multi_heap_realloc = multi_heap_realloc_impl);
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PROVIDE (multi_heap_get_allocated_size = multi_heap_get_allocated_size_impl);
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PROVIDE (multi_heap_register = multi_heap_register_impl);
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PROVIDE (multi_heap_get_info = multi_heap_get_info_impl);
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PROVIDE (multi_heap_free_size = multi_heap_free_size_impl);
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PROVIDE (multi_heap_minimum_free_size = multi_heap_minimum_free_size_impl);
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PROVIDE (multi_heap_get_block_address = multi_heap_get_block_address_impl);
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PROVIDE (multi_heap_aligned_alloc = multi_heap_aligned_alloc_impl);
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PROVIDE (multi_heap_aligned_free = multi_heap_aligned_free_impl);
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PROVIDE (multi_heap_check = multi_heap_check);
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PROVIDE (multi_heap_set_lock = multi_heap_set_lock);
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PROVIDE (multi_heap_os_funcs_init = multi_heap_mutex_init);
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PROVIDE (multi_heap_internal_lock = multi_heap_internal_lock);
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PROVIDE (multi_heap_internal_unlock = multi_heap_internal_unlock);
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@@ -1,404 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ROM function interface esp32h4.rom.ld for esp32h4
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*
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*
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* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
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*
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* Compatible with ROM where ECO version equal or greater to 0.
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*
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* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
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*/
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/***************************************
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Group common
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***************************************/
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/* Functions */
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rtc_get_reset_reason = 0x40000018;
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rtc_get_wakeup_cause = 0x4000001c;
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pmu_enable_unhold_pads = 0x40000020;
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ets_printf = 0x40000024;
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ets_install_putc1 = 0x40000028;
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ets_install_putc2 = 0x4000002c;
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ets_install_uart_printf = 0x40000030;
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ets_install_usb_printf = 0x40000034;
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ets_get_printf_channel = 0x40000038;
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ets_delay_us = 0x4000003c;
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ets_get_cpu_frequency = 0x40000040;
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ets_update_cpu_frequency = 0x40000044;
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ets_install_lock = 0x40000048;
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UartRxString = 0x4000004c;
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UartGetCmdLn = 0x40000050;
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uart_tx_one_char = 0x40000054;
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uart_tx_one_char2 = 0x40000058;
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uart_tx_one_char3 = 0x4000005c;
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uart_rx_one_char = 0x40000060;
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uart_rx_one_char_block = 0x40000064;
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uart_rx_intr_handler = 0x40000068;
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uart_rx_readbuff = 0x4000006c;
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uartAttach = 0x40000070;
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uart_tx_flush = 0x40000074;
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uart_tx_wait_idle = 0x40000078;
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uart_div_modify = 0x4000007c;
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ets_write_char_uart = 0x40000080;
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uart_tx_switch = 0x40000084;
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uart_buff_switch = 0x40000088;
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roundup2 = 0x4000008c;
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multofup = 0x40000090;
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software_reset = 0x40000094;
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software_reset_cpu = 0x40000098;
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ets_clk_assist_debug_clock_enable = 0x4000009c;
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clear_super_wdt_reset_flag = 0x400000a0;
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disable_default_watchdog = 0x400000a4;
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ets_set_appcpu_boot_addr = 0x400000a8;
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send_packet = 0x400000ac;
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recv_packet = 0x400000b0;
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GetUartDevice = 0x400000b4;
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UartDwnLdProc = 0x400000b8;
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GetSecurityInfoProc = 0x400000bc;
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Uart_Init = 0x400000c0;
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ets_set_user_start = 0x400000c4;
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/* Data (.data, .bss, .rodata) */
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ets_rom_layout_p = 0x4001fffc;
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ets_ops_table_ptr = 0x4085fff4;
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g_saved_pc = 0x4085fff8;
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/***************************************
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Group miniz
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***************************************/
|
||||
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/* Functions */
|
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mz_adler32 = 0x400000c8;
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mz_free = 0x400000cc;
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tdefl_compress = 0x400000d0;
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tdefl_compress_buffer = 0x400000d4;
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tdefl_compress_mem_to_heap = 0x400000d8;
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tdefl_compress_mem_to_mem = 0x400000dc;
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tdefl_compress_mem_to_output = 0x400000e0;
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tdefl_get_adler32 = 0x400000e4;
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tdefl_get_prev_return_status = 0x400000e8;
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tdefl_init = 0x400000ec;
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tdefl_write_image_to_png_file_in_memory = 0x400000f0;
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tdefl_write_image_to_png_file_in_memory_ex = 0x400000f4;
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tinfl_decompress = 0x400000f8;
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tinfl_decompress_mem_to_callback = 0x400000fc;
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tinfl_decompress_mem_to_heap = 0x40000100;
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tinfl_decompress_mem_to_mem = 0x40000104;
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/***************************************
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Group spi_extmem_common
|
||||
***************************************/
|
||||
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/* Functions */
|
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esp_rom_spi_cmd_config = 0x40000108;
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esp_rom_spi_cmd_start = 0x4000010c;
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esp_rom_spi_set_op_mode = 0x40000110;
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|
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/***************************************
|
||||
Group spiflash_legacy
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
esp_rom_spiflash_wait_idle = 0x40000114;
|
||||
esp_rom_spiflash_write_encrypted = 0x40000118;
|
||||
esp_rom_spiflash_write_encrypted_dest = 0x4000011c;
|
||||
esp_rom_spiflash_write_encrypted_enable = 0x40000120;
|
||||
esp_rom_spiflash_write_encrypted_disable = 0x40000124;
|
||||
esp_rom_spiflash_erase_chip = 0x40000128;
|
||||
_esp_rom_spiflash_erase_sector = 0x4000012c;
|
||||
_esp_rom_spiflash_erase_block = 0x40000130;
|
||||
_esp_rom_spiflash_write = 0x40000134;
|
||||
_esp_rom_spiflash_read = 0x40000138;
|
||||
_esp_rom_spiflash_unlock = 0x4000013c;
|
||||
_SPIEraseArea = 0x40000140;
|
||||
_SPI_write_enable = 0x40000144;
|
||||
esp_rom_spiflash_erase_sector = 0x40000148;
|
||||
esp_rom_spiflash_erase_block = 0x4000014c;
|
||||
esp_rom_spiflash_write = 0x40000150;
|
||||
esp_rom_spiflash_read = 0x40000154;
|
||||
esp_rom_spiflash_unlock = 0x40000158;
|
||||
SPIEraseArea = 0x4000015c;
|
||||
SPI_write_enable = 0x40000160;
|
||||
esp_rom_spiflash_config_param = 0x40000164;
|
||||
esp_rom_spiflash_read_user_cmd = 0x40000168;
|
||||
esp_rom_spiflash_select_qio_pins = 0x4000016c;
|
||||
esp_rom_spi_flash_auto_sus_res = 0x40000170;
|
||||
esp_rom_spi_flash_send_resume = 0x40000174;
|
||||
esp_rom_spi_flash_update_id = 0x40000178;
|
||||
esp_rom_spiflash_config_clk = 0x4000017c;
|
||||
esp_rom_spiflash_config_readmode = 0x40000180;
|
||||
esp_rom_spiflash_read_status = 0x40000184;
|
||||
esp_rom_spiflash_read_statushigh = 0x40000188;
|
||||
esp_rom_spiflash_write_status = 0x4000018c;
|
||||
esp_rom_spiflash_write_disable = 0x40000190;
|
||||
spi_cache_mode_switch = 0x40000194;
|
||||
spi_common_set_dummy_output = 0x40000198;
|
||||
spi_common_set_flash_cs_timing = 0x4000019c;
|
||||
esp_rom_spi_set_address_bit_len = 0x400001a0;
|
||||
SPILock = 0x400001a4;
|
||||
SPIMasterReadModeCnfig = 0x400001a8;
|
||||
SPI_Common_Command = 0x400001ac;
|
||||
SPI_WakeUp = 0x400001b0;
|
||||
SPI_block_erase = 0x400001b4;
|
||||
SPI_chip_erase = 0x400001b8;
|
||||
SPI_init = 0x400001bc;
|
||||
SPI_page_program = 0x400001c0;
|
||||
SPI_read_data = 0x400001c4;
|
||||
SPI_sector_erase = 0x400001c8;
|
||||
SelectSpiFunction = 0x400001cc;
|
||||
SetSpiDrvs = 0x400001d0;
|
||||
Wait_SPI_Idle = 0x400001d4;
|
||||
spi_dummy_len_fix = 0x400001d8;
|
||||
Disable_QMode = 0x400001dc;
|
||||
Enable_QMode = 0x400001e0;
|
||||
spi_flash_attach = 0x400001e4;
|
||||
spi_flash_get_chip_size = 0x400001e8;
|
||||
spi_flash_guard_set = 0x400001ec;
|
||||
spi_flash_guard_get = 0x400001f0;
|
||||
spi_flash_read_encrypted = 0x400001f4;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
rom_spiflash_legacy_funcs = 0x4085ffec;
|
||||
rom_spiflash_legacy_data = 0x4085ffe8;
|
||||
g_flash_guard_ops = 0x4085fff0;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group cache
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
Cache_Get_Line_Size = 0x400005d8;
|
||||
Cache_Get_Mode = 0x400005dc;
|
||||
Cache_Address_Through_Cache = 0x400005e0;
|
||||
ROM_Boot_Cache_Init = 0x400005e4;
|
||||
Cache_Sync_Items = 0x400005e8;
|
||||
Cache_Op_Addr = 0x400005ec;
|
||||
Cache_Invalidate_Addr = 0x400005f0;
|
||||
Cache_Clean_Addr = 0x400005f4;
|
||||
Cache_WriteBack_Addr = 0x400005f8;
|
||||
Cache_WriteBack_Invalidate_Addr = 0x400005fc;
|
||||
Cache_Invalidate_All = 0x40000600;
|
||||
Cache_Clean_All = 0x40000604;
|
||||
Cache_WriteBack_All = 0x40000608;
|
||||
Cache_WriteBack_Invalidate_All = 0x4000060c;
|
||||
Cache_Mask_All = 0x40000610;
|
||||
Cache_UnMask_Dram0 = 0x40000614;
|
||||
Cache_Suspend_Autoload = 0x40000618;
|
||||
Cache_Resume_Autoload = 0x4000061c;
|
||||
Cache_Start_Preload = 0x40000620;
|
||||
Cache_Preload_Done = 0x40000624;
|
||||
Cache_End_Preload = 0x40000628;
|
||||
Cache_Config_Autoload = 0x4000062c;
|
||||
Cache_Enable_Autoload = 0x40000630;
|
||||
Cache_Disable_Autoload = 0x40000634;
|
||||
Cache_Enable_PreLock = 0x40000638;
|
||||
Cache_Disable_PreLock = 0x4000063c;
|
||||
Cache_Lock_Items = 0x40000640;
|
||||
Cache_Lock_Addr = 0x40000644;
|
||||
Cache_Unlock_Addr = 0x40000648;
|
||||
Cache_Disable_Cache = 0x4000064c;
|
||||
Cache_Enable_Cache = 0x40000650;
|
||||
Cache_Suspend_Cache = 0x40000654;
|
||||
Cache_Resume_Cache = 0x40000658;
|
||||
Cache_Freeze_Enable = 0x4000065c;
|
||||
Cache_Freeze_Disable = 0x40000660;
|
||||
Cache_Set_IDROM_MMU_Size = 0x40000664;
|
||||
Cache_Get_IROM_MMU_End = 0x40000668;
|
||||
Cache_Get_DROM_MMU_End = 0x4000066c;
|
||||
Cache_MMU_Init = 0x40000670;
|
||||
Cache_MSPI_MMU_Set = 0x40000674;
|
||||
Cache_MSPI_MMU_Set_Secure = 0x40000678;
|
||||
Cache_Count_Flash_Pages = 0x4000067c;
|
||||
Cache_Travel_Tag_Memory = 0x40000680;
|
||||
Cache_Get_Virtual_Addr = 0x40000684;
|
||||
flash2spiram_instruction_offset = 0x40000688;
|
||||
flash2spiram_rodata_offset = 0x4000068c;
|
||||
flash_instr_rodata_start_page = 0x40000690;
|
||||
flash_instr_rodata_end_page = 0x40000694;
|
||||
Cache_Set_IDROM_MMU_Info = 0x40000698;
|
||||
Cache_Flash_To_SPIRAM_Copy = 0x4000069c;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
rom_cache_op_cb = 0x4085ffc8;
|
||||
rom_cache_internal_table_ptr = 0x4085ffc4;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group clock
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
ets_clk_get_xtal_freq = 0x400006a0;
|
||||
ets_clk_get_cpu_freq = 0x400006a4;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group gpio
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
rom_gpio_set_output_level = 0x400006a8;
|
||||
rom_gpio_get_input_level = 0x400006ac;
|
||||
rom_gpio_matrix_in = 0x400006b0;
|
||||
rom_gpio_matrix_out = 0x400006b4;
|
||||
rom_gpio_bypass_matrix_in = 0x400006b8;
|
||||
rom_gpio_output_disable = 0x400006bc;
|
||||
rom_gpio_output_enable = 0x400006c0;
|
||||
rom_gpio_pad_input_disable = 0x400006c4;
|
||||
rom_gpio_pad_input_enable = 0x400006c8;
|
||||
rom_gpio_pad_pulldown = 0x400006cc;
|
||||
rom_gpio_pad_pullup = 0x400006d0;
|
||||
rom_gpio_pad_select_gpio = 0x400006d4;
|
||||
rom_gpio_pad_set_drv = 0x400006d8;
|
||||
rom_gpio_pad_unhold = 0x400006dc;
|
||||
rom_gpio_pad_hold = 0x400006e0;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group interrupts
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
esprv_intc_int_set_priority = 0x400006e4;
|
||||
esprv_intc_int_set_threshold = 0x400006e8;
|
||||
esprv_intc_int_enable = 0x400006ec;
|
||||
esprv_intc_int_disable = 0x400006f0;
|
||||
esprv_intc_int_set_type = 0x400006f4;
|
||||
PROVIDE( intr_handler_set = 0x400006f8 );
|
||||
intr_matrix_set = 0x400006fc;
|
||||
ets_intr_register_ctx = 0x40000700;
|
||||
ets_intr_lock = 0x40000704;
|
||||
ets_intr_unlock = 0x40000708;
|
||||
ets_isr_attach = 0x4000070c;
|
||||
ets_isr_mask = 0x40000710;
|
||||
ets_isr_unmask = 0x40000714;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group crc
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
crc32_le = 0x40000718;
|
||||
crc16_le = 0x4000071c;
|
||||
crc8_le = 0x40000720;
|
||||
crc32_be = 0x40000724;
|
||||
crc16_be = 0x40000728;
|
||||
crc8_be = 0x4000072c;
|
||||
esp_crc8 = 0x40000730;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
crc32_le_table_ptr = 0x4001fff8;
|
||||
crc16_le_table_ptr = 0x4001fff4;
|
||||
crc8_le_table_ptr = 0x4001fff0;
|
||||
crc32_be_table_ptr = 0x4001ffec;
|
||||
crc16_be_table_ptr = 0x4001ffe8;
|
||||
crc8_be_table_ptr = 0x4001ffe4;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group md5
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
md5_vector = 0x40000734;
|
||||
MD5Init = 0x40000738;
|
||||
MD5Update = 0x4000073c;
|
||||
MD5Final = 0x40000740;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group hwcrypto
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
ets_sha_enable = 0x40000744;
|
||||
ets_sha_disable = 0x40000748;
|
||||
ets_sha_get_state = 0x4000074c;
|
||||
ets_sha_init = 0x40000750;
|
||||
ets_sha_process = 0x40000754;
|
||||
ets_sha_starts = 0x40000758;
|
||||
ets_sha_update = 0x4000075c;
|
||||
ets_sha_finish = 0x40000760;
|
||||
ets_sha_clone = 0x40000764;
|
||||
ets_hmac_enable = 0x40000768;
|
||||
ets_hmac_disable = 0x4000076c;
|
||||
ets_hmac_calculate_message = 0x40000770;
|
||||
ets_hmac_calculate_downstream = 0x40000774;
|
||||
ets_hmac_invalidate_downstream = 0x40000778;
|
||||
ets_aes_enable = 0x4000077c;
|
||||
ets_aes_disable = 0x40000780;
|
||||
ets_aes_setkey = 0x40000784;
|
||||
ets_aes_block = 0x40000788;
|
||||
ets_aes_setkey_dec = 0x4000078c;
|
||||
ets_aes_setkey_enc = 0x40000790;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group efuse
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
ets_efuse_read = 0x40000794;
|
||||
ets_efuse_program = 0x40000798;
|
||||
ets_efuse_clear_program_registers = 0x4000079c;
|
||||
ets_efuse_write_key = 0x400007a0;
|
||||
ets_efuse_get_read_register_address = 0x400007a4;
|
||||
ets_efuse_get_key_purpose = 0x400007a8;
|
||||
ets_efuse_key_block_unused = 0x400007ac;
|
||||
ets_efuse_find_unused_key_block = 0x400007b0;
|
||||
ets_efuse_rs_calculate = 0x400007b4;
|
||||
ets_efuse_count_unused_key_blocks = 0x400007b8;
|
||||
ets_efuse_secure_boot_enabled = 0x400007bc;
|
||||
ets_efuse_secure_boot_aggressive_revoke_enabled = 0x400007c0;
|
||||
ets_efuse_cache_encryption_enabled = 0x400007c4;
|
||||
ets_efuse_download_modes_disabled = 0x400007c8;
|
||||
ets_efuse_find_purpose = 0x400007cc;
|
||||
ets_efuse_force_send_resume = 0x400007d0;
|
||||
ets_efuse_get_flash_delay_us = 0x400007d4;
|
||||
ets_efuse_get_uart_print_control = 0x400007d8;
|
||||
ets_efuse_direct_boot_mode_disabled = 0x400007dc;
|
||||
ets_efuse_security_download_modes_enabled = 0x400007e0;
|
||||
ets_efuse_jtag_disabled = 0x400007e4;
|
||||
ets_efuse_usb_print_is_disabled = 0x400007e8;
|
||||
ets_efuse_usb_download_mode_disabled = 0x400007ec;
|
||||
ets_efuse_usb_device_disabled = 0x400007f0;
|
||||
ets_jtag_enable_temporarily = 0x400007f4;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group key_mgr
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
esp_rom_check_recover_key = 0x400007f8;
|
||||
esp_rom_km_huk_conf = 0x400007fc;
|
||||
esp_rom_km_huk_risk = 0x40000800;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group secureboot
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
ets_ecdsa_verify = 0x40000804;
|
||||
ets_secure_boot_verify_bootloader_with_keys = 0x40000808;
|
||||
ets_secure_boot_verify_signature = 0x4000080c;
|
||||
ets_secure_boot_read_key_digests = 0x40000810;
|
||||
ets_secure_boot_revoke_public_key_digest = 0x40000814;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group usb_device_uart
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
usb_serial_device_rx_one_char = 0x40000944;
|
||||
usb_serial_device_rx_one_char_block = 0x40000948;
|
||||
usb_serial_device_tx_flush = 0x4000094c;
|
||||
usb_serial_device_tx_one_char = 0x40000950;
|
||||
@@ -1,65 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
esp_rom_newlib_init_common_mutexes = 0x40000478;
|
||||
memset = 0x4000047c;
|
||||
memcpy = 0x40000480;
|
||||
memmove = 0x40000484;
|
||||
memcmp = 0x40000488;
|
||||
strcpy = 0x4000048c;
|
||||
strncpy = 0x40000490;
|
||||
strcmp = 0x40000494;
|
||||
strncmp = 0x40000498;
|
||||
strlen = 0x4000049c;
|
||||
strstr = 0x400004a0;
|
||||
bzero = 0x400004a4;
|
||||
sbrk = 0x400004ac;
|
||||
isalnum = 0x400004b0;
|
||||
isalpha = 0x400004b4;
|
||||
isascii = 0x400004b8;
|
||||
isblank = 0x400004bc;
|
||||
iscntrl = 0x400004c0;
|
||||
isdigit = 0x400004c4;
|
||||
islower = 0x400004c8;
|
||||
isgraph = 0x400004cc;
|
||||
isprint = 0x400004d0;
|
||||
ispunct = 0x400004d4;
|
||||
isspace = 0x400004d8;
|
||||
isupper = 0x400004dc;
|
||||
toupper = 0x400004e0;
|
||||
tolower = 0x400004e4;
|
||||
toascii = 0x400004e8;
|
||||
memccpy = 0x400004ec;
|
||||
memchr = 0x400004f0;
|
||||
memrchr = 0x400004f4;
|
||||
strcasecmp = 0x400004f8;
|
||||
strcasestr = 0x400004fc;
|
||||
strcat = 0x40000500;
|
||||
strchr = 0x40000508;
|
||||
strcspn = 0x4000050c;
|
||||
strcoll = 0x40000510;
|
||||
strlcat = 0x40000514;
|
||||
strlcpy = 0x40000518;
|
||||
strlwr = 0x4000051c;
|
||||
strncasecmp = 0x40000520;
|
||||
strncat = 0x40000524;
|
||||
strnlen = 0x4000052c;
|
||||
strrchr = 0x40000530;
|
||||
strsep = 0x40000534;
|
||||
strspn = 0x40000538;
|
||||
strtok_r = 0x4000053c;
|
||||
strupr = 0x40000540;
|
||||
longjmp = 0x40000544;
|
||||
setjmp = 0x40000548;
|
||||
abs = 0x4000054c;
|
||||
div = 0x40000550;
|
||||
labs = 0x40000554;
|
||||
ldiv = 0x40000558;
|
||||
qsort = 0x4000055c;
|
||||
utoa = 0x4000056c;
|
||||
itoa = 0x40000570;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
syscall_table_ptr = 0x4085ffd0;
|
||||
_global_impure_ptr = 0x4085ffcc;
|
||||
@@ -1,95 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM function interface esp32h4.rom.libgcc.ld for esp32h4
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group libgccdf
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
__absvdi2 = 0x40000818;
|
||||
__absvsi2 = 0x4000081c;
|
||||
__adddf3 = 0x40000820;
|
||||
__addvdi3 = 0x40000824;
|
||||
__addvsi3 = 0x40000828;
|
||||
__ashldi3 = 0x4000082c;
|
||||
__ashrdi3 = 0x40000830;
|
||||
__bswapdi2 = 0x40000834;
|
||||
__bswapsi2 = 0x40000838;
|
||||
__clear_cache = 0x4000083c;
|
||||
__clrsbdi2 = 0x40000840;
|
||||
__clrsbsi2 = 0x40000844;
|
||||
__clzdi2 = 0x40000848;
|
||||
__clzsi2 = 0x4000084c;
|
||||
__cmpdi2 = 0x40000850;
|
||||
__ctzdi2 = 0x40000854;
|
||||
__ctzsi2 = 0x40000858;
|
||||
__divdc3 = 0x4000085c;
|
||||
__divdf3 = 0x40000860;
|
||||
__divdi3 = 0x40000864;
|
||||
__divsc3 = 0x40000868;
|
||||
__divsi3 = 0x4000086c;
|
||||
__eqdf2 = 0x40000870;
|
||||
__extendsfdf2 = 0x40000874;
|
||||
__ffsdi2 = 0x40000878;
|
||||
__ffssi2 = 0x4000087c;
|
||||
__fixdfdi = 0x40000880;
|
||||
__fixdfsi = 0x40000884;
|
||||
__fixsfdi = 0x40000888;
|
||||
__fixunsdfsi = 0x4000088c;
|
||||
__fixunssfdi = 0x40000890;
|
||||
__fixunssfsi = 0x40000894;
|
||||
__floatdidf = 0x40000898;
|
||||
__floatdisf = 0x4000089c;
|
||||
__floatsidf = 0x400008a0;
|
||||
__floatundidf = 0x400008a4;
|
||||
__floatundisf = 0x400008a8;
|
||||
__floatunsidf = 0x400008ac;
|
||||
__gcc_bcmp = 0x400008b0;
|
||||
__gedf2 = 0x400008b4;
|
||||
__gtdf2 = 0x400008b8;
|
||||
__ledf2 = 0x400008bc;
|
||||
__lshrdi3 = 0x400008c0;
|
||||
__ltdf2 = 0x400008c4;
|
||||
__moddi3 = 0x400008c8;
|
||||
__modsi3 = 0x400008cc;
|
||||
__muldc3 = 0x400008d0;
|
||||
__muldf3 = 0x400008d4;
|
||||
__muldi3 = 0x400008d8;
|
||||
__mulsc3 = 0x400008dc;
|
||||
__mulsi3 = 0x400008e0;
|
||||
__mulvdi3 = 0x400008e4;
|
||||
__mulvsi3 = 0x400008e8;
|
||||
__nedf2 = 0x400008ec;
|
||||
__negdf2 = 0x400008f0;
|
||||
__negdi2 = 0x400008f4;
|
||||
__negvdi2 = 0x400008f8;
|
||||
__negvsi2 = 0x400008fc;
|
||||
__paritysi2 = 0x40000900;
|
||||
__popcountdi2 = 0x40000904;
|
||||
__popcountsi2 = 0x40000908;
|
||||
__powidf2 = 0x4000090c;
|
||||
__subdf3 = 0x40000910;
|
||||
__subvdi3 = 0x40000914;
|
||||
__subvsi3 = 0x40000918;
|
||||
__ucmpdi2 = 0x4000091c;
|
||||
__udivdi3 = 0x40000920;
|
||||
__udivmoddi4 = 0x40000924;
|
||||
__udivsi3 = 0x40000928;
|
||||
__udiv_w_sdiv = 0x4000092c;
|
||||
__umoddi3 = 0x40000930;
|
||||
__umodsi3 = 0x40000934;
|
||||
__unorddf2 = 0x40000938;
|
||||
__extenddftf2 = 0x4000093c;
|
||||
__trunctfdf2 = 0x40000940;
|
||||
@@ -1,32 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM function interface esp32h4.rom.newlib-nano.ld for esp32h4
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group newlib_nano_format
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
__sprint_r = 0x400005a8;
|
||||
_fiprintf_r = 0x400005ac;
|
||||
_fprintf_r = 0x400005b0;
|
||||
_printf_common = 0x400005b4;
|
||||
_printf_i = 0x400005b8;
|
||||
_vfiprintf_r = 0x400005bc;
|
||||
_vfprintf_r = 0x400005c0;
|
||||
fiprintf = 0x400005c4;
|
||||
fprintf = 0x400005c8;
|
||||
printf = 0x400005cc;
|
||||
vfiprintf = 0x400005d0;
|
||||
vfprintf = 0x400005d4;
|
||||
@@ -1,41 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM function interface esp32h4.rom.newlib.ld for esp32h4
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. !!! BUT EDITED !!!
|
||||
* The file was originally generated for use with newlib, but it was split into
|
||||
* multiple files to make it compatible with picolibc.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group newlib
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
_isatty_r = 0x400004a8;
|
||||
strdup = 0x40000504;
|
||||
strndup = 0x40000528;
|
||||
rand_r = 0x40000560;
|
||||
rand = 0x40000564;
|
||||
srand = 0x40000568;
|
||||
atoi = 0x40000574;
|
||||
atol = 0x40000578;
|
||||
strtol = 0x4000057c;
|
||||
strtoul = 0x40000580;
|
||||
fflush = 0x40000584;
|
||||
_fflush_r = 0x40000588;
|
||||
_fwalk = 0x4000058c;
|
||||
_fwalk_reent = 0x40000590;
|
||||
__smakebuf_r = 0x40000594;
|
||||
__swhatbuf_r = 0x40000598;
|
||||
__swbuf_r = 0x4000059c;
|
||||
__swbuf = 0x400005a0;
|
||||
__swsetup_r = 0x400005a4;
|
||||
@@ -1,148 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
/* ROM function interface esp32h4.rom.spiflash.ld for esp32h4
|
||||
*
|
||||
*
|
||||
* Generated from ./target/esp32h4/interface-esp32h4.yml md5sum 14f04fa4b1cf69c4e6eec57d641026c4
|
||||
*
|
||||
* Compatible with ROM where ECO version equal or greater to 0.
|
||||
*
|
||||
* THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group spi_flash_cache
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
spi_flash_disable_cache = 0x400001f8;
|
||||
spi_flash_restore_cache = 0x400001fc;
|
||||
spi_flash_cache_enabled = 0x40000200;
|
||||
spi_flash_enable_cache = 0x40000204;
|
||||
esp_enable_cache_flash_wrap = 0x40000208;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group esp_flash
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
esp_flash_chip_driver_initialized = 0x4000020c;
|
||||
esp_flash_read_id = 0x40000210;
|
||||
esp_flash_get_size = 0x40000214;
|
||||
esp_flash_erase_chip = 0x40000218;
|
||||
rom_esp_flash_erase_region = 0x4000021c;
|
||||
esp_flash_get_chip_write_protect = 0x40000220;
|
||||
esp_flash_set_chip_write_protect = 0x40000224;
|
||||
esp_flash_get_protectable_regions = 0x40000228;
|
||||
esp_flash_get_protected_region = 0x4000022c;
|
||||
esp_flash_set_protected_region = 0x40000230;
|
||||
esp_flash_read = 0x40000234;
|
||||
rom_esp_flash_write = 0x40000238;
|
||||
rom_esp_flash_write_encrypted = 0x4000023c;
|
||||
esp_flash_read_encrypted = 0x40000240;
|
||||
esp_flash_get_io_mode = 0x40000244;
|
||||
esp_flash_set_io_mode = 0x40000248;
|
||||
spi_flash_boot_attach = 0x4000024c;
|
||||
esp_flash_read_chip_id = 0x40000250;
|
||||
detect_spi_flash_chip = 0x40000254;
|
||||
esp_flash_suspend_cmd_init = 0x40000258;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
esp_flash_default_chip = 0x4085ffe4;
|
||||
esp_flash_api_funcs = 0x4085ffe0;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group spi_flash_chips
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
spi_flash_chip_generic_probe = 0x4000025c;
|
||||
spi_flash_chip_generic_detect_size = 0x40000260;
|
||||
spi_flash_chip_generic_write = 0x40000264;
|
||||
spi_flash_chip_generic_write_encrypted = 0x40000268;
|
||||
spi_flash_chip_generic_set_write_protect = 0x4000026c;
|
||||
spi_flash_common_write_status_16b_wrsr = 0x40000270;
|
||||
spi_flash_chip_generic_reset = 0x40000274;
|
||||
spi_flash_chip_generic_erase_chip = 0x40000278;
|
||||
spi_flash_chip_generic_erase_sector = 0x4000027c;
|
||||
spi_flash_chip_generic_erase_block = 0x40000280;
|
||||
spi_flash_chip_generic_page_program = 0x40000284;
|
||||
spi_flash_chip_generic_get_write_protect = 0x40000288;
|
||||
spi_flash_common_read_status_16b_rdsr_rdsr2 = 0x4000028c;
|
||||
spi_flash_chip_generic_read_reg = 0x40000290;
|
||||
spi_flash_chip_generic_yield = 0x40000294;
|
||||
spi_flash_generic_wait_host_idle = 0x40000298;
|
||||
spi_flash_chip_generic_wait_idle = 0x4000029c;
|
||||
spi_flash_chip_generic_config_host_io_mode = 0x400002a0;
|
||||
spi_flash_chip_generic_read = 0x400002a4;
|
||||
spi_flash_common_read_status_8b_rdsr2 = 0x400002a8;
|
||||
spi_flash_chip_generic_get_io_mode = 0x400002ac;
|
||||
spi_flash_common_read_status_8b_rdsr = 0x400002b0;
|
||||
spi_flash_common_write_status_8b_wrsr = 0x400002b4;
|
||||
spi_flash_common_write_status_8b_wrsr2 = 0x400002b8;
|
||||
spi_flash_common_set_io_mode = 0x400002bc;
|
||||
spi_flash_chip_generic_set_io_mode = 0x400002c0;
|
||||
spi_flash_chip_generic_read_unique_id = 0x400002c4;
|
||||
spi_flash_chip_generic_get_caps = 0x400002c8;
|
||||
spi_flash_chip_generic_suspend_cmd_conf = 0x400002cc;
|
||||
spi_flash_chip_gd_get_io_mode = 0x400002d0;
|
||||
spi_flash_chip_gd_probe = 0x400002d4;
|
||||
spi_flash_chip_gd_set_io_mode = 0x400002d8;
|
||||
/* Data (.data, .bss, .rodata) */
|
||||
spi_flash_chip_generic_config_data = 0x4085ffdc;
|
||||
spi_flash_encryption = 0x4085ffd8;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group memspi_host
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
memspi_host_read_id_hs = 0x400002dc;
|
||||
memspi_host_read_status_hs = 0x400002e0;
|
||||
memspi_host_flush_cache = 0x400002e4;
|
||||
memspi_host_erase_chip = 0x400002e8;
|
||||
memspi_host_erase_sector = 0x400002ec;
|
||||
memspi_host_erase_block = 0x400002f0;
|
||||
memspi_host_program_page = 0x400002f4;
|
||||
memspi_host_read = 0x400002f8;
|
||||
memspi_host_set_write_protect = 0x400002fc;
|
||||
memspi_host_set_max_read_len = 0x40000300;
|
||||
memspi_host_read_data_slicer = 0x40000304;
|
||||
memspi_host_write_data_slicer = 0x40000308;
|
||||
|
||||
|
||||
/***************************************
|
||||
Group hal_spiflash
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
spi_flash_hal_poll_cmd_done = 0x4000030c;
|
||||
spi_flash_hal_device_config = 0x40000310;
|
||||
spi_flash_hal_configure_host_io_mode = 0x40000314;
|
||||
spi_flash_hal_common_command = 0x40000318;
|
||||
spi_flash_hal_read = 0x4000031c;
|
||||
spi_flash_hal_erase_chip = 0x40000320;
|
||||
spi_flash_hal_erase_sector = 0x40000324;
|
||||
spi_flash_hal_erase_block = 0x40000328;
|
||||
spi_flash_hal_program_page = 0x4000032c;
|
||||
spi_flash_hal_set_write_protect = 0x40000330;
|
||||
spi_flash_hal_host_idle = 0x40000334;
|
||||
spi_flash_hal_check_status = 0x40000338;
|
||||
spi_flash_hal_setup_read_suspend = 0x4000033c;
|
||||
spi_flash_hal_setup_auto_suspend_mode = 0x40000340;
|
||||
spi_flash_hal_setup_auto_resume_mode = 0x40000344;
|
||||
spi_flash_hal_disable_auto_suspend_mode = 0x40000348;
|
||||
spi_flash_hal_disable_auto_resume_mode = 0x4000034c;
|
||||
spi_flash_hal_resume = 0x40000350;
|
||||
spi_flash_hal_suspend = 0x40000354;
|
||||
spi_flash_encryption_hal_enable = 0x40000358;
|
||||
spi_flash_encryption_hal_disable = 0x4000035c;
|
||||
spi_flash_encryption_hal_prepare = 0x40000360;
|
||||
spi_flash_encryption_hal_done = 0x40000364;
|
||||
spi_flash_encryption_hal_destroy = 0x40000368;
|
||||
spi_flash_encryption_hal_check = 0x4000036c;
|
||||
@@ -1,28 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
/***************************************
|
||||
Group hal_systimer
|
||||
***************************************/
|
||||
|
||||
/* Functions */
|
||||
/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
|
||||
/* systimer_hal_init = 0x4000039c; */
|
||||
/* systimer_hal_deinit = 0x400003a0; */
|
||||
|
||||
systimer_hal_set_tick_rate_ops = 0x400003a4;
|
||||
systimer_hal_get_counter_value = 0x400003a8;
|
||||
systimer_hal_get_time = 0x400003ac;
|
||||
systimer_hal_set_alarm_target = 0x400003b0;
|
||||
systimer_hal_set_alarm_period = 0x400003b4;
|
||||
systimer_hal_get_alarm_value = 0x400003b8;
|
||||
systimer_hal_enable_alarm_int = 0x400003bc;
|
||||
systimer_hal_on_apb_freq_update = 0x400003c0;
|
||||
systimer_hal_counter_value_advance = 0x400003c4;
|
||||
systimer_hal_enable_counter = 0x400003c8;
|
||||
systimer_hal_select_alarm_mode = 0x400003cc;
|
||||
systimer_hal_connect_alarm_counter = 0x400003d0;
|
||||
systimer_hal_counter_can_stall_by_cpu = 0x400003d4;
|
||||
@@ -4,17 +4,10 @@ set(target_folder "${target}")
|
||||
|
||||
# On Linux the soc component is a simple wrapper, without much functionality
|
||||
if(NOT ${target} STREQUAL "linux")
|
||||
if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
|
||||
set(srcs "lldesc.c"
|
||||
"dport_access_common.c"
|
||||
"${target_folder}/interrupts_beta5.c"
|
||||
"${target_folder}/gpio_periph.c")
|
||||
else()
|
||||
set(srcs "lldesc.c"
|
||||
"dport_access_common.c"
|
||||
"${target_folder}/interrupts.c"
|
||||
"${target_folder}/gpio_periph.c")
|
||||
endif()
|
||||
set(srcs "lldesc.c"
|
||||
"dport_access_common.c"
|
||||
"${target_folder}/interrupts.c"
|
||||
"${target_folder}/gpio_periph.c")
|
||||
endif()
|
||||
|
||||
set(includes "include" "${target_folder}")
|
||||
@@ -22,13 +15,6 @@ set(includes "include" "${target_folder}")
|
||||
if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/include")
|
||||
# miscellaneous headers, like definitions, man-made register headers, wrappers, etc.
|
||||
list(APPEND includes "${target_folder}/include")
|
||||
if(CONFIG_IDF_TARGET_ESP32H4) # TODO: ESP32H4 IDF-13835
|
||||
if(CONFIG_ESP32H4_SELECTS_REV_MP)
|
||||
list(APPEND includes "${target_folder}/include/hw_ver_mp")
|
||||
else()
|
||||
list(APPEND includes "${target_folder}/include/hw_ver_beta5")
|
||||
endif()
|
||||
endif()
|
||||
endif()
|
||||
|
||||
# register headers that generated by script from CSV
|
||||
@@ -45,13 +31,6 @@ elseif(CONFIG_IDF_TARGET_ESP32H21) # TODO: ESP32H21 IDF-13923
|
||||
else()
|
||||
list(APPEND includes "${target_folder}/register/hw_ver_beta1")
|
||||
endif()
|
||||
elseif(CONFIG_IDF_TARGET_ESP32H4) # TODO: ESP32H4 IDF-13835
|
||||
list(APPEND includes "${target_folder}/register")
|
||||
if(CONFIG_ESP32H4_SELECTS_REV_MP)
|
||||
list(APPEND includes "${target_folder}/register/hw_ver_mp")
|
||||
else()
|
||||
list(APPEND includes "${target_folder}/register/hw_ver_beta5")
|
||||
endif()
|
||||
else()
|
||||
if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register")
|
||||
list(APPEND includes "${target_folder}/register")
|
||||
@@ -96,9 +75,5 @@ if(target STREQUAL "esp32")
|
||||
endif()
|
||||
|
||||
if(NOT CONFIG_IDF_TARGET_LINUX)
|
||||
if(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.beta5.ld")
|
||||
else()
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld")
|
||||
endif()
|
||||
target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/ld/${target}.peripherals.ld")
|
||||
endif()
|
||||
|
||||
@@ -1,116 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
//Interrupt hardware source table
|
||||
//This table is decided by hardware, don't touch this.
|
||||
typedef enum {
|
||||
ETS_WIFI_MAC_INTR_SOURCE,
|
||||
ETS_WIFI_MAC_NMI_SOURCE,
|
||||
ETS_WIFI_PWR_INTR_SOURCE,
|
||||
ETS_WIFI_BB_INTR_SOURCE,
|
||||
ETS_BT_MAC_INTR_SOURCE,
|
||||
ETS_BT_BB_INTR_SOURCE,
|
||||
ETS_BT_BB_NMI_SOURCE,
|
||||
ETS_LP_TIMER_INTR_SOURCE,
|
||||
ETS_COEX_INTR_SOURCE,
|
||||
ETS_BLE_TIMER_INTR_SOURCE,
|
||||
ETS_BLE_SEC_INTR_SOURCE,
|
||||
ETS_I2C_MST_INTR_SOURCE,
|
||||
ETS_ZB_MAC_INTR_SOURCE,
|
||||
ETS_MODEM_APB_TIMEOUT_INTR_SOURCE,
|
||||
ETS_BT_MAC_INT1_SOURCE,
|
||||
ETS_PMU_INTR_SOURCE,
|
||||
ETS_EFUSE_INTR_SOURCE,
|
||||
ETS_LP_RTC_TIMER_INTR_SOURCE,
|
||||
ETS_LP_RTC_BLE_TIMER_INTR_SOURCE,
|
||||
ETS_LP_WDT_INTR_SOURCE,
|
||||
ETS_TOUCH_INTR_SOURCE,
|
||||
ETS_HUK_INTR_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_0_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_1_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_2_SOURCE,
|
||||
ETS_CPU_INTR_FROM_CPU_3_SOURCE,
|
||||
ETS_BUS_MONITOR_INTR_SOURCE,
|
||||
ETS_CORE0_TRACE_INTR_SOURCE,
|
||||
ETS_CORE1_TRACE_INTR_SOURCE,
|
||||
ETS_CACHE_INTR_SOURCE,
|
||||
ETS_CPU_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_GPIO_INTERRUPT_PRO_SOURCE,
|
||||
ETS_GPIO_INTERRUPT_2_SOURCE,
|
||||
ETS_PAU_INTR_SOURCE,
|
||||
ETS_HP_PERI_TIMEOUT_INTR_SOURCE,
|
||||
ETS_HP_APM_M0_INTR_SOURCE,
|
||||
ETS_HP_APM_M1_INTR_SOURCE,
|
||||
ETS_HP_APM_M2_INTR_SOURCE,
|
||||
ETS_HP_APM_M3_INTR_SOURCE,
|
||||
ETS_HP_APM_M4_INTR_SOURCE,
|
||||
ETS_CPU_APM_M0_INTR_SOURCE,
|
||||
ETS_CPU_APM_M1_INTR_SOURCE,
|
||||
ETS_CPU_APM_M2_INTR_SOURCE,
|
||||
ETS_CPU_APM_M3_INTR_SOURCE,
|
||||
ETS_MSPI_INTR_SOURCE,
|
||||
ETS_I2S_INTR_SOURCE,
|
||||
ETS_UHCI0_INTR_SOURCE,
|
||||
ETS_UART0_INTR_SOURCE,
|
||||
ETS_UART1_INTR_SOURCE,
|
||||
ETS_LEDC_INTR_SOURCE,
|
||||
ETS_TWAI0_INTR_SOURCE,
|
||||
ETS_TWAI0_TIMER_INTR_SOURCE,
|
||||
ETS_USB_SERIAL_JTAG_INTR_SOURCE,
|
||||
ETS_RMT_INTR_SOURCE,
|
||||
ETS_I2C_EXT0_INTR_SOURCE,
|
||||
ETS_I2C_EXT1_INTR_SOURCE,
|
||||
ETS_TG0_T0_INTR_SOURCE,
|
||||
ETS_TG0_WDT_INTR_SOURCE,
|
||||
ETS_TG1_T0_INTR_SOURCE,
|
||||
ETS_TG1_WDT_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET0_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET1_INTR_SOURCE,
|
||||
ETS_SYSTIMER_TARGET2_INTR_SOURCE,
|
||||
ETS_APB_ADC_INTR_SOURCE,
|
||||
ETS_PWM0_INTR_SOURCE,
|
||||
ETS_PWM1_INTR_SOURCE,
|
||||
ETS_PCNT_INTR_SOURCE,
|
||||
ETS_PARL_IO_TX_INTR_SOURCE,
|
||||
ETS_PARL_IO_RX_INTR_SOURCE,
|
||||
ETS_USB_OTG11_INTR_SOURCE,
|
||||
ETS_ASRC_CHNL0_INTR_SOURCE,
|
||||
ETS_ASRC_CHNL1_INTR_SOURCE,
|
||||
ETS_ZERO_DET_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH0_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH1_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH2_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH3_INTR_SOURCE,
|
||||
ETS_DMA_IN_CH4_INTR_SOURCE,
|
||||
ETS_DMA_OUT_CH0_INTR_SOURCE,
|
||||
ETS_DMA_OUT_CH1_INTR_SOURCE,
|
||||
ETS_DMA_OUT_CH2_INTR_SOURCE,
|
||||
ETS_DMA_OUT_CH3_INTR_SOURCE,
|
||||
ETS_DMA_OUT_CH4_INTR_SOURCE,
|
||||
ETS_GPSPI2_INTR_SOURCE,
|
||||
ETS_GPSPI3_INTR_SOURCE,
|
||||
ETS_AES_INTR_SOURCE,
|
||||
ETS_SHA_INTR_SOURCE,
|
||||
ETS_ECC_INTR_SOURCE,
|
||||
ETS_ECDSA_INTR_SOURCE,
|
||||
ETS_KM_INTR_SOURCE,
|
||||
ETS_MAX_INTR_SOURCE,
|
||||
} periph_interrupt_t;
|
||||
|
||||
extern const char * const esp_isr_names[ETS_MAX_INTR_SOURCE];
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,100 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
|
||||
#include "soc/interrupts.h"
|
||||
|
||||
const char *const esp_isr_names[] = {
|
||||
[0] = "WIFI_MAC",
|
||||
[1] = "WIFI_MAC_NMI",
|
||||
[2] = "WIFI_PWR",
|
||||
[3] = "WIFI_BB",
|
||||
[4] = "BT_MAC",
|
||||
[5] = "BT_BB",
|
||||
[6] = "BT_BB_NMI",
|
||||
[7] = "LP_TIMER",
|
||||
[8] = "COEX",
|
||||
[9] = "BLE_TIMER",
|
||||
[10] = "BLE_SEC",
|
||||
[11] = "I2C_MST",
|
||||
[12] = "ZB_MAC",
|
||||
[13] = "MODEM_APB_TIMEOUT",
|
||||
[14] = "BT_MAC_INT1",
|
||||
[15] = "PMU",
|
||||
[16] = "EFUSE",
|
||||
[17] = "LP_RTC_TIMER",
|
||||
[18] = "LP_RTC_BLE_TIMER",
|
||||
[19] = "LP_WDT",
|
||||
[20] = "TOUCH",
|
||||
[21] = "HUK",
|
||||
[22] = "CPU_FROM_CPU_0",
|
||||
[23] = "CPU_FROM_CPU_1",
|
||||
[24] = "CPU_FROM_CPU_2",
|
||||
[25] = "CPU_FROM_CPU_3",
|
||||
[26] = "BUS_MONITOR",
|
||||
[27] = "CORE0_TRACE",
|
||||
[28] = "CORE1_TRACE",
|
||||
[29] = "CACHE",
|
||||
[30] = "CPU_PERI_TIMEOUT",
|
||||
[31] = "GPIO_INTERRUPT_PRO",
|
||||
[32] = "GPIO_INTERRUPT_2",
|
||||
[33] = "PAU",
|
||||
[34] = "HP_PERI_TIMEOUT",
|
||||
[35] = "HP_APM_M0",
|
||||
[36] = "HP_APM_M1",
|
||||
[37] = "HP_APM_M2",
|
||||
[38] = "HP_APM_M3",
|
||||
[39] = "HP_APM_M4",
|
||||
[40] = "CPU_APM_M0",
|
||||
[41] = "CPU_APM_M1",
|
||||
[42] = "CPU_APM_M2",
|
||||
[43] = "CPU_APM_M3",
|
||||
[44] = "MSPI",
|
||||
[45] = "I2S",
|
||||
[46] = "UHCI0",
|
||||
[47] = "UART0",
|
||||
[48] = "UART1",
|
||||
[49] = "LEDC",
|
||||
[50] = "TWAI0",
|
||||
[51] = "TWAI0_TIMER",
|
||||
[52] = "USB_SERIAL_JTAG",
|
||||
[53] = "RMT",
|
||||
[54] = "I2C_EXT0",
|
||||
[55] = "I2C_EXT1",
|
||||
[56] = "TG0_T0",
|
||||
[57] = "TG0_WDT",
|
||||
[58] = "TG1_T0",
|
||||
[59] = "TG1_WDT",
|
||||
[60] = "SYSTIMER_TARGET0",
|
||||
[61] = "SYSTIMER_TARGET1",
|
||||
[62] = "SYSTIMER_TARGET2",
|
||||
[63] = "APB_ADC",
|
||||
[64] = "PWM0",
|
||||
[65] = "PWM1",
|
||||
[66] = "PCNT",
|
||||
[67] = "PARL_IO_TX",
|
||||
[68] = "PARL_IO_RX",
|
||||
[69] = "USB_OTG11",
|
||||
[70] = "ASRC_CHNL0",
|
||||
[71] = "ASRC_CHNL1",
|
||||
[72] = "ZERO_DET",
|
||||
[73] = "DMA_IN_CH0",
|
||||
[74] = "DMA_IN_CH1",
|
||||
[75] = "DMA_IN_CH2",
|
||||
[76] = "DMA_IN_CH3",
|
||||
[77] = "DMA_IN_CH4",
|
||||
[78] = "DMA_OUT_CH0",
|
||||
[79] = "DMA_OUT_CH1",
|
||||
[80] = "DMA_OUT_CH2",
|
||||
[81] = "DMA_OUT_CH3",
|
||||
[82] = "DMA_OUT_CH4",
|
||||
[83] = "GPSPI2",
|
||||
[84] = "GPSPI3",
|
||||
[85] = "AES",
|
||||
[86] = "SHA",
|
||||
[87] = "ECC",
|
||||
[88] = "ECDSA",
|
||||
[89] = "KM",
|
||||
};
|
||||
@@ -1,84 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
|
||||
PROVIDE ( TRACE0 = 0x60000000 );
|
||||
PROVIDE ( TRACE1 = 0x60001000 );
|
||||
PROVIDE ( BUS_MONITOR = 0x60002000 );
|
||||
PROVIDE ( INTPRI = 0x60005000 );
|
||||
PROVIDE ( CACHE = 0x60008000 );
|
||||
PROVIDE ( GPSPI2 = 0x60010000 );
|
||||
PROVIDE ( GPSPI3 = 0x60011000 );
|
||||
PROVIDE ( UART0 = 0x60012000 );
|
||||
PROVIDE ( UART1 = 0x60013000 );
|
||||
PROVIDE ( UHCI0 = 0x60014000 );
|
||||
PROVIDE ( I2C0 = 0x60015000 );
|
||||
PROVIDE ( I2C1 = 0x60016000 );
|
||||
PROVIDE ( I2S0 = 0x60017000 );
|
||||
PROVIDE ( PARL_IO = 0x60018000 );
|
||||
PROVIDE ( MCPWM0 = 0x60019000 );
|
||||
PROVIDE ( MCPWM1 = 0x6001A000 );
|
||||
PROVIDE ( LEDC = 0x6001B000 );
|
||||
PROVIDE ( TWAI0 = 0x6001C000 );
|
||||
PROVIDE ( USB_SERIAL_JTAG = 0x6001D000 );
|
||||
PROVIDE ( RMT = 0x6001E000 );
|
||||
PROVIDE ( RMTMEM = 0x6001E400 );
|
||||
PROVIDE ( AHB_DMA = 0x6001F000 );
|
||||
PROVIDE ( PAU = 0x60020000 );
|
||||
PROVIDE ( SOC_ETM = 0x60021000 );
|
||||
PROVIDE ( ADC = 0x60022000 );
|
||||
PROVIDE ( SYSTIMER = 0x60023000 );
|
||||
PROVIDE ( PSRAM_ACS_MONITOR = 0x60024000 ); /* TODO: IDF-12491 [ESP32H4] inherit from verify code, need check */
|
||||
PROVIDE ( MEM_MONITOR = 0x60025000 );
|
||||
PROVIDE ( PVT = 0x60026000 );
|
||||
PROVIDE ( PCNT = 0x60027000 );
|
||||
PROVIDE ( SAMPLE_RATE_CONVERTER = 0x60028000 );
|
||||
PROVIDE ( ZERO_DET = 0x60029000 );
|
||||
PROVIDE ( USB_OTG_FS_CORE0 = 0x60040000 );
|
||||
PROVIDE ( USB_OTG_FS_CORE1 = 0x6007F000 );
|
||||
PROVIDE ( USB_DWC = 0x60040000 );
|
||||
PROVIDE ( USB_WRAP = 0x60080000 );
|
||||
PROVIDE ( TIMERG0 = 0x60090000 );
|
||||
PROVIDE ( TIMERG1 = 0x60091000 );
|
||||
PROVIDE ( IO_MUX = 0x60092000 );
|
||||
PROVIDE ( GPIO = 0x60093000 );
|
||||
PROVIDE ( GPIO_EXT = 0x60093E00 );
|
||||
PROVIDE ( SDM = 0x60093E00 );
|
||||
PROVIDE ( GLITCH_FILTER = 0x60093ED8 );
|
||||
PROVIDE ( GPIO_ETM = 0x60093F18 );
|
||||
PROVIDE ( PCR = 0x60094000 );
|
||||
PROVIDE ( SPIMEM0 = 0x60098000 );
|
||||
PROVIDE ( SPIMEM1 = 0x60099000 );
|
||||
PROVIDE ( INTMTX0 = 0x6009A000 );
|
||||
PROVIDE ( INTMTX1 = 0x6009B000 );
|
||||
PROVIDE ( HP_SYSTEM = 0x6009C000 );
|
||||
PROVIDE ( HP_APM = 0x6009D000 );
|
||||
PROVIDE ( CPU_APM = 0x6009E000 );
|
||||
PROVIDE ( TEE = 0x6009F000 );
|
||||
PROVIDE ( KEYMNG = 0x600A5000 );
|
||||
PROVIDE ( AES = 0x600A6000 );
|
||||
PROVIDE ( SHA = 0x600A7000 );
|
||||
PROVIDE ( ECC = 0x600A8000 );
|
||||
PROVIDE ( HMAC = 0x600A9000 );
|
||||
PROVIDE ( ECDSA = 0x600AA000 );
|
||||
PROVIDE ( HUK = 0x600B1000 );
|
||||
PROVIDE ( LP_TEE = 0x600B1400 );
|
||||
PROVIDE ( EFUSE = 0x600B1800 );
|
||||
PROVIDE ( OTP_DEBUG = 0x600B1C00 );
|
||||
PROVIDE ( TRNG = 0x600B2000 );
|
||||
PROVIDE ( PMU = 0x600B2400 );
|
||||
PROVIDE ( LP_AON = 0x600B2800 );
|
||||
PROVIDE ( LP_ANA_PERI = 0x600B2C00 );
|
||||
PROVIDE ( LP_CLKRST = 0x600B3000 );
|
||||
PROVIDE ( LPPERI = 0x600B3400 );
|
||||
PROVIDE ( LP_IO_MUX = 0x600B3800 );
|
||||
PROVIDE ( LP_GPIO = 0x600B3C00 );
|
||||
PROVIDE ( LP_TIMER = 0x600B5000 );
|
||||
PROVIDE ( LP_WDT = 0x600B5400 );
|
||||
PROVIDE ( TOUCH_SENS = 0x600B5800 );
|
||||
PROVIDE ( TOUCH_AON = 0x600B5C00 );
|
||||
PROVIDE ( IEEE802154 = 0x600C3000 );
|
||||
PROVIDE ( MODEM_SYSCON = 0x600C9C00 );
|
||||
PROVIDE ( MODEM_LPCON = 0x600CF000 );
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,578 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: Region filter enable register */
|
||||
/** Type of apm_region_filter_en register
|
||||
* Region filter enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_region_filter_en : R/W; bitpos: [7:0]; default: 1;
|
||||
* Configure bit $n (0-7) to enable region $n.
|
||||
* 0: disable
|
||||
* 1: enable
|
||||
*/
|
||||
uint32_t apm_region_filter_en:8;
|
||||
uint32_t reserved_8:24;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_region_filter_en_reg_t;
|
||||
|
||||
|
||||
/** Group: Region address register */
|
||||
/** Type of apm_regionn_addr_start register
|
||||
* Region address register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_regionn_addr_start_l : HRO; bitpos: [11:0]; default: 0;
|
||||
* Low 12 bit, start address of region n.
|
||||
*/
|
||||
uint32_t apm_regionn_addr_start_l:12;
|
||||
/** apm_regionn_addr_start : R/W; bitpos: [18:12]; default: 0;
|
||||
* Configures start address of region n.
|
||||
*/
|
||||
uint32_t apm_regionn_addr_start:7;
|
||||
/** apm_regionn_addr_start_h : HRO; bitpos: [31:19]; default: 2064;
|
||||
* High 13 bit, start address of region n.
|
||||
*/
|
||||
uint32_t apm_regionn_addr_start_h:13;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_regionn_addr_start_reg_t;
|
||||
|
||||
/** Type of apm_regionn_addr_end register
|
||||
* Region address register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_regionn_addr_end_l : HRO; bitpos: [11:0]; default: 4095;
|
||||
* Low 12 bit, end address of region n.
|
||||
*/
|
||||
uint32_t apm_regionn_addr_end_l:12;
|
||||
/** apm_regionn_addr_end : R/W; bitpos: [18:12]; default: 127;
|
||||
* Configures end address of region n.
|
||||
*/
|
||||
uint32_t apm_regionn_addr_end:7;
|
||||
/** apm_regionn_addr_end_h : HRO; bitpos: [31:19]; default: 2064;
|
||||
* High 13 bit, end address of region n.
|
||||
*/
|
||||
uint32_t apm_regionn_addr_end_h:13;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_regionn_addr_end_reg_t;
|
||||
|
||||
|
||||
/** Group: Region access authority attribute register */
|
||||
/** Type of apm_regionn_attr register
|
||||
* Region access authority attribute register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_regionn_r0_x : R/W; bitpos: [0]; default: 0;
|
||||
* Configures the execution authority of REE_MODE 0 in region n.
|
||||
*/
|
||||
uint32_t apm_regionn_r0_x:1;
|
||||
/** apm_regionn_r0_w : R/W; bitpos: [1]; default: 0;
|
||||
* Configures the write authority of REE_MODE 0 in region n.
|
||||
*/
|
||||
uint32_t apm_regionn_r0_w:1;
|
||||
/** apm_regionn_r0_r : R/W; bitpos: [2]; default: 0;
|
||||
* Configures the read authority of REE_MODE 0 in region n.
|
||||
*/
|
||||
uint32_t apm_regionn_r0_r:1;
|
||||
uint32_t reserved_3:1;
|
||||
/** apm_regionn_r1_x : R/W; bitpos: [4]; default: 0;
|
||||
* Configures the execution authority of REE_MODE 1 in region n.
|
||||
*/
|
||||
uint32_t apm_regionn_r1_x:1;
|
||||
/** apm_regionn_r1_w : R/W; bitpos: [5]; default: 0;
|
||||
* Configures the write authority of REE_MODE 1 in region n.
|
||||
*/
|
||||
uint32_t apm_regionn_r1_w:1;
|
||||
/** apm_regionn_r1_r : R/W; bitpos: [6]; default: 0;
|
||||
* Configures the read authority of REE_MODE 1 in region n.
|
||||
*/
|
||||
uint32_t apm_regionn_r1_r:1;
|
||||
uint32_t reserved_7:1;
|
||||
/** apm_regionn_r2_x : R/W; bitpos: [8]; default: 0;
|
||||
* Configures the execution authority of REE_MODE 2 in region n.
|
||||
*/
|
||||
uint32_t apm_regionn_r2_x:1;
|
||||
/** apm_regionn_r2_w : R/W; bitpos: [9]; default: 0;
|
||||
* Configures the write authority of REE_MODE 2 in region n.
|
||||
*/
|
||||
uint32_t apm_regionn_r2_w:1;
|
||||
/** apm_regionn_r2_r : R/W; bitpos: [10]; default: 0;
|
||||
* Configures the read authority of REE_MODE 2 in region n.
|
||||
*/
|
||||
uint32_t apm_regionn_r2_r:1;
|
||||
/** apm_regionn_lock : R/W; bitpos: [11]; default: 0;
|
||||
* Set 1 to lock region0 configuration
|
||||
*/
|
||||
uint32_t apm_regionn_lock:1;
|
||||
uint32_t reserved_12:20;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_regionn_attr_reg_t;
|
||||
|
||||
|
||||
/** Group: function control register */
|
||||
/** Type of apm_func_ctrl register
|
||||
* APM function control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m0_func_en : R/W; bitpos: [0]; default: 1;
|
||||
* PMS M0 function enable
|
||||
*/
|
||||
uint32_t apm_m0_func_en:1;
|
||||
/** apm_m1_func_en : R/W; bitpos: [1]; default: 1;
|
||||
* PMS M1 function enable
|
||||
*/
|
||||
uint32_t apm_m1_func_en:1;
|
||||
/** apm_m2_func_en : R/W; bitpos: [2]; default: 1;
|
||||
* PMS M2 function enable
|
||||
*/
|
||||
uint32_t apm_m2_func_en:1;
|
||||
/** apm_m3_func_en : R/W; bitpos: [3]; default: 1;
|
||||
* PMS M3 function enable
|
||||
*/
|
||||
uint32_t apm_m3_func_en:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_func_ctrl_reg_t;
|
||||
|
||||
|
||||
/** Group: M0 status register */
|
||||
/** Type of apm_m0_status register
|
||||
* M0 status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m0_exception_status : RO; bitpos: [1:0]; default: 0;
|
||||
* Represents exception status.
|
||||
* bit0: 1 represents authority_exception
|
||||
* bit1: 1 represents space_exception
|
||||
*/
|
||||
uint32_t apm_m0_exception_status:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m0_status_reg_t;
|
||||
|
||||
|
||||
/** Group: M0 status clear register */
|
||||
/** Type of apm_m0_status_clr register
|
||||
* M0 status clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m0_exception_status_clr : WT; bitpos: [0]; default: 0;
|
||||
* Configures to clear exception status.
|
||||
*/
|
||||
uint32_t apm_m0_exception_status_clr:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m0_status_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: M0 exception_info0 register */
|
||||
/** Type of apm_m0_exception_info0 register
|
||||
* M0 exception_info0 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m0_exception_region : RO; bitpos: [15:0]; default: 0;
|
||||
* Represents exception region.
|
||||
*/
|
||||
uint32_t apm_m0_exception_region:16;
|
||||
/** apm_m0_exception_mode : RO; bitpos: [17:16]; default: 0;
|
||||
* Represents exception mode.
|
||||
*/
|
||||
uint32_t apm_m0_exception_mode:2;
|
||||
/** apm_m0_exception_id : RO; bitpos: [22:18]; default: 0;
|
||||
* Represents exception id information.
|
||||
*/
|
||||
uint32_t apm_m0_exception_id:5;
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m0_exception_info0_reg_t;
|
||||
|
||||
|
||||
/** Group: M0 exception_info1 register */
|
||||
/** Type of apm_m0_exception_info1 register
|
||||
* M0 exception_info1 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m0_exception_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents exception addr.
|
||||
*/
|
||||
uint32_t apm_m0_exception_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m0_exception_info1_reg_t;
|
||||
|
||||
|
||||
/** Group: M1 status register */
|
||||
/** Type of apm_m1_status register
|
||||
* M1 status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m1_exception_status : RO; bitpos: [1:0]; default: 0;
|
||||
* Represents exception status.
|
||||
* bit0: 1 represents authority_exception
|
||||
* bit1: 1 represents space_exception
|
||||
*/
|
||||
uint32_t apm_m1_exception_status:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m1_status_reg_t;
|
||||
|
||||
|
||||
/** Group: M1 status clear register */
|
||||
/** Type of apm_m1_status_clr register
|
||||
* M1 status clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m1_exception_status_clr : WT; bitpos: [0]; default: 0;
|
||||
* Configures to clear exception status.
|
||||
*/
|
||||
uint32_t apm_m1_exception_status_clr:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m1_status_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: M1 exception_info0 register */
|
||||
/** Type of apm_m1_exception_info0 register
|
||||
* M1 exception_info0 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m1_exception_region : RO; bitpos: [15:0]; default: 0;
|
||||
* Represents exception region.
|
||||
*/
|
||||
uint32_t apm_m1_exception_region:16;
|
||||
/** apm_m1_exception_mode : RO; bitpos: [17:16]; default: 0;
|
||||
* Represents exception mode.
|
||||
*/
|
||||
uint32_t apm_m1_exception_mode:2;
|
||||
/** apm_m1_exception_id : RO; bitpos: [22:18]; default: 0;
|
||||
* Represents exception id information.
|
||||
*/
|
||||
uint32_t apm_m1_exception_id:5;
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m1_exception_info0_reg_t;
|
||||
|
||||
|
||||
/** Group: M1 exception_info1 register */
|
||||
/** Type of apm_m1_exception_info1 register
|
||||
* M1 exception_info1 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m1_exception_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents exception addr.
|
||||
*/
|
||||
uint32_t apm_m1_exception_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m1_exception_info1_reg_t;
|
||||
|
||||
|
||||
/** Group: M2 status register */
|
||||
/** Type of apm_m2_status register
|
||||
* M2 status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m2_exception_status : RO; bitpos: [1:0]; default: 0;
|
||||
* Represents exception status.
|
||||
* bit0: 1 represents authority_exception
|
||||
* bit1: 1 represents space_exception
|
||||
*/
|
||||
uint32_t apm_m2_exception_status:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m2_status_reg_t;
|
||||
|
||||
|
||||
/** Group: M2 status clear register */
|
||||
/** Type of apm_m2_status_clr register
|
||||
* M2 status clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m2_exception_status_clr : WT; bitpos: [0]; default: 0;
|
||||
* Configures to clear exception status.
|
||||
*/
|
||||
uint32_t apm_m2_exception_status_clr:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m2_status_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: M2 exception_info0 register */
|
||||
/** Type of apm_m2_exception_info0 register
|
||||
* M2 exception_info0 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m2_exception_region : RO; bitpos: [15:0]; default: 0;
|
||||
* Represents exception region.
|
||||
*/
|
||||
uint32_t apm_m2_exception_region:16;
|
||||
/** apm_m2_exception_mode : RO; bitpos: [17:16]; default: 0;
|
||||
* Represents exception mode.
|
||||
*/
|
||||
uint32_t apm_m2_exception_mode:2;
|
||||
/** apm_m2_exception_id : RO; bitpos: [22:18]; default: 0;
|
||||
* Represents exception id information.
|
||||
*/
|
||||
uint32_t apm_m2_exception_id:5;
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m2_exception_info0_reg_t;
|
||||
|
||||
|
||||
/** Group: M2 exception_info1 register */
|
||||
/** Type of apm_m2_exception_info1 register
|
||||
* M2 exception_info1 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m2_exception_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents exception addr.
|
||||
*/
|
||||
uint32_t apm_m2_exception_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m2_exception_info1_reg_t;
|
||||
|
||||
|
||||
/** Group: M3 status register */
|
||||
/** Type of apm_m3_status register
|
||||
* M3 status register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m3_exception_status : RO; bitpos: [1:0]; default: 0;
|
||||
* Represents exception status.
|
||||
* bit0: 1 represents authority_exception
|
||||
* bit1: 1 represents space_exception
|
||||
*/
|
||||
uint32_t apm_m3_exception_status:2;
|
||||
uint32_t reserved_2:30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m3_status_reg_t;
|
||||
|
||||
|
||||
/** Group: M3 status clear register */
|
||||
/** Type of apm_m3_status_clr register
|
||||
* M3 status clear register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m3_exception_status_clr : WT; bitpos: [0]; default: 0;
|
||||
* Configures to clear exception status.
|
||||
*/
|
||||
uint32_t apm_m3_exception_status_clr:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m3_status_clr_reg_t;
|
||||
|
||||
|
||||
/** Group: M3 exception_info0 register */
|
||||
/** Type of apm_m3_exception_info0 register
|
||||
* M3 exception_info0 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m3_exception_region : RO; bitpos: [15:0]; default: 0;
|
||||
* Represents exception region.
|
||||
*/
|
||||
uint32_t apm_m3_exception_region:16;
|
||||
/** apm_m3_exception_mode : RO; bitpos: [17:16]; default: 0;
|
||||
* Represents exception mode.
|
||||
*/
|
||||
uint32_t apm_m3_exception_mode:2;
|
||||
/** apm_m3_exception_id : RO; bitpos: [22:18]; default: 0;
|
||||
* Represents exception id information.
|
||||
*/
|
||||
uint32_t apm_m3_exception_id:5;
|
||||
uint32_t reserved_23:9;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m3_exception_info0_reg_t;
|
||||
|
||||
|
||||
/** Group: M3 exception_info1 register */
|
||||
/** Type of apm_m3_exception_info1 register
|
||||
* M3 exception_info1 register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m3_exception_addr : RO; bitpos: [31:0]; default: 0;
|
||||
* Represents exception addr.
|
||||
*/
|
||||
uint32_t apm_m3_exception_addr:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_m3_exception_info1_reg_t;
|
||||
|
||||
|
||||
/** Group: APM interrupt enable register */
|
||||
/** Type of apm_int_en register
|
||||
* APM interrupt enable register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_m0_apm_int_en : R/W; bitpos: [0]; default: 0;
|
||||
* Configures to enable APM M0 interrupt.
|
||||
* 0: disable
|
||||
* 1: enable
|
||||
*/
|
||||
uint32_t apm_m0_apm_int_en:1;
|
||||
/** apm_m1_apm_int_en : R/W; bitpos: [1]; default: 0;
|
||||
* Configures to enable APM M1 interrupt.
|
||||
* 0: disable
|
||||
* 1: enable
|
||||
*/
|
||||
uint32_t apm_m1_apm_int_en:1;
|
||||
/** apm_m2_apm_int_en : R/W; bitpos: [2]; default: 0;
|
||||
* Configures to enable APM M2 interrupt.
|
||||
* 0: disable
|
||||
* 1: enable
|
||||
*/
|
||||
uint32_t apm_m2_apm_int_en:1;
|
||||
/** apm_m3_apm_int_en : R/W; bitpos: [3]; default: 0;
|
||||
* Configures to enable APM M3 interrupt.
|
||||
* 0: disable
|
||||
* 1: enable
|
||||
*/
|
||||
uint32_t apm_m3_apm_int_en:1;
|
||||
uint32_t reserved_4:28;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_int_en_reg_t;
|
||||
|
||||
|
||||
/** Group: Clock gating register */
|
||||
/** Type of apm_clock_gate register
|
||||
* Clock gating register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_clk_en : R/W; bitpos: [0]; default: 1;
|
||||
* Configures whether to keep the clock always on.
|
||||
* 0: enable automatic clock gating
|
||||
* 1: keep the clock always on
|
||||
*/
|
||||
uint32_t apm_clk_en:1;
|
||||
uint32_t reserved_1:31;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_clock_gate_reg_t;
|
||||
|
||||
|
||||
/** Group: Version control register */
|
||||
/** Type of apm_date register
|
||||
* Version control register
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** apm_date : R/W; bitpos: [27:0]; default: 37769360;
|
||||
* Version control register.
|
||||
*/
|
||||
uint32_t apm_date:28;
|
||||
uint32_t reserved_28:4;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_apm_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile cpu_apm_region_filter_en_reg_t apm_region_filter_en;
|
||||
volatile cpu_apm_regionn_addr_start_reg_t apm_region0_addr_start;
|
||||
volatile cpu_apm_regionn_addr_end_reg_t apm_region0_addr_end;
|
||||
volatile cpu_apm_regionn_attr_reg_t apm_region0_attr;
|
||||
volatile cpu_apm_regionn_addr_start_reg_t apm_region1_addr_start;
|
||||
volatile cpu_apm_regionn_addr_end_reg_t apm_region1_addr_end;
|
||||
volatile cpu_apm_regionn_attr_reg_t apm_region1_attr;
|
||||
volatile cpu_apm_regionn_addr_start_reg_t apm_region2_addr_start;
|
||||
volatile cpu_apm_regionn_addr_end_reg_t apm_region2_addr_end;
|
||||
volatile cpu_apm_regionn_attr_reg_t apm_region2_attr;
|
||||
volatile cpu_apm_regionn_addr_start_reg_t apm_region3_addr_start;
|
||||
volatile cpu_apm_regionn_addr_end_reg_t apm_region3_addr_end;
|
||||
volatile cpu_apm_regionn_attr_reg_t apm_region3_attr;
|
||||
volatile cpu_apm_regionn_addr_start_reg_t apm_region4_addr_start;
|
||||
volatile cpu_apm_regionn_addr_end_reg_t apm_region4_addr_end;
|
||||
volatile cpu_apm_regionn_attr_reg_t apm_region4_attr;
|
||||
volatile cpu_apm_regionn_addr_start_reg_t apm_region5_addr_start;
|
||||
volatile cpu_apm_regionn_addr_end_reg_t apm_region5_addr_end;
|
||||
volatile cpu_apm_regionn_attr_reg_t apm_region5_attr;
|
||||
volatile cpu_apm_regionn_addr_start_reg_t apm_region6_addr_start;
|
||||
volatile cpu_apm_regionn_addr_end_reg_t apm_region6_addr_end;
|
||||
volatile cpu_apm_regionn_attr_reg_t apm_region6_attr;
|
||||
volatile cpu_apm_regionn_addr_start_reg_t apm_region7_addr_start;
|
||||
volatile cpu_apm_regionn_addr_end_reg_t apm_region7_addr_end;
|
||||
volatile cpu_apm_regionn_attr_reg_t apm_region7_attr;
|
||||
uint32_t reserved_064[24];
|
||||
volatile cpu_apm_func_ctrl_reg_t apm_func_ctrl;
|
||||
volatile cpu_apm_m0_status_reg_t apm_m0_status;
|
||||
volatile cpu_apm_m0_status_clr_reg_t apm_m0_status_clr;
|
||||
volatile cpu_apm_m0_exception_info0_reg_t apm_m0_exception_info0;
|
||||
volatile cpu_apm_m0_exception_info1_reg_t apm_m0_exception_info1;
|
||||
volatile cpu_apm_m1_status_reg_t apm_m1_status;
|
||||
volatile cpu_apm_m1_status_clr_reg_t apm_m1_status_clr;
|
||||
volatile cpu_apm_m1_exception_info0_reg_t apm_m1_exception_info0;
|
||||
volatile cpu_apm_m1_exception_info1_reg_t apm_m1_exception_info1;
|
||||
volatile cpu_apm_m2_status_reg_t apm_m2_status;
|
||||
volatile cpu_apm_m2_status_clr_reg_t apm_m2_status_clr;
|
||||
volatile cpu_apm_m2_exception_info0_reg_t apm_m2_exception_info0;
|
||||
volatile cpu_apm_m2_exception_info1_reg_t apm_m2_exception_info1;
|
||||
volatile cpu_apm_m3_status_reg_t apm_m3_status;
|
||||
volatile cpu_apm_m3_status_clr_reg_t apm_m3_status_clr;
|
||||
volatile cpu_apm_m3_exception_info0_reg_t apm_m3_exception_info0;
|
||||
volatile cpu_apm_m3_exception_info1_reg_t apm_m3_exception_info1;
|
||||
uint32_t reserved_108[4];
|
||||
volatile cpu_apm_int_en_reg_t apm_int_en;
|
||||
uint32_t reserved_11c[439];
|
||||
volatile cpu_apm_clock_gate_reg_t apm_clock_gate;
|
||||
volatile cpu_apm_date_reg_t apm_date;
|
||||
} cpu_dev_t;
|
||||
|
||||
extern cpu_dev_t CPU_APM;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(cpu_dev_t) == 0x800, "Invalid size of cpu_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -1,917 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "soc/pmu_reg.h"
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 18;
|
||||
uint32_t vdd_flash_mode: 4;
|
||||
uint32_t mem_dslp : 1;
|
||||
uint32_t mem_pd_en : 4;
|
||||
uint32_t wifi_pd_en : 1;
|
||||
uint32_t peri_pd_en : 1;
|
||||
uint32_t cpu_pd_en : 1;
|
||||
uint32_t aon_pd_en : 1;
|
||||
uint32_t top_pd_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_dig_power_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0: 30;
|
||||
uint32_t code : 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_icg_modem_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 24;
|
||||
uint32_t uart_wakeup_en : 1;
|
||||
uint32_t lp_pad_hold_all: 1;
|
||||
uint32_t hp_pad_hold_all: 1;
|
||||
uint32_t dig_pad_slp_sel: 1;
|
||||
uint32_t dig_pause_wdt : 1;
|
||||
uint32_t dig_cpu_stall : 1;
|
||||
uint32_t reserved1 : 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_sys_cntl_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t i2c_iso_en : 1;
|
||||
uint32_t i2c_retention: 1;
|
||||
uint32_t xpd_bb_i2c : 1;
|
||||
uint32_t xpd_bbpll_i2c: 1;
|
||||
uint32_t xpd_bbpll : 1;
|
||||
uint32_t reserved1 : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_clk_power_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 9;
|
||||
uint32_t dcdc_ccm_enb : 1;
|
||||
uint32_t dcdc_clear_rdy : 1;
|
||||
uint32_t dig_reg_dpcur_bias: 2;
|
||||
uint32_t dig_reg_dsfmos : 4;
|
||||
uint32_t dcm_vset : 5;
|
||||
uint32_t dcm_mode : 2;
|
||||
uint32_t xpd_trx : 1;
|
||||
uint32_t xpd_bias : 1;
|
||||
uint32_t reserved1 : 3;
|
||||
uint32_t discnnt_dig_rtc : 1;
|
||||
uint32_t pd_cur : 1;
|
||||
uint32_t bias_sleep : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_bias_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct { /* HP: Active State */
|
||||
uint32_t reserved0 : 4;
|
||||
uint32_t hp_sleep2active_backup_modem_clk_code: 2;
|
||||
uint32_t hp_modem2active_backup_modem_clk_code: 2;
|
||||
uint32_t reserved1 : 6;
|
||||
uint32_t hp_sleep2active_backup_clk_sel : 2;
|
||||
uint32_t hp_modem2active_backup_clk_sel : 2;
|
||||
uint32_t hp_sleep2active_backup_mode : 5;
|
||||
uint32_t hp_modem2active_backup_mode : 5;
|
||||
uint32_t reserved3 : 1;
|
||||
uint32_t hp_sleep2active_backup_en : 1;
|
||||
uint32_t hp_modem2active_backup_en : 1;
|
||||
uint32_t reserved4 : 1;
|
||||
};
|
||||
struct { /* HP: Modem State */
|
||||
uint32_t reserved5 : 4;
|
||||
uint32_t hp_sleep2modem_backup_modem_clk_code : 2;
|
||||
uint32_t reserved6 : 8;
|
||||
uint32_t hp_sleep2modem_backup_clk_sel : 2;
|
||||
uint32_t reserved8 : 4;
|
||||
uint32_t hp_sleep2modem_backup_mode : 5;
|
||||
uint32_t reserved9 : 4;
|
||||
uint32_t hp_sleep2modem_backup_en : 1;
|
||||
uint32_t reserved10 : 2;
|
||||
};
|
||||
struct { /* HP: Sleep State */
|
||||
uint32_t reserved11 : 6;
|
||||
uint32_t hp_modem2sleep_backup_modem_clk_code : 2;
|
||||
uint32_t hp_active2sleep_backup_modem_clk_code: 2;
|
||||
uint32_t reserved12 : 6;
|
||||
uint32_t hp_modem2sleep_backup_clk_sel : 2;
|
||||
uint32_t hp_active2sleep_backup_clk_sel : 2;
|
||||
uint32_t hp_modem2sleep_backup_mode : 5;
|
||||
uint32_t hp_active2sleep_backup_mode : 5;
|
||||
uint32_t hp_modem2sleep_backup_en : 1;
|
||||
uint32_t hp_active2sleep_backup_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_backup_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t dig_sysclk_nodiv: 1;
|
||||
uint32_t icg_sysclk_en : 1;
|
||||
uint32_t sysclk_slp_sel : 1;
|
||||
uint32_t icg_slp_sel : 1;
|
||||
uint32_t dig_sysclk_sel : 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_sysclk_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t power_det_bypass: 1;
|
||||
uint32_t reserved0 : 3;
|
||||
uint32_t lp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */
|
||||
uint32_t hp_dbias_vol : 5; /* Only HP_ACTIVE mode under hp system is valid */
|
||||
uint32_t dbias_sel : 1; /* Only HP_ACTIVE mode under hp system is valid */
|
||||
uint32_t dbias_init : 1; /* Only HP_ACTIVE mode under hp system is valid */
|
||||
uint32_t slp_mem_xpd : 1;
|
||||
uint32_t slp_logic_xpd : 1;
|
||||
uint32_t xpd : 1;
|
||||
uint32_t slp_mem_dbias : 4;
|
||||
uint32_t slp_logic_dbias : 4;
|
||||
uint32_t dbias : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_regulator0_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0: 8;
|
||||
uint32_t drv_b : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_regulator1_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 30;
|
||||
uint32_t xpd_xtalx2: 1;
|
||||
uint32_t xpd_xtal : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_xtal_reg_t;
|
||||
|
||||
typedef struct pmu_hp_hw_regmap {
|
||||
pmu_hp_dig_power_reg_t dig_power;
|
||||
uint32_t icg_func;
|
||||
uint32_t icg_apb;
|
||||
pmu_hp_icg_modem_reg_t icg_modem;
|
||||
pmu_hp_sys_cntl_reg_t syscntl;
|
||||
pmu_hp_clk_power_reg_t clk_power;
|
||||
pmu_hp_bias_reg_t bias;
|
||||
pmu_hp_backup_reg_t backup;
|
||||
uint32_t backup_clk;
|
||||
pmu_hp_sysclk_reg_t sysclk;
|
||||
pmu_hp_regulator0_reg_t regulator0;
|
||||
pmu_hp_regulator1_reg_t regulator1;
|
||||
pmu_hp_xtal_reg_t xtal;
|
||||
} pmu_hp_hw_regmap_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0: 21;
|
||||
uint32_t slp_xpd : 1;
|
||||
uint32_t xpd : 1;
|
||||
uint32_t slp_dbias: 4;
|
||||
uint32_t dbias : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_regulator0_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0: 28;
|
||||
uint32_t drv_b : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_regulator1_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 30;
|
||||
uint32_t xpd_xtalx2: 1;
|
||||
uint32_t xpd_xtal : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_xtal_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 23;
|
||||
uint32_t vdd_io_mode : 4;
|
||||
uint32_t bod_source_sel: 1;
|
||||
uint32_t vddbat_mode : 2;
|
||||
uint32_t mem_dslp : 1;
|
||||
uint32_t peri_pd_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_dig_power_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 27;
|
||||
uint32_t xpd_lppll : 1;
|
||||
uint32_t xpd_xtal32k: 1;
|
||||
uint32_t xpd_rc32k : 1;
|
||||
uint32_t xpd_fosc : 1;
|
||||
uint32_t pd_osc : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_clk_power_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 9;
|
||||
uint32_t dcdc_ccm_enb : 1;
|
||||
uint32_t dcdc_clear_rdy : 1;
|
||||
uint32_t dig_reg_dpcur_bias: 2;
|
||||
uint32_t dig_reg_dsfmos : 4;
|
||||
uint32_t dcm_vset : 5;
|
||||
uint32_t dcm_mode : 2;
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t xpd_bias : 1;
|
||||
uint32_t reserved2 : 3;
|
||||
uint32_t discnnt_dig_rtc : 1;
|
||||
uint32_t pd_cur : 1;
|
||||
uint32_t bias_sleep : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_bias_reg_t;
|
||||
|
||||
typedef struct pmu_lp_hw_regmap {
|
||||
pmu_lp_regulator0_reg_t regulator0;
|
||||
pmu_lp_regulator1_reg_t regulator1;
|
||||
pmu_lp_xtal_reg_t xtal; /* Only LP_SLEEP mode under lp system, xtal is valid */
|
||||
pmu_lp_dig_power_reg_t dig_power;
|
||||
pmu_lp_clk_power_reg_t clk_power;
|
||||
pmu_lp_bias_reg_t bias; /* Only LP_SLEEP mode under lp system, bias is valid */
|
||||
} pmu_lp_hw_regmap_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t tie_low_global_bbpll_icg : 1;
|
||||
uint32_t tie_low_global_xtal_icg : 1;
|
||||
uint32_t tie_low_i2c_retention : 1;
|
||||
uint32_t tie_low_xpd_bb_i2c : 1;
|
||||
uint32_t tie_low_xpd_bbpll_i2c : 1;
|
||||
uint32_t tie_low_xpd_bbpll : 1;
|
||||
uint32_t tie_low_xpd_xtal : 1;
|
||||
uint32_t tie_low_global_xtalx2_icg : 1;
|
||||
uint32_t tie_low_xpd_xtalx2 : 1;
|
||||
uint32_t reserved0 : 14;
|
||||
uint32_t tie_high_xtalx2 : 1;
|
||||
uint32_t tie_high_global_xtalx2_icg: 1;
|
||||
uint32_t tie_high_global_bbpll_icg : 1;
|
||||
uint32_t tie_high_global_xtal_icg : 1;
|
||||
uint32_t tie_high_i2c_retention : 1;
|
||||
uint32_t tie_high_xpd_bb_i2c : 1;
|
||||
uint32_t tie_high_xpd_bbpll_i2c : 1;
|
||||
uint32_t tie_high_xpd_bbpll : 1;
|
||||
uint32_t tie_high_xpd_xtal : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_imm_hp_clk_power_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 28;
|
||||
uint32_t update_dig_icg_switch: 1;
|
||||
uint32_t tie_low_icg_slp_sel : 1;
|
||||
uint32_t tie_high_icg_slp_sel : 1;
|
||||
uint32_t update_dig_sysclk_sel: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_imm_sleep_sysclk_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 31;
|
||||
uint32_t update_dig_icg_func_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_imm_hp_func_icg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 31;
|
||||
uint32_t update_dig_icg_apb_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_imm_hp_apb_icg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 31;
|
||||
uint32_t update_dig_icg_modem_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_imm_modem_icg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 30;
|
||||
uint32_t tie_low_lp_rootclk_sel : 1;
|
||||
uint32_t tie_high_lp_rootclk_sel: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_imm_lp_icg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t tie_high_dig_pad_slp_sel: 1;
|
||||
uint32_t tie_low_dig_pad_slp_sel : 1;
|
||||
uint32_t tie_high_lp_pad_hold_all: 1;
|
||||
uint32_t tie_low_lp_pad_hold_all : 1;
|
||||
uint32_t tie_high_hp_pad_hold_all: 1;
|
||||
uint32_t tie_low_hp_pad_hold_all : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_imm_pad_hold_all_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 30;
|
||||
uint32_t tie_high_i2c_iso_en: 1;
|
||||
uint32_t tie_low_i2c_iso_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_imm_i2c_isolate_reg_t;
|
||||
|
||||
typedef struct pmu_imm_hw_regmap {
|
||||
pmu_imm_hp_clk_power_reg_t clk_power;
|
||||
pmu_imm_sleep_sysclk_reg_t sleep_sysclk;
|
||||
pmu_imm_hp_func_icg_reg_t hp_func_icg;
|
||||
pmu_imm_hp_apb_icg_reg_t hp_apb_icg;
|
||||
pmu_imm_modem_icg_reg_t modem_icg;
|
||||
pmu_imm_lp_icg_reg_t lp_icg;
|
||||
pmu_imm_pad_hold_all_reg_t pad_hold_all;
|
||||
pmu_imm_i2c_isolate_reg_t i2c_iso;
|
||||
} pmu_imm_hw_regmap_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 5;
|
||||
uint32_t hp_powerdown_timer: 9;
|
||||
uint32_t hp_powerup_timer : 9;
|
||||
uint32_t hp_wait_timer : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_wait_timer0_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 9;
|
||||
uint32_t lp_powerdown_timer: 7;
|
||||
uint32_t lp_powerup_timer : 7;
|
||||
uint32_t lp_wait_timer : 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_wait_timer1_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t lp_iso_wait_timer: 8;
|
||||
uint32_t lp_rst_wait_timer: 8;
|
||||
uint32_t hp_iso_wait_timer: 8;
|
||||
uint32_t hp_rst_wait_timer: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_wait_timer2_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t force_reset : 1;
|
||||
uint32_t force_iso : 1;
|
||||
uint32_t force_pu : 1;
|
||||
uint32_t force_no_reset: 1;
|
||||
uint32_t force_no_iso : 1;
|
||||
uint32_t force_pd : 1;
|
||||
uint32_t mask : 5; /* Invalid of lp peripherals */
|
||||
uint32_t reserved0 : 16; /* Invalid of lp peripherals */
|
||||
uint32_t pd_mask : 5; /* Invalid of lp peripherals */
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_domain_cntl_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t force_hp_mem_iso : 4;
|
||||
uint32_t force_hp_mem_pd : 4;
|
||||
uint32_t reserved0 : 16;
|
||||
uint32_t force_hp_mem_no_iso: 4;
|
||||
uint32_t force_hp_mem_pu : 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_memory_cntl_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t mem2_pd_mask : 5;
|
||||
uint32_t mem1_pd_mask : 5;
|
||||
uint32_t mem0_pd_mask : 5;
|
||||
uint32_t reserved0 : 2;
|
||||
uint32_t mem2_mask : 5;
|
||||
uint32_t mem1_mask : 5;
|
||||
uint32_t mem0_mask : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_memory_mask_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t force_hp_pad_no_iso_all: 1;
|
||||
uint32_t force_hp_pad_iso_all : 1;
|
||||
uint32_t reserved0 : 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_hp_pad_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ldo_rdy : 1;
|
||||
uint32_t sw_en_xpd : 1;
|
||||
uint32_t sw_en_thru : 1;
|
||||
uint32_t sw_en_standby : 1;
|
||||
uint32_t sw_en_power_adjust: 1;
|
||||
uint32_t sw_en_endet : 1;
|
||||
uint32_t reserved0 : 16;
|
||||
uint32_t bypass_ldo_rdy : 1;
|
||||
uint32_t xpd : 1;
|
||||
uint32_t thru : 1;
|
||||
uint32_t standby : 1;
|
||||
uint32_t power_adjust : 4;
|
||||
uint32_t reserved1 : 1;
|
||||
uint32_t endet : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_flash_ldo_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 22;
|
||||
uint32_t ldo_sw_en_tiel : 1;
|
||||
uint32_t ldo_power_sel : 1;
|
||||
uint32_t ldo_sw_en_power_sel: 1;
|
||||
uint32_t ldo_wait_target : 4;
|
||||
uint32_t ldo_tiel_en : 1;
|
||||
uint32_t ldo_tiel : 1;
|
||||
uint32_t ldo_sw_update : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_vdd_flash_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t ldo_rdy : 1;
|
||||
uint32_t sw_en_xpd : 1;
|
||||
uint32_t reserved0 : 1;
|
||||
uint32_t sw_en_thru : 1;
|
||||
uint32_t sw_en_standby : 1;
|
||||
uint32_t sw_en_power_adjust: 1;
|
||||
uint32_t sw_en_endet : 1;
|
||||
uint32_t reserved1 : 15;
|
||||
uint32_t bypass_ldo_rdy : 1;
|
||||
uint32_t xpd : 1;
|
||||
uint32_t thru : 1;
|
||||
uint32_t standby : 1;
|
||||
uint32_t power_adjust : 4;
|
||||
uint32_t reserved2 : 1;
|
||||
uint32_t endet : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_io_ldo_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 23;
|
||||
uint32_t ldo_power_sel : 1;
|
||||
uint32_t ldo_sw_en_power_sel: 1;
|
||||
uint32_t reserved1 : 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_vdd_io_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t wait_xtal_stable: 16;
|
||||
uint32_t wait_pll_stable : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_power_clk_wait_cntl_reg_t;
|
||||
|
||||
typedef struct pmu_power_hw_regmap {
|
||||
pmu_power_wait_timer0_reg_t wait_timer0;
|
||||
pmu_power_wait_timer1_reg_t wait_timer1;
|
||||
pmu_power_wait_timer2_reg_t wait_timer2;
|
||||
pmu_power_domain_cntl_reg_t hp_pd[5]; /* Include TOP, HPAON, HPCPU, HPPERI and MODEM power domain */
|
||||
pmu_power_domain_cntl_reg_t lp_peri;
|
||||
pmu_power_memory_cntl_reg_t mem_cntl;
|
||||
pmu_power_memory_mask_reg_t mem_mask;
|
||||
pmu_power_hp_pad_reg_t hp_pad;
|
||||
pmu_power_flash_ldo_reg_t flash_ldo[2]; /* Include Flash 1p8 and 1p2 LDO */
|
||||
pmu_power_vdd_flash_reg_t vdd_flash;
|
||||
pmu_power_io_ldo_reg_t io_ldo;
|
||||
pmu_power_vdd_io_reg_t vdd_io;
|
||||
pmu_power_clk_wait_cntl_reg_t clk_wait;
|
||||
} pmu_power_hw_regmap_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t sleep_req: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_slp_wakeup_cntl0_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t sleep_reject_ena: 31;
|
||||
uint32_t slp_reject_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_slp_wakeup_cntl1_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t lp_min_slp_val: 8;
|
||||
uint32_t hp_min_slp_val: 8;
|
||||
uint32_t sleep_prt_sel : 2;
|
||||
uint32_t reserved0 : 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_slp_wakeup_cntl3_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 31;
|
||||
uint32_t slp_reject_cause_clr: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_slp_wakeup_cntl4_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modem_wait_target : 20;
|
||||
uint32_t reserved0 : 4;
|
||||
uint32_t lp_ana_wait_target: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_slp_wakeup_cntl5_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t soc_wakeup_wait : 20;
|
||||
uint32_t reserved0 : 10;
|
||||
uint32_t soc_wakeup_wait_cfg: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_slp_wakeup_cntl6_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 15;
|
||||
uint32_t ana_wait_clk_sel: 1;
|
||||
uint32_t ana_wait_target : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_slp_wakeup_cntl7_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t wakeup_cause: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_slp_wakeup_status0_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reject_cause: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_slp_wakeup_status1_reg_t;
|
||||
|
||||
typedef struct pmu_wakeup_hw_regmap {
|
||||
pmu_slp_wakeup_cntl0_reg_t cntl0;
|
||||
pmu_slp_wakeup_cntl1_reg_t cntl1;
|
||||
uint32_t cntl2;
|
||||
pmu_slp_wakeup_cntl3_reg_t cntl3;
|
||||
pmu_slp_wakeup_cntl4_reg_t cntl4;
|
||||
pmu_slp_wakeup_cntl5_reg_t cntl5;
|
||||
pmu_slp_wakeup_cntl6_reg_t cntl6;
|
||||
pmu_slp_wakeup_cntl7_reg_t cntl7;
|
||||
pmu_slp_wakeup_status0_reg_t status0;
|
||||
pmu_slp_wakeup_status1_reg_t status1;
|
||||
} pmu_wakeup_hw_regmap_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t i2c_por_wait_target: 8;
|
||||
uint32_t reserved0 : 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_clk_poweron_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t modify_icg_cntl_wait: 8;
|
||||
uint32_t switch_icg_cntl_wait: 8;
|
||||
uint32_t reserved0 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_clk_cntl_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t por_done : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_por_status_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 26;
|
||||
uint32_t xpd_force_rftx : 1;
|
||||
uint32_t xpd_perif_i2c : 1;
|
||||
uint32_t xpd_rftx_i2c : 1;
|
||||
uint32_t xpd_rfrx_i2c : 1;
|
||||
uint32_t xpd_rfpll : 1;
|
||||
uint32_t xpd_force_rfpll: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_rf_pwc_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t vddbat_mode : 2;
|
||||
uint32_t reserved0 : 29;
|
||||
uint32_t vddbat_sw_update: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_vddbat_cfg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 31;
|
||||
uint32_t backup_sysclk_nodiv: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_backup_cfg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 27;
|
||||
uint32_t lp_cpu_exc : 1;
|
||||
uint32_t sdio_idle : 1;
|
||||
uint32_t sw : 1;
|
||||
uint32_t soc_sleep_reject: 1;
|
||||
uint32_t soc_wakeup : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_intr_reg_t;
|
||||
|
||||
typedef struct pmu_hp_ext_hw_regmap {
|
||||
pmu_hp_clk_poweron_reg_t clk_poweron;
|
||||
pmu_hp_clk_cntl_reg_t clk_cntl;
|
||||
pmu_por_status_reg_t por_status;
|
||||
pmu_rf_pwc_reg_t rf_pwc;
|
||||
pmu_vddbat_cfg_reg_t vddbat_cfg;
|
||||
pmu_backup_cfg_reg_t backup_cfg;
|
||||
pmu_hp_intr_reg_t int_raw;
|
||||
pmu_hp_intr_reg_t int_st;
|
||||
pmu_hp_intr_reg_t int_ena;
|
||||
pmu_hp_intr_reg_t int_clr;
|
||||
} pmu_hp_ext_hw_regmap_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 20;
|
||||
uint32_t lp_cpu_wakeup : 1;
|
||||
uint32_t modem_switch_active_end : 1;
|
||||
uint32_t sleep_switch_active_end : 1;
|
||||
uint32_t sleep_switch_modem_end : 1;
|
||||
uint32_t modem_switch_sleep_end : 1;
|
||||
uint32_t active_switch_sleep_end : 1;
|
||||
uint32_t modem_switch_active_start: 1;
|
||||
uint32_t sleep_switch_active_start: 1;
|
||||
uint32_t sleep_switch_modem_start : 1;
|
||||
uint32_t modem_switch_sleep_start : 1;
|
||||
uint32_t active_switch_sleep_start: 1;
|
||||
uint32_t hp_sw_trigger : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_intr_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t waiti_rdy : 1;
|
||||
uint32_t stall_rdy : 1;
|
||||
uint32_t reserved0 : 16;
|
||||
uint32_t force_stall : 1;
|
||||
uint32_t slp_waiti_flag_en : 1;
|
||||
uint32_t slp_stall_flag_en : 1;
|
||||
uint32_t slp_stall_wait : 8;
|
||||
uint32_t slp_stall_en : 1;
|
||||
uint32_t slp_reset_en : 1;
|
||||
uint32_t slp_bypass_intr_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_cpu_pwr0_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t wakeup_en: 16;
|
||||
uint32_t reserved0: 15;
|
||||
uint32_t sleep_req: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_cpu_pwr1_reg_t;
|
||||
|
||||
typedef struct pmu_lp_ext_hw_regmap {
|
||||
pmu_lp_intr_reg_t int_raw;
|
||||
pmu_lp_intr_reg_t int_st;
|
||||
pmu_lp_intr_reg_t int_ena;
|
||||
pmu_lp_intr_reg_t int_clr;
|
||||
pmu_lp_cpu_pwr0_reg_t pwr0;
|
||||
pmu_lp_cpu_pwr1_reg_t pwr1;
|
||||
} pmu_lp_ext_hw_regmap_t;
|
||||
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 30;
|
||||
uint32_t lp_trigger_hp: 1;
|
||||
uint32_t hp_trigger_lp: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_lp_cpu_comm_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 31;
|
||||
uint32_t dig_regulator_en_cal: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_regulator_cfg_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 11;
|
||||
uint32_t main_last_st_state: 7;
|
||||
uint32_t main_tar_st_state : 7;
|
||||
uint32_t main_cur_st_state : 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_main_state_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 13;
|
||||
uint32_t backup_st_state: 5;
|
||||
uint32_t lp_pwr_st_state: 5;
|
||||
uint32_t hp_pwr_st_state: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_pwr_state_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t stable_xpd_bbpll_state : 1;
|
||||
uint32_t stable_xpd_xtal_state : 1;
|
||||
uint32_t reserved0 : 13;
|
||||
uint32_t sysclk_slp_sel_state : 1;
|
||||
uint32_t sysclk_sel_state : 2;
|
||||
uint32_t sysclk_nodiv_state : 1;
|
||||
uint32_t icg_sysclk_en_state : 1;
|
||||
uint32_t icg_modem_switch_state : 1;
|
||||
uint32_t icg_modem_code_state : 2;
|
||||
uint32_t icg_slp_sel_state : 1;
|
||||
uint32_t icg_global_xtal_state : 1;
|
||||
uint32_t icg_global_pll_state : 1;
|
||||
uint32_t ana_i2c_iso_en_state : 1;
|
||||
uint32_t ana_i2c_retention_state: 1;
|
||||
uint32_t ana_xpd_bb_i2c_state : 1;
|
||||
uint32_t ana_xpd_bbpll_i2c_state: 1;
|
||||
uint32_t ana_xpd_bbpll_state : 1;
|
||||
uint32_t ana_xpd_xtal_state : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_clk_state0_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t icg_func_en_state: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_clk_state1_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t icg_apb_en_state: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_clk_state2_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t dsfmos_use_por : 1;
|
||||
uint32_t reserved0 : 21;
|
||||
uint32_t dcdc_dcm_update : 1;
|
||||
uint32_t dcdc_pcur_limit : 3;
|
||||
uint32_t dcdc_bias_cal_done: 1;
|
||||
uint32_t dcdc_ccm_sw_en : 1;
|
||||
uint32_t dcdc_vcm_enb : 1;
|
||||
uint32_t dcdc_ccm_rdy : 1;
|
||||
uint32_t dcdc_vcm_rdy : 1;
|
||||
uint32_t dcdc_rdy_clr : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_dcm_ctrl_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved0 : 24;
|
||||
uint32_t dcdc_boost_ccm_ctrlen: 1;
|
||||
uint32_t dcdc_boost_ccm_enb : 1;
|
||||
uint32_t dcdc_boost_en : 1;
|
||||
uint32_t dcdc_boost_dreg : 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_dcm_boost_ctrl_reg_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t touch_sleep_cycles : 16;
|
||||
uint32_t reserved0 : 5;
|
||||
uint32_t touch_wait_cycles : 9;
|
||||
uint32_t touch_sleep_timer_en: 1;
|
||||
uint32_t touch_force_done : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_touch_pwr_ctrl_reg_t;
|
||||
|
||||
typedef struct pmu_dev {
|
||||
volatile pmu_hp_hw_regmap_t hp_sys[3];
|
||||
volatile pmu_lp_hw_regmap_t lp_sys[2];
|
||||
volatile pmu_imm_hw_regmap_t imm;
|
||||
volatile pmu_power_hw_regmap_t power;
|
||||
volatile pmu_wakeup_hw_regmap_t wakeup;
|
||||
volatile pmu_hp_ext_hw_regmap_t hp_ext;
|
||||
volatile pmu_lp_ext_hw_regmap_t lp_ext;
|
||||
|
||||
volatile pmu_hp_lp_cpu_comm_reg_t hp_lp_cpu_common;
|
||||
volatile pmu_hp_regulator_cfg_reg_t hp_regulator_cfg;
|
||||
|
||||
volatile pmu_main_state_reg_t main_state;
|
||||
volatile pmu_pwr_state_reg_t pwr_state;
|
||||
volatile pmu_clk_state0_reg_t clk_state0;
|
||||
volatile pmu_clk_state1_reg_t clk_state1;
|
||||
volatile pmu_clk_state2_reg_t clk_state2;
|
||||
|
||||
volatile pmu_dcm_ctrl_reg_t dcm_ctrl;
|
||||
volatile pmu_dcm_boost_ctrl_reg_t dcm_boost_ctrl;
|
||||
volatile pmu_touch_pwr_ctrl_reg_t touch_pwr_ctrl;
|
||||
|
||||
uint32_t reserved[142];
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t pmu_date: 31;
|
||||
uint32_t clk_en : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} pmu_dev_t;
|
||||
|
||||
extern pmu_dev_t PMU;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(pmu_dev_t) == 0x400, "Invalid size of pmu_dev_t structure");
|
||||
|
||||
_Static_assert(offsetof(pmu_dev_t, reserved) == (PMU_TOUCH_PWR_CTRL_REG - DR_REG_PMU_BASE) + 4, "Invalid size of pmu_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user