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release/v5.5
Commit Graph

1562 Commits

Author SHA1 Message Date
armando 0cb42beabf fix(spm): rename scp (scratchpad) to spm (scratchpad memory) 2026-03-31 09:24:53 +08:00
armando 55c462ccab change(mem): deprecated tcm and added scp memory utils 2026-03-31 09:22:11 +08:00
Alexey Lapshin dfafd6fc2a fix(esp_system): xtensa: refactor linker scripts and reduce binary size for C++ apps 2026-03-16 14:39:26 +08:00
Alexey Lapshin 6bd63cc577 feat(esp_system): riscv: refactor linker scripts to reduce duplicated code 2026-03-16 14:39:26 +08:00
Song Ruo Jing 5698be672b feat(mspi): support 120MHz flash and psram for esp32c61 2026-03-13 16:27:17 +08:00
Jiang Jiang Jian fdfcae24e3 Merge branch 'feat/support_esp32p4_rev3.1_lowpower_v5.5' into 'release/v5.5' 
feat: esp32p4 eco6 lowpower support and leakage optimization (v5.5)

See merge request espressif/esp-idf!45532
 2026-03-06 19:54:06 +08:00
Alexey Gerenkov 0c7eac2565 Merge branch 'feature/picolibc_v5.5' into 'release/v5.5' 
feat(build): add Picolibc support (v5.5)

See merge request espressif/esp-idf!44108
 2026-02-26 18:12:58 +08:00
Fu Hanxi 124a1d3b82 ci: backport master to 5.5 2026-02-25 11:38:38 +01:00
wuzhenghui 33794f6b52 feat(esp_hw_support): set USB2.0 phy to suspend mode at startup for active power saving 2026-02-10 16:18:36 +08:00
Xiao Xufeng 07cc2c7d3b fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption 
This reverts commit 7145fc9558.
 2026-02-06 11:44:52 +08:00
Alexey Lapshin 0b3929d0d9 feat(esp_libc): add full support for picolibc 2026-01-30 23:39:53 +07:00
armando 4b884d0f46 fix(kconfig): fixed default cpu freq issue on <rev3 2026-01-22 10:00:52 +08:00
Michael (XIAO Xufeng) 3cf945bdbc Merge branch 'fix/p4_min_rev_usage_v5.5' into 'release/v5.5' 
P4: fix wrong rev_min usage in rom and other places (v5.5)

See merge request espressif/esp-idf!45224
 2026-01-21 00:47:30 +08:00
Jiang Jiang Jian e0c90dba02 Merge branch 'feat/freq_change_enc_write_c5_v5.5' into 'release/v5.5' 
Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption" (v5.5)

See merge request espressif/esp-idf!45167
 2026-01-20 21:35:01 +08:00
Jiang Jiang Jian 18ce7a64d5 Merge branch 'feature/support_chip752_pvt_auto_dbias_backport_v5.5' into 'release/v5.5' 
feat(c5): support chip752 pvt auto dbias (v5.5)

See merge request espressif/esp-idf!45208
 2026-01-20 21:34:21 +08:00
Alexey Gerenkov bc7a18fe63 Merge branch 'fix/esp32p4_eco5_multicore_wfi_autoclock_gating_v5.5' into 'release/v5.5' 
fix(esp_hw_support): enable core1 auto clock gating for esp32p4 rev3+ multicore (v5.5)

See merge request espressif/esp-idf!44256
 2026-01-20 00:21:27 +08:00
Xiao Xufeng bb79e6f246 fix(esp32p4): fix efuse, encryption and other rev_min usage 2026-01-19 17:53:51 +08:00
Xiao Xufeng 3d22ac034c fix(esp32p4): fix rom and ld misuse min_rev 2026-01-19 17:53:34 +08:00
Jiang Jiang Jian a3ce1fc579 Merge branch 'feature/support_7.6.1_pvt_auto_dbias_v5.5' into 'release/v5.5' 
feat(esp32c6): auto adjust LDO voltage using pvt function (v5.5)

See merge request espressif/esp-idf!44102
 2026-01-19 14:57:11 +08:00
yanzihan@espressif.com 51adb83f39 feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32c5 v5.5 2026-01-19 14:25:25 +08:00
morris c680ab6288 Merge branch 'fix/esp32_flash_cache_crash_v5.5' into 'release/v5.5' 
fix(hw_support): Fix crash when reconfiguring flash from 40 to 80 MHz on ESP32 (v5.5)

See merge request espressif/esp-idf!44904
 2026-01-18 23:41:48 +08:00
Jiang Jiang Jian 9d80cb0d95 Merge branch 'fix/fix_secure_boot_fast_wake_feature_v5.5' into 'release/v5.5' 
fix(esp_system): fix ROM secure boot fast wake feature (v5.5)

See merge request espressif/esp-idf!45016
 2026-01-17 17:17:59 +08:00
Samuel Obuch d9a7ff38f6 fix(esp_hw_support): enable core1 auto clock gating for esp32p4 rev3+ multicore 2026-01-16 03:54:13 +08:00
Xiao Xufeng ccaaa3a923 refactor(startup): make flash_init_state static 2026-01-15 23:54:49 +08:00
Mattias Schäffersmann 02a3b294a5 fix(hw_support): Fix crash when reconfiguring flash from 40 to 80 MHz 
Reading from the flash while it is being reconfigured leads to data
corruption and a crash when the reconfiguration code is located in flash.
This is only an issue if a device has a bootloader that runs with 40 MHz
flash and an application flashed via OTA that runs with 80 MHz flash.
If bootloader and application run with the same flash speed, the
reconfiguration is basically a no-op and no data corruption occurs.
Fix reconfiguration by placing the code back into IRAM.

Issue introduced in: 7549d08

Closes: https://github.com/espressif/esp-idf/pull/17905
 2026-01-15 23:54:49 +08:00
Xiao Xufeng 343fbafafe Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption" 
This reverts commit cca0ac8c56.
 2026-01-15 23:52:41 +08:00
hebinglin 17c110d640 change(esp_driver): set cases with toppd check only run in esp32c5eco3 rather than eco2 2026-01-15 17:04:17 +08:00
hebinglin 902d13d489 change(esp_hw_support): remove sleep_mmu_retention related flow for esp32c5 eco1 2026-01-15 17:04:17 +08:00
hebinglin 69ced7c670 revert(unit-test): filter top domain power down check for some sleep test cases 
This reverts commit c6c2948a99.
 2026-01-15 17:04:17 +08:00
zlq 873afefba8 feat(esp32c6): auto adjust LDO voltage using pvt function 2026-01-15 14:46:52 +08:00
wuzhenghui 67a62f45ce fix(esp_system): fix rom secure boot fast wake feature for c5/c6/h2/h21 2026-01-12 18:11:59 +08:00
Li Shuai 1f95182e55 fix(ld): fix cannot move location counter backwards (from 3fc88000 to 3fc87a00) 2025-12-31 17:17:39 +08:00
Jiang Jiang Jian 2d344bc185 Merge branch 'fix/fix_mspi_reset_order_v5.5' into 'release/v5.5' 
fix(esp_system): fix c61 mspi core/axi reset order (v5.5)

See merge request espressif/esp-idf!44097
 2025-12-30 10:20:56 +08:00
Marius Vikhammer be52835d21 fix(system): removed the exe flag from psram memory for esp32 
extern_ram_seg segment was marked as RWX in the linker script
even though we cannot run code from PSRAM on ESP32.

This is a link-time check, and actual CPU RWX permissions are
controlled seperately so this has no practical implications,
but it could mistakenly be remarked upon during security scans
or checks by customers.
 2025-12-29 16:39:06 +08:00
Xiao Xufeng 08f5f0d66b fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption 
This reverts commit 7145fc9558.
 2025-12-24 02:31:57 +08:00
Xiao Xufeng 187f43a3bb Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption" 
This reverts commit 3c5d2e6b58.
 2025-12-17 03:33:30 +08:00
Xiao Xufeng faf6cc4f84 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes 
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
 2025-12-17 03:33:29 +08:00
wuzhenghui 3146ab33ab fix(esp_system): fix c61 mspi core/axi reset order 2025-12-10 12:16:33 +08:00
Jiang Jiang Jian ddb9f5d9dc Merge branch 'fix/fix_mspi_write_stuck_after_reset_v5.5' into 'release/v5.5' 
fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 (v5.5)

See merge request espressif/esp-idf!43732
 2025-12-04 10:34:56 +08:00
Jiang Jiang Jian a5cc517d31 Merge branch 'fix/core_system_fixes_for_p4_eco5_v5_5' into 'release/v5.5' 
Core System fixes for p4 eco5 (v5.5)

See merge request espressif/esp-idf!43726
 2025-12-02 19:56:22 +08:00
sibeibei 83acb84d8a bugfix: clear regdma status when restart 2025-12-02 13:34:21 +08:00
wuzhenghui 104145de7f fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 2025-12-02 13:34:17 +08:00
Xiao Xufeng 09aafffb2e esp_system: increase bootloader partition size in examples using framepointer 2025-12-01 15:31:44 +08:00
Sudeep Mohanty 0f268f0920 fix(system): Fix linker error for esp32p4 C++ constructors 
This commit fixes an issue where C++ constructor priority array symbols
(__init_priority_array_start/end) were undefined when linking.
 2025-11-27 11:20:43 +05:30
Sudeep Mohanty ccab591764 ci(esp_system): Re-enable esp_system tests for esp32p4 2025-11-27 11:20:43 +05:30
morris 1d5fcc6d2e Merge branch 'bugfix/uart_related_backports_v5.5' into 'release/v5.5' 
fix(uart): some related uart backports (v5.5)

See merge request espressif/esp-idf!43617
 2025-11-27 10:52:38 +08:00
Marius Vikhammer 0392a67f07 fix(system): fixed constructors not working properly on P4 ECO5 2025-11-26 11:40:01 +05:30
Marius Vikhammer 91e8dc6b53 fix(lp-core): fixed rtc mem conflict on p4 eco5 between app and ULP 2025-11-26 11:40:01 +05:30
Song Ruo Jing 3228998165 fix(uart): fix some wdt get triggered due to uart sclk not exist on C5 
Interrupt wdt would get triggered on uart_driver_install if uart driver was deleted before
Closes https://github.com/espressif/esp-idf/issues/17779

RTC wdt would get triggered on esp_restart if uart driver was deleted before
 2025-11-24 11:41:26 +08:00
Song Ruo Jing fb20e147d5 fix(console): release default console UART pins if console is switched in bootloader 
Also print out console UART pin number in app cpu_startup stage

Closes https://github.com/espressif/esp-idf/issues/16764
Closes https://github.com/espressif/esp-idf/issues/17459
 2025-11-21 22:11:25 +08:00