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1530 Commits

Author SHA1 Message Date
Jiang Jiang Jian 2d344bc185 Merge branch 'fix/fix_mspi_reset_order_v5.5' into 'release/v5.5' 
fix(esp_system): fix c61 mspi core/axi reset order (v5.5)

See merge request espressif/esp-idf!44097
 2025-12-30 10:20:56 +08:00
Marius Vikhammer be52835d21 fix(system): removed the exe flag from psram memory for esp32 
extern_ram_seg segment was marked as RWX in the linker script
even though we cannot run code from PSRAM on ESP32.

This is a link-time check, and actual CPU RWX permissions are
controlled seperately so this has no practical implications,
but it could mistakenly be remarked upon during security scans
or checks by customers.
 2025-12-29 16:39:06 +08:00
Xiao Xufeng 08f5f0d66b fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption 
This reverts commit 7145fc9558.
 2025-12-24 02:31:57 +08:00
Xiao Xufeng 187f43a3bb Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption" 
This reverts commit 3c5d2e6b58.
 2025-12-17 03:33:30 +08:00
Xiao Xufeng faf6cc4f84 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes 
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
 2025-12-17 03:33:29 +08:00
wuzhenghui 3146ab33ab fix(esp_system): fix c61 mspi core/axi reset order 2025-12-10 12:16:33 +08:00
Jiang Jiang Jian ddb9f5d9dc Merge branch 'fix/fix_mspi_write_stuck_after_reset_v5.5' into 'release/v5.5' 
fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 (v5.5)

See merge request espressif/esp-idf!43732
 2025-12-04 10:34:56 +08:00
Jiang Jiang Jian a5cc517d31 Merge branch 'fix/core_system_fixes_for_p4_eco5_v5_5' into 'release/v5.5' 
Core System fixes for p4 eco5 (v5.5)

See merge request espressif/esp-idf!43726
 2025-12-02 19:56:22 +08:00
sibeibei 83acb84d8a bugfix: clear regdma status when restart 2025-12-02 13:34:21 +08:00
wuzhenghui 104145de7f fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61 2025-12-02 13:34:17 +08:00
Xiao Xufeng 09aafffb2e esp_system: increase bootloader partition size in examples using framepointer 2025-12-01 15:31:44 +08:00
Sudeep Mohanty 0f268f0920 fix(system): Fix linker error for esp32p4 C++ constructors 
This commit fixes an issue where C++ constructor priority array symbols
(__init_priority_array_start/end) were undefined when linking.
 2025-11-27 11:20:43 +05:30
Sudeep Mohanty ccab591764 ci(esp_system): Re-enable esp_system tests for esp32p4 2025-11-27 11:20:43 +05:30
morris 1d5fcc6d2e Merge branch 'bugfix/uart_related_backports_v5.5' into 'release/v5.5' 
fix(uart): some related uart backports (v5.5)

See merge request espressif/esp-idf!43617
 2025-11-27 10:52:38 +08:00
Marius Vikhammer 0392a67f07 fix(system): fixed constructors not working properly on P4 ECO5 2025-11-26 11:40:01 +05:30
Marius Vikhammer 91e8dc6b53 fix(lp-core): fixed rtc mem conflict on p4 eco5 between app and ULP 2025-11-26 11:40:01 +05:30
Song Ruo Jing 3228998165 fix(uart): fix some wdt get triggered due to uart sclk not exist on C5 
Interrupt wdt would get triggered on uart_driver_install if uart driver was deleted before
Closes https://github.com/espressif/esp-idf/issues/17779

RTC wdt would get triggered on esp_restart if uart driver was deleted before
 2025-11-24 11:41:26 +08:00
Song Ruo Jing fb20e147d5 fix(console): release default console UART pins if console is switched in bootloader 
Also print out console UART pin number in app cpu_startup stage

Closes https://github.com/espressif/esp-idf/issues/16764
Closes https://github.com/espressif/esp-idf/issues/17459
 2025-11-21 22:11:25 +08:00
armando cdff2570c7 ci(p4): disable p4 rev3 invalid tests temporarily 2025-11-20 11:33:36 +08:00
Jiang Jiang Jian 29e9e7ebee Merge branch 'feat/support_p4_unicore_auto_clock_gating_v5.5' into 'release/v5.5' 
feat(esp_hw_support): support unicore auto clock gating for esp32p4 rev3+ (v5.5)

See merge request espressif/esp-idf!43370
 2025-11-17 19:07:39 +08:00
Jiang Jiang Jian 376f396e20 Merge branch 'bugfix/esp32c5_encrypted_flash_write_v5.5' into 'release/v5.5' 
fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption (v5.5)

See merge request espressif/esp-idf!43326
 2025-11-17 15:02:40 +08:00
Jiang Jiang Jian 01b9a1dd18 Merge branch 'fix/fix_xtal32k_power_breaks_adc_v5.5' into 'release/v5.5' 
fix(esp_system): fix XTAL32K power breaks ADC function on 32k XTAL clock pin (v5.5)

See merge request espressif/esp-idf!43297
 2025-11-14 15:31:04 +08:00
wuzhenghui 9e06691c52 feat(esp_hw_support): support unicore auto clock gating for esp32p4 rev3+ 2025-11-14 14:08:52 +08:00
Mahavir Jain 3fd00b4d80 fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption 
Encrypted flash write operation sometimes result in random corruption in
certain bytes. Root cause points to sudden current surge due to involvement of
encryption block overwhelming LDO supply. More details will be provided
in the ESP32-C5 SoC Errata document.

This fix limits the CPU clock to 160MHz for flash encryption enabled
case. Failing encrypted flash write tests could successfully pass in
this configuration. Going ahead, a dynamic clock adjustment in flash
driver will be considered to mitigate this issue.
 2025-11-13 13:26:06 +05:30
wuzhenghui 7adb3a5a2e fix(esp_system): fix XTAL32K power breaks ADC function on 32k XTAL clock pin 2025-11-13 14:17:34 +08:00
Song Ruo Jing ea6ed237d2 fix(clk): 400MHz CPU should still be selectable on ESP32-P4 less than rev3 2025-11-13 11:36:22 +08:00
Marius Vikhammer 8410210c9a Merge branch 'fix/eh_frame_parser_warnings_v5.5' into 'release/v5.5' 
fix(esp_system): fix potential warnings related to array size in .eh_frame parser (backport v5.5)

See merge request espressif/esp-idf!41983
 2025-11-06 13:45:45 +08:00
Omar Chebib 1bbf16c5bc fix(esp_system): fix potential warnings related to array size in .eh_frame parser 2025-11-05 11:26:24 +08:00
Omar Chebib cc0a98a3c4 fix(esp_system): prevent .eh_frame-based unwinding from looping indefinitely 2025-11-05 10:04:00 +08:00
Jiang Jiang Jian 9602933fad Merge branch 'fix/p4_rev3_further_fixes_v5.5' into 'release/v5.5' 
fix(esp_hw_support): p4 rev3 further fixes  (v5.5)

See merge request espressif/esp-idf!42942
 2025-10-31 10:00:36 +08:00
Jiang Jiang Jian 24a36e5c01 Merge branch 'fix/cdcacm-callback-placement_v5.5' into 'release/v5.5' 
fix(esp_vfs_console): Update placement of cdcacm_xx_cb when ETS print enabled (v5.5)

See merge request espressif/esp-idf!41330
 2025-10-31 07:10:47 +08:00
Jiang Jiang Jian d7bdd17dba Merge branch 'fix/fix_32k_config_revoke_breaks_io_holding_v5.5' into 'release/v5.5' 
fix(esp_system): fix ext 32k io revoking breaks sleep io holding (v5.5)

See merge request espressif/esp-idf!42495
 2025-10-31 06:53:44 +08:00
wuzhenghui 3ee348fe52 fix(esp_hw_support): add p4 rev3.0 MSPI workaround for deepsleep 2025-10-30 19:09:44 +08:00
Jiang Jiang Jian 7109c7b939 Merge branch 'feature/ipc_allows_recursion_calls_v5.5' into 'release/v5.5' 
feat(ipc): Allow IPC recursion calls in esp_ipc_call (v5.5)

See merge request espressif/esp-idf!41938
 2025-10-30 13:59:39 +08:00
wuzhenghui 96aef65a2d fix(esp_system): fix ext 32k io revoking breaks sleep io holding 2025-10-28 18:54:20 +08:00
morris 2f63581f51 Merge branch 'bugfix/usb_dp_pin_unusable_after_cpu_reset_v5.5' into 'release/v5.5' 
fix(gpio): fix USB DP pin unusable after CPU reset for S3/C3 (v5.5)

See merge request espressif/esp-idf!42800
 2025-10-28 10:00:46 +08:00
morris a0de5f7387 Merge branch 'feature/esp32p4_eco5_support_v5.5' into 'release/v5.5' 
feat(gpio/ledc/uart/2ddma/ppa): ESP32P4 ECO5 related updates (v5.5)

See merge request espressif/esp-idf!42816
 2025-10-27 15:50:42 +08:00
Xiao Xufeng 5a4ff6bb6a dma: fixed issue that DMA are not reset when CPU reset 
When DMA keep writing the memory, some data may be corrupted after reset. For example, the stack of bootloader may be overwritten and failed to boot until a higher scope of reset (Core).
 2025-10-23 21:39:09 +08:00
Song Ruo Jing 912c24eb09 fix(gpio): fix USB DP pin unusable after CPU reset for S3/C3 
Closes https://github.com/espressif/esp-idf/issues/17488
 2025-10-23 15:07:25 +08:00
Song Ruo Jing e69eeb7355 feat(2ddma): ESP32P4 ECO5 2DDMA related updates 
Added one more pair of 2DDMA channels
Priority bit width increased corespondingly
Added three new CSC modes for RX channel 0
 2025-10-22 20:05:59 +08:00
Song Ruo Jing e71732139a fix(clk): allow P4 CPU clk freq can auto switch between 360/400MHz according to revision 2025-10-22 20:05:59 +08:00
Jiang Jiang Jian 438046d809 Merge branch 'fix/fix_esp32c5_xtal32k_clock_lost_in_sleep_v5.5' into 'release/v5.5' 
fix(esp_system): manage slow clock sleep pd in select_rtc_slow_clk (v5.5)

See merge request espressif/esp-idf!42494
 2025-10-20 14:36:47 +08:00
Konstantin Kondrashov 37ebf6793e feat(ipc): Allow IPC recursion calls in esp_ipc_call 2025-10-20 14:25:24 +08:00
Mahavir Jain ea36c4f609 Merge branch 'feature/esp_tee_c5_v5.5' into 'release/v5.5' 
feat(esp_tee): Initial support for ESP32-C5 and related changes (v5.5)

See merge request espressif/esp-idf!42357
 2025-10-16 09:39:23 +05:30
Laukik Hase 508a659001 feat(esp_tee): Support for ESP32-C5 - the rest of the components 2025-10-14 10:12:11 +05:30
armando e6d4eec507 feat(p4): p4 rev3 real chip support 2025-10-13 15:25:23 +08:00
wuzhenghui 3d3b287672 fix(esp_system): manage slow clock sleep pd in select_rtc_slow_clk 2025-10-10 20:04:58 +08:00
Chen Jichang 69c31289ad fix(clk): clear force_on reg for cache 2025-10-09 13:19:46 +08:00
Guillaume Souchere 175e885555 fix(esp_vfs_console): Update placement of cdcacm_xx_cb when ETS print enabled 2025-10-07 08:26:54 +02:00
Sudeep Mohanty 22bec9eed7 fix(panic_handler): Fixed a issue where the system reboots before halt 
This commit fixes an issue where the panic handler may reboot even if it
is configured to halt the CPU.

Closes https://github.com/espressif/esp-idf/issues/17260
 2025-08-14 11:00:45 +02:00