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feat(mcpwm): support mcpwm on esp32h21

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This commit is contained in:
Chen Chen
2025-11-14 09:42:39 +08:00
committed by morris
parent 1275fb1f42
commit c6ab28f336
25 changed files with 2166 additions and 1765 deletions
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components/esp_driver_mcpwm/test_apps/mcpwm/README.md
+2 -2
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
components/esp_hal_mcpwm/esp32/include/hal/mcpwm_ll.h
-6
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@@ -4,12 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32 MCPWM register operations
#pragma once
components/esp_hal_mcpwm/esp32c5/include/hal/mcpwm_ll.h
+1 -1
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@@ -28,7 +28,7 @@ extern "C" {
#define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : NULL)
// MCPWM capabilities
#define MCPWM_LL_GROUP_NUM (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_GROUP_NUM (1) ///< 1 MCPWM group on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
components/esp_hal_mcpwm/esp32c6/include/hal/mcpwm_ll.h
+1 -7
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@@ -4,12 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32-C6 MCPWM register operations
#pragma once
@@ -35,7 +29,7 @@ extern "C" {
#define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : NULL)
// MCPWM capabilities
#define MCPWM_LL_GROUP_NUM (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_GROUP_NUM (1) ///< 1 MCPWM group on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
components/esp_hal_mcpwm/esp32h2/include/hal/mcpwm_ll.h
+1 -7
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@@ -4,12 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
#pragma once
#include <stdbool.h>
@@ -33,7 +27,7 @@ extern "C" {
#define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : NULL)
// MCPWM capabilities
#define MCPWM_LL_GROUP_NUM (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_GROUP_NUM (1) ///< 1 MCPWM group on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c
-1
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@@ -4,7 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "hal/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
components/esp_hal_mcpwm/esp32h21/include/hal/mcpwm_ll.h
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components/esp_hal_mcpwm/esp32h21/mcpwm_periph.c
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@@ -0,0 +1,129 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
{
.module_name = "MCPWM0",
.irq_id = ETS_PWM_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
}
};
/**
* MCPWM Registers to be saved during sleep retention
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 60
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4)
static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE, MCPWM_RETENTION_REGS_BASE,
MCPWM_RETENTION_REGS_CNT, 0, 0,
mcpwm_regs_map[0], mcpwm_regs_map[1],
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2)
},
// restore stage: trigger a forced update of all active registers
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
MCPWM_UPDATE_CFG_REG, MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
MCPWM_UPDATE_CFG_REG, 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2)
},
};
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[1] = {
[0] = {
.regdma_entry_array = mcpwm_regs_retention,
.array_size = ARRAY_SIZE(mcpwm_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
};
components/esp_hal_mcpwm/esp32h4/include/hal/mcpwm_ll.h
+1 -1
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@@ -28,7 +28,7 @@ extern "C" {
#define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : &MCPWM1)
// MCPWM capabilities
#define MCPWM_LL_GROUP_NUM (2U) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_GROUP_NUM (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
components/esp_hal_mcpwm/esp32p4/include/hal/mcpwm_ll.h
+1 -7
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@@ -4,12 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32-P4 MCPWM register operations
#pragma once
@@ -36,7 +30,7 @@ extern "C" {
#define MCPWM_LL_GET_HW(ID) (((ID) == 0) ? &MCPWM0 : &MCPWM1)
// MCPWM capabilities
#define MCPWM_LL_GROUP_NUM (2U) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_GROUP_NUM (2) ///< 2 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
#define MCPWM_LL_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
#define MCPWM_LL_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define MCPWM_LL_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
components/esp_hal_mcpwm/esp32s3/include/hal/mcpwm_ll.h
-6
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@@ -4,12 +4,6 @@
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The LL layer for ESP32-S3 MCPWM register operations
#pragma once
components/esp_hal_mcpwm/include/hal/mcpwm_hal.h
+1 -1
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@@ -7,7 +7,7 @@
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
* See readme.md in esp_hal_mcpwm/readme.md
******************************************************************************/
#pragma once
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+20
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@@ -143,6 +143,10 @@ config SOC_PCNT_SUPPORTED
bool
default y
config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
@@ -643,6 +647,22 @@ config SOC_RMT_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_SUPPORT_ETM
bool
default y
config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MPI_MEM_BLOCKS_NUM
int
default 4
components/soc/esp32h21/include/soc/clk_tree_defs.h
+44
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@@ -277,6 +277,50 @@ typedef enum {
#endif
} soc_periph_uart_clk_src_legacy_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Carrier
*/
#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM carrier clock source
*/
typedef enum {
MCPWM_CARRIER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_carrier_clk_src_t;
/////////////////////////////////////////////////I2C////////////////////////////////////////////////////////////////////
/**
components/soc/esp32h21/include/soc/soc_caps.h
+6 -14
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@@ -73,7 +73,7 @@
#define SOC_REG_I2C_SUPPORTED 1
// #define SOC_PHY_SUPPORTED 1
#define SOC_PCNT_SUPPORTED 1
// #define SOC_MCPWM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11601
#define SOC_MCPWM_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_ETM_SUPPORTED 1
// #define SOC_PARLIO_SUPPORTED 1 //TODO: [ESP32H21] IDF-11570, IDF-11572
@@ -317,19 +317,11 @@
#define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */
/*-------------------------- MCPWM CAPS --------------------------------------*/
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
#define SOC_MCPWM_SUPPORT_SLEEP_RETENTION (1) ///< Support back up registers before sleep
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
components/soc/esp32h21/register/soc/mcpwm_struct.h
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components/soc/esp32h21/register/soc/reg_base.h
+1 -1
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@@ -25,7 +25,7 @@
#define DR_REG_INTMTX_BASE 0x60010000
#define DR_REG_PCNT_BASE 0x60012000
#define DR_REG_SOC_ETM_BASE 0x60013000
#define DR_REG_MCPWM0_BASE 0x60014000
#define DR_REG_MCPWM_BASE 0x60014000
#define DR_REG_PARL_IO_BASE 0x60015000
#define DR_REG_PVT_BASE 0x60019000
#define DR_REG_GDMA_BASE 0x60080000
components/soc/esp32h21/sdm_periph.c
+3 -3
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@@ -30,12 +30,12 @@ const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
/**
* @brief Registers in retention context:
* GPIO_EXT_SIGMADELTA[x]_REG
* GPIO_EXT_SIGMADELTA_MISC_REG
* GPIO_EXT_SIGMADELTA[x]_REG
*/
#define GPIO_EXT_RETENTION_REGS_CNT 5
#define GPIO_EXT_RETENTION_REGS_BASE (DR_REG_GPIO_EXT_BASE + 0x0)
static const uint32_t gpio_ext_regs_map[4] = {0x20f, 0x0, 0x0, 0x0};
#define GPIO_EXT_RETENTION_REGS_BASE (DR_REG_GPIO_EXT_BASE + 0x4)
static const uint32_t gpio_ext_regs_map[4] = {0x1f, 0x0, 0x0, 0x0};
static const regdma_entries_config_t gpio_ext_regdma_entries[] = {
// backup stage: save configuration and status registers
// restore stage: restore the configuration and status registers
docs/docs_not_updated/esp32h21.txt
-1
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@@ -119,7 +119,6 @@ api-reference/peripherals/index.rst
api-reference/peripherals/sdio_slave.rst
api-reference/peripherals/temp_sensor.rst
api-reference/peripherals/usb_device.rst
api-reference/peripherals/mcpwm.rst
api-reference/peripherals/usb_host.rst
api-reference/peripherals/camera_driver.rst
api-reference/peripherals/adc_oneshot.rst
examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
# MCPWM Brushed DC Motor Example
(See the README.md file in the upper level 'examples' directory for more information about examples.)
examples/peripherals/mcpwm/mcpwm_bldc_hall_control/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
# MCPWM BLDC Motor Control with HALL Sensor Example
examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
# HC-SR04 Example based on MCPWM Capture
examples/peripherals/mcpwm/mcpwm_foc_svpwm_open_loop/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
# MCPWM FOC SVPWM Generation Open Loop Example
examples/peripherals/mcpwm/mcpwm_servo_control/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
# MCPWM RC Servo Control Example
(See the README.md file in the upper level 'examples' directory for more information about examples.)
examples/peripherals/mcpwm/mcpwm_sync/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
# MCPWM Sync Example