This commit sets the calibration parameters for a a given LP ADC unit
and channel to improve the raw LP ADC reading when read from the LP
core. The calibration params are set from the HP core.
The existing spinlock mechanism possibly has an overlap of memory
operations during multi core execution, as visible in CI testing. When
running the example inter_cpu_critical_section, shared count increment
stops at 299999 instead of reaching 300000, but this only happens
randomly 1 out of 10 times. It is suspected that a memory operation
happens simultaneously from both core, even though spinlock protection
is in place.
To handle this problem, a memory barrier (fence instruction) is added
at critical places during spinlock acquire and release, to ensure that
all memory operations upto that point are completed and synchronised
before proceeding further.
This commit adds APIs to initialize and configure the LP ADC from the HP
core and also adds APIs to read the raw and converted ADC values from the LP core.
Previously we would calculate the wakeup ticks upon every wakeup using the lp-timer clock frequency,
but this caused the binary to pull in software division functions, increasing the binary size.
This value is now precalculated by the hp-core when we configure the ULP. This saves about 1k bytes.
hebinglin
Konstantin Kondrashov
Wu Zheng Hui
Sudeep Mohanty
Meet Patel
Omar Chebib
igor.udot
Armando
Xiaoyu Liu
Marius Vikhammer
Song Ruo Jing