Chen Chen
17d2041821
refactor(i2c): cleanup I2C definitions in soc_caps.h
2026-01-12 17:07:04 +08:00
zhiweijian
ce72e90291
feat(ble/bluedroid): Add new bluedroid host examples
2026-01-08 12:17:26 +08:00
wuzhenghui
48ba430297
change(esp_hal_rtc_timer): unify lp_timer/rtc_timer naming to RTC_TIMER
2025-12-30 11:35:36 +08:00
Song Ruo Jing
e0d3cc040d
refactor(uart): clean up uart soc_caps
2025-12-25 14:52:11 +08:00
Song Ruo Jing
643b2508fa
refactor(uart): remove soc/uart_channel.h
2025-12-25 14:42:43 +08:00
hebinglin
7cba4c8c4c
feat(esp_hw_support): support clock output in esp32h4 mp
2025-12-24 10:50:34 +08:00
Xiao Xufeng
230ee88d99
feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes
...
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes
Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
use SPI1 and must work correctly at reduced CPU frequencies
Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases
This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
2025-12-16 17:42:44 +08:00
morris
291554cd09
refactor(global): remove completed todos in the codebase
2025-12-15 22:40:15 +08:00
Wan Lei
a633083633
Merge branch 'fix/spi_clean_soc_caps' into 'master'
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refactor(driver_spi): clean spi soc caps
See merge request espressif/esp-idf!44083
2025-12-15 20:48:21 +08:00
C.S.M
61769cad4f
Merge branch 'fix/remove_done_jiras' into 'master'
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fix(spi_flash): Cleanup jira tickets
See merge request espressif/esp-idf!44183
2025-12-15 15:32:59 +08:00
Island
6781283061
Merge branch 'fix/add_soc_caps_for_pawr_feat' into 'master'
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fix(ble): add soc caps feat for PAwR
Closes BLERP-2446 and BLERP-2447
See merge request espressif/esp-idf!44075
2025-12-15 11:22:55 +08:00
C.S.M
07519fac25
fix(spi_flash): Cleanup jira tickets
2025-12-12 17:53:01 +08:00
C.S.M
e3eaee53e2
Merge branch 'ci/esp32s31_build_ena' into 'master'
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ci(esp32s31): Add ci build test for esp32s31
See merge request espressif/esp-idf!44045
2025-12-12 14:59:42 +08:00
wanckl
13e1ae57e1
refactor(driver_spi): clean spi soc caps
2025-12-12 11:29:42 +08:00
C.S.M
f405e51784
ci(esp32s31): Add ci build test for esp32s31
2025-12-11 15:17:15 +08:00
wanckl
6449181ce0
feat(driver_spi): split spi hal component
2025-12-11 15:00:18 +08:00
cjin
d667a41826
fix(ble): add soc caps config for pawr feat on ESP32C61
2025-12-09 16:27:00 +08:00
morris
af02c173fb
refactor(soc): remove soc_caps_full.h
2025-12-04 10:48:07 +08:00
morris
580d9bca57
Merge branch 'refactor/esp_hal_gpio' into 'master'
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refactor(gpio): split GPIO HAL into separate component
Closes IDF-14089
See merge request espressif/esp-idf!43215
2025-12-01 10:40:07 +08:00
Jaroslav Burian
da18980ff0
change: Modify license of soc component
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License of soc component is changed from Apache-2.0 to Apache-2.0 OR MIT
to be able to use it in esp-stub-lib
2025-11-28 10:32:05 +01:00
Song Ruo Jing
06970a5284
refactor(esp_hal_gpio): move some caps definitions to esp_hal_gpio
2025-11-26 15:35:27 +08:00
morris
bc064a353a
refactor(hal_dma): move bitscrambler from hal component
...
because bitscrambler can't live without DMA, it's highly binded with the
GDMA peripheral.
2025-11-21 16:10:16 +08:00
laokaiyao
bab5a7a8ed
refactor(i2s): refactor of the private i2s caps
2025-11-18 16:13:14 +08:00
Jiang Jiang Jian
504c82ff6a
Merge branch 'bugfix/update_wifi_fragment_doc' into 'master'
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docs(wifi): update wifi fragment doc
Closes WIFI-7097
See merge request espressif/esp-idf!43044
2025-11-18 10:50:27 +08:00
Alexey Lapshin
8b1bb83af7
Merge branch 'feature/dynamic_flags_in_toolchain_cmake' into 'master'
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feat(build): propagate compiler flags from files to toolchain.cmake
Closes IDF-11323
See merge request espressif/esp-idf!42966
2025-11-17 07:52:41 +04:00
Alexey Lapshin
b0388ad4a5
feat(build): add COMPILER_ENABLE_RISCV_ZCMP option
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Applicable for chips affected by interrupt issue:
- ESP32C5
- ESP32C61
- ESP32H4
For all other chips that support the ZCMP extension without issues,
it will be enabled unconditionally.
2025-11-14 21:04:58 +07:00
morris
6bd8524115
feat(etm): support ETM driver on esp32h21
2025-11-14 10:40:40 +08:00
Harshal Patil
0debe71b3d
Merge branch 'feat/flash_enc_using_key_manager' into 'master'
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Support Flash Encryption using Key Manager
Closes IDF-13462 and IDF-14278
See merge request espressif/esp-idf!41879
2025-11-13 07:55:15 +05:30
muhaidong
9cbd5c2804
docs(wifi): update wifi fragment doc
2025-11-12 19:15:28 +08:00
Song Ruo Jing
a2901819b4
Merge branch 'feature/esp32p4_eco5_io_hold' into 'master'
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feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5
Closes IDF-12844 and IDF-13518
See merge request espressif/esp-idf!43147
2025-11-12 15:13:36 +08:00
Song Ruo Jing
c17644a400
feat(gpio): add IO hold support for Deep-sleep for ESP32-P4 ECO5
2025-11-11 17:03:24 +08:00
harshal.patil
0c3c284819
feat(bootloader_support): Support FE XTS-AES-256 using Key Manager for ESP32-C5
2025-11-11 12:23:27 +05:30
harshal.patil
a6de2c79ed
fix(mbedtls/port): Align AES and SHA DMA buffers to 16 when SPIRAM encryption is enabled
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- Targets that support GDMA and MSPI encryption module need data and addresses aligned to 16
2025-11-06 12:28:19 +05:30
hebinglin
6d51f0ea8b
fix(esp_hw_support): resolved setting mie to disable interrupts failed in sleep flow
2025-10-31 14:37:25 +08:00
Song Ruo Jing
cc3577e31a
feat(ledc): add ETM support for LEDC peripheral
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Closes https://github.com/espressif/esp-idf/issues/11855
2025-10-23 16:24:11 +08:00
morris
2de3be7300
feat(dma): graduate the dma driver into a single component
2025-10-19 22:06:46 +08:00
morris
e8de5b5a95
refactor(gptimer): clean up SOC capabilities for GPTIMER and Timer Group
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- Remove GPTIMER and TIMG related definitions from soc_caps_full.h files
- Move timer peripheral definitions to appropriate HAL layer files
- Update references across components to use proper HAL abstractions
- Consolidate timer group and GPTIMER capabilities organization
- Ensure consistent timer configuration across all ESP32 variants
This refactoring improves the separation of concerns between SOC
capabilities and HAL implementations for timer-related functionality.
2025-10-14 11:44:38 +08:00
Chen Jichang
d0e24e4a81
refactor(hw_support): remove unused periph_module_t members
2025-10-09 15:27:20 +08:00
laokaiyao
fec96035be
refactor(i2s): replace the enum i2s_port_t with int type
2025-10-01 21:53:55 +08:00
laokaiyao
91a6387005
refactor(i2s): clean up i2s soc caps
2025-10-01 21:51:58 +08:00
Alexey Lapshin
6ed3fe13ca
fix(build): add workaround for cm.push that triggers interrupt
2025-09-24 21:30:56 +07:00
Song Ruo Jing
24a9cb7dde
refactor(dedic_gpio): clean up dedic gpio soc caps
2025-09-16 11:18:10 +08:00
Jiang Jiang Jian
c17244b92f
Merge branch 'bugfix/add_bt_phy_calibration_independent_support' into 'master'
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feat(phy): add phy calibration independent support
Closes WIFIBUG-1409, PHY-348, and PHY-354
See merge request espressif/esp-idf!41391
2025-08-23 10:30:21 +08:00
yinqingzhao
4a15df3d0f
feat(phy): add phy calibration independent support
2025-08-22 10:47:49 +08:00
morris
661590940a
refactor(etm): enhance thread safety and clean up soc macros
2025-08-18 14:58:24 +08:00
morris
83512e3e7c
feat(sdm): enhance the thread safety
2025-08-11 10:13:57 +08:00
gaoxu
db32e42122
feat(uart): support uart on ESP32H4
2025-08-08 14:48:12 +08:00
Song Ruo Jing
6bfdc93593
feat(uart): add DTR and DSR signals support for UART
2025-08-05 16:45:46 +08:00
Song Ruo Jing
48233e0e7e
refactor(ledc): remove deprecated LEDC_USE_RTC8M_CLK macro for v6.0
2025-07-30 20:01:47 +08:00
Song Ruo Jing
f61e780f60
refactor(clk): deprecate rtc_cal_sel_t enum
2025-07-30 20:01:46 +08:00