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1697 Commits

Author SHA1 Message Date
hebinglin fa532d0348 change(esp_system): replace temp_skip_ci with soc_filtered_targets for esp32c5 2026-01-15 11:04:09 +08:00
Erhan Kurubas 392dfed30b Merge branch 'feat/coredump_rtc_noinit' into 'master' 
Add a new attribute COREDUMP_NOINIT_ATTR

See merge request espressif/esp-idf!44843
 2026-01-13 08:24:11 +01:00
hebinglin 4756d62584 change(esp_driver): set cases with toppd check only run in esp32c5eco3 rather than eco2 2026-01-12 14:30:57 +08:00
hebinglin 94b54832f8 change(esp_hw_support): remove sleep_mmu_retention related flow for esp32c5 eco1 2026-01-12 14:15:48 +08:00
hebinglin d164d34f5b revert(unit-test): filter top domain power down check for some sleep test cases 
This reverts commit c6c2948a99.
 2026-01-12 14:15:48 +08:00
Erhan Kurubas 14c16bee61 feat(coredump): add coredump_noinit attribute 2026-01-11 18:57:37 +03:00
zlq 02f3974b6a fix(pvt): fix pvt retention bug,replace pvt_retention with pvt_init 2026-01-09 15:55:38 +08:00
Xiao Xufeng bbafc3375a refactor(startup): make flash_init_state static 2026-01-07 17:41:36 +08:00
Mattias Schäffersmann eda4c247d0 fix(hw_support): Fix crash when reconfiguring flash from 40 to 80 MHz 
Reading from the flash while it is being reconfigured leads to data
corruption and a crash when the reconfiguration code is located in flash.
This is only an issue if a device has a bootloader that runs with 40 MHz
flash and an application flashed via OTA that runs with 80 MHz flash.
If bootloader and application run with the same flash speed, the
reconfiguration is basically a no-op and no data corruption occurs.
Fix reconfiguration by placing the code back into IRAM.

Issue introduced in: 7549d08

Closes: https://github.com/espressif/esp-idf/pull/17905
 2026-01-07 17:41:36 +08:00
Chen Jichang 8702d5c986 feat(clk): support clk tree on h4mp 2026-01-04 14:07:01 +08:00
Li Shuai 6e9885f7e6 Merge branch 'bugfix/idfgh-16634' into 'master' 
remove the configurable constraint for sleep memory usage optimization option

Closes IDFGH-16634 and IDF-13780

See merge request espressif/esp-idf!42882
 2025-12-31 12:57:50 +08:00
Li Shuai cbbbc413b1 change(ld): adding a comment explaining the unsigned arithmetic constraint for GNU ld buildin function MAX. 2025-12-30 16:45:14 +08:00
Li Shuai dba80336df fix(ld): fix cannot move location counter backwards (from 3fc88000 to 3fc87fff) 2025-12-30 11:47:49 +08:00
Marius Vikhammer ce1ebc714c Merge branch 'feature/h4_misc_core_support' into 'master' 
feat(rom): misc updates for H4 ROM support

Closes IDF-12300, IDF-12321, and IDF-11534

See merge request espressif/esp-idf!44477
 2025-12-29 16:38:12 +08:00
Marius Vikhammer 77aa671902 Merge branch 'bugfix/esp32_psram_remove_execute' into 'master' 
fix(system): removed the exe flag from psram memory for esp32

See merge request espressif/esp-idf!44411
 2025-12-29 16:22:14 +08:00
Marius Vikhammer af174ff486 fix(system): removed the exe flag from psram memory for esp32 
extern_ram_seg segment was marked as RWX in the linker script
even though we cannot run code from PSRAM on ESP32.

This is a link-time check, and actual CPU RWX permissions are
controlled seperately so this has no practical implications,
but it could mistakenly be remarked upon during security scans
or checks by customers.
 2025-12-29 09:36:39 +08:00
Marius Vikhammer 32c6d9d327 feat(rom): added esp-rom support for ESP32-H4 2025-12-29 09:36:32 +08:00
armando 7fe40f12ba feat(mspi): supported mspi flash and psram isr 2025-12-26 01:04:45 +00:00
Song Ruo Jing 74aeb3f41f refactor(uart): split UART HAL into separate component 2025-12-25 14:41:28 +08:00
Wu Zheng Hui 59fa9f7430 Merge branch 'feat/support_configurable_behavior_for_sleep_console' into 'master' 
feat(esp_hw_support): Support configurable console uart behavior before sleep

Closes PM-396

See merge request espressif/esp-idf!38409
 2025-12-25 12:31:35 +08:00
wuzhenghui f9a0d6ee8a feat(esp_hw_support): add test case for esp_sleep_set_uart_handling 2025-12-19 17:25:47 +08:00
wuzhenghui 353075ca30 change(esp_hw_support): reject sleep request if task stack in PSRAM 2025-12-19 10:27:28 +08:00
Erhan Kurubas b42e3f01d0 Merge branch 'esp32h4_debug_asistant' into 'master' 
feat(esp32h4): add assist_debug/bus_monitor support

Closes IDF-12592

See merge request espressif/esp-idf!44014
 2025-12-17 21:19:25 +01:00
Michael (XIAO Xufeng) 32c31f68c8 Merge branch 'bugfix/esp32c5_encrypted_flash_write' into 'master' 
fix(spi_flash): Add CPU frequency switching during flash encrypted write

See merge request espressif/esp-idf!43032
 2025-12-17 21:48:05 +08:00
Erhan Kurubas bdcfbd3c05 feat(esp32h4): add assist_debug stack monitoring support 2025-12-17 10:11:36 +01:00
Erhan Kurubas bc289f92d8 refactor(hal): update assist_debug_ll_reset_register() to pass core_id 2025-12-17 10:11:36 +01:00
Wu Zheng Hui 610b19abd7 Merge branch 'feat/enable_c61_pm_tests' into 'master' 
feat(esp_pm): enable esp32c61 pm UT test cases

Closes IDF-9250 and IDF-10985

See merge request espressif/esp-idf!44186
 2025-12-17 15:12:27 +08:00
Wu Zheng Hui 3f3100a2c4 Merge branch 'fix/fix_mspi_reset_order' into 'master' 
fix(esp_system): fix c61 mspi core/axi reset order

See merge request espressif/esp-idf!44096
 2025-12-17 15:12:06 +08:00
Xiao Xufeng 7145fc9558 Revert "fix(esp_system): limit CPU clock to 160MHz in ESP32-C5 for flash encryption" 
This reverts commit 3c5d2e6b58.
 2025-12-16 17:43:58 +08:00
Xiao Xufeng 230ee88d99 feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes 
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes

Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
  CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
  use SPI1 and must work correctly at reduced CPU frequencies

Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
  hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases

This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
 2025-12-16 17:42:44 +08:00
morris 1f04dbb31b Merge branch 'refactor/remove_completed_todos' into 'master' 
refactor(global): remove completed todos in the codebase

See merge request espressif/esp-idf!44188
 2025-12-16 14:21:25 +08:00
Wu Zheng Hui 0f549fa113 Merge branch 'fix/fix_secure_boot_fast_wake_feature' into 'master' 
fix(esp_system): fix ROM secure boot fast wake feature

Closes PM-625

See merge request espressif/esp-idf!44052
 2025-12-16 10:24:16 +08:00
morris 827cb1b734 Merge branch 'refactor/unify_periph_clk_init' into 'master' 
refactor(esp_system): clear dependency on hal components

Closes IDF-14844 and IDF-13980

See merge request espressif/esp-idf!43725
 2025-12-16 08:58:51 +08:00
Chen Chen 3cf86e260c refactor(esp_system): clear dependency on hal components 2025-12-15 22:56:09 +08:00
morris 291554cd09 refactor(global): remove completed todos in the codebase 2025-12-15 22:40:15 +08:00
Samuel Obuch 14fcae7082 fix(esp_hw_support): enable core1 auto clock gating for esp32p4 rev3+ multicore 2025-12-15 12:51:37 +01:00
wuzhenghui 56bc8492e0 change(esp_system): remove P4 ECO5 resolved TODO 2025-12-15 14:24:20 +08:00
wuzhenghui 019a019514 docs(esp_system): add detailed RTC memory layout documentation 2025-12-12 16:04:24 +08:00
wuzhenghui 4125fd68ac fix(esp_system): fix rom secure boot fast wake feature for c5/c6/h2/h21 2025-12-12 16:04:20 +08:00
C.S.M f405e51784 ci(esp32s31): Add ci build test for esp32s31 2025-12-11 15:17:15 +08:00
wuzhenghui 5b827e1b04 fix(esp_system): fix c61 mspi core/axi reset order 2025-12-10 12:08:19 +08:00
Jiang Jiang Jian c467c91773 Merge branch 'fix/fix_mspi_write_stuck_after_reset' into 'master' 
fix(esp_system): fix mspi write stuck after cpu/digital reset on c5/c61

Closes WIFIBUG-1577

See merge request espressif/esp-idf!43731
 2025-12-04 10:34:53 +08:00
Alexey Lapshin f6cd2fe970 Merge branch 'feature/update-toolchain-to-esp-15.2.0_20250929.4-6d3fdb7' into 'master' 
Make Picolibc the default libc

See merge request espressif/esp-idf!43620
 2025-12-04 01:14:01 +04:00
morris f8736489fc Merge branch 'feat/esp_hal_twai' into 'master' 
feat(twai): graduate the hal drivers into esp_hal_twai component

Closes IDF-14102

See merge request espressif/esp-idf!43557
 2025-12-03 16:31:43 +08:00
Alexey Lapshin 31810ae993 feat(esp_libc): make picolibc default libc 2025-12-03 13:31:42 +07:00
C.S.M 690dfd8c79 Merge branch 'feat/introduce_esp32s31_hello_world' into 'master' 
feat(esp32s31): Introduce esp32s31 hello world 🛸

See merge request espressif/esp-idf!43761
 2025-12-03 13:36:01 +08:00
C.S.M 0c4cf75c35 feat(esp32s31): Introduce esp32s31 hello world 2025-12-02 10:44:16 +08:00
C.S.M 986481f616 Merge branch 'ci/freertos_header' into 'master' 
ci(header_check): Add check for public header should not include freertos

Closes IDF-10013

See merge request espressif/esp-idf!43219
 2025-12-02 10:42:26 +08:00
morris ab4200e6f6 feat(twai): graduate the hal drivers into esp_hal_twai component 2025-12-01 22:32:54 +08:00
Jiang Jiang Jian dddc0bf6c8 Merge branch 'bugfix/fix_chip_hangup' into 'master' 
bugfix: clear regdma status when restart

See merge request espressif/esp-idf!43860
 2025-12-01 20:41:20 +08:00