a8ef2b0c0c
feat(gpio): support dedicated gpio for s31
2026-01-15 14:48:55 +08:00
36a6bfe3a6
feat(soc): make flash encryption depends on SOC_FLASH_ENC_SUPPORTED
2026-01-14 16:04:28 +08:00
4709b6b474
change(soc): split SOC_NON_CACHEABLE_OFFSET macro to SRAM/PSRAM/FLASH
2026-01-14 16:04:28 +08:00
307b21f591
feat(gdma): add gdma support for s31
2026-01-14 16:04:28 +08:00
62dd2cb09b
fix(soc): correct some reg bases on s31
2026-01-14 15:26:09 +08:00
43dbdd75a3
feat(sdm): support SDM on esp32s31
2026-01-13 15:09:55 +08:00
94eeb84814
feat(gptimer): add gptimer support on esp32s31
2026-01-07 15:14:54 +08:00
b0c4d4b7f3
Merge branch 'soc/etm_header' into 'master'
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soc(esp32s31): Add etm souce header
See merge request espressif/esp-idf!44648
2025-12-31 10:07:18 +08:00
48ba430297
change(esp_hal_rtc_timer): unify lp_timer/rtc_timer naming to RTC_TIMER
2025-12-30 11:35:36 +08:00
4fda4bd0fd
soc(esp32s31): Add etm souce header
2025-12-29 17:49:03 +08:00
1db608e658
Merge branch 'feat/mspi_isr' into 'master'
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mspi: supported mspi flash and psram isr
Closes IDF-14224
See merge request espressif/esp-idf!43643
2025-12-29 03:29:56 +00:00
f98b9e2b21
feat(gpio): basic support of gpio on s31
2025-12-26 14:54:56 +08:00
7fe40f12ba
feat(mspi): supported mspi flash and psram isr
2025-12-26 01:04:45 +00:00
e0d3cc040d
refactor(uart): clean up uart soc_caps
2025-12-25 14:52:11 +08:00
643b2508fa
refactor(uart): remove soc/uart_channel.h
2025-12-25 14:42:43 +08:00
74aeb3f41f
refactor(uart): split UART HAL into separate component
2025-12-25 14:41:28 +08:00
230ee88d99
feat(spi_flash): implement dynamic CPU frequency switching workaround for encrypted writes
...
This commit implements a workaround that allows ESP32-C5 to run at 240MHz CPU frequency
normally, while automatically reducing CPU frequency during encrypted flash writes to
ensure correct operation. The frequency limit is chip revision dependent:
- v1.2 and above: limited to 160MHz during encrypted writes
- v1.0 and below: limited to 80MHz during encrypted writes
Key implementation details:
- Frequency limiting is triggered automatically when esp_flash_write_encrypted() is called
- Uses start() flags (ESP_FLASH_START_FLAG_LIMIT_CPU_FREQ) to integrate with OS layer
- Works with both PM enabled and disabled configurations
- Frequency is automatically restored after encrypted write completes
- For ESP32-C5 with 120MHz flash, Flash clock and timing registers are adjusted when
CPU frequency is reduced to 80MHz
- SPI1 timing registers are configured during frequency switching since encrypted writes
use SPI1 and must work correctly at reduced CPU frequencies
Code improvements:
- Use SOC_MSPI_FREQ_AXI_CONSTRAINED capability macro instead of hardcoded chip checks
- Control workaround via Kconfig (CONFIG_PM_WORKAROUND_FREQ_LIMIT_ENABLED) instead of
hardcoded macros
- Add comprehensive test cases covering various PM configurations and edge cases
This workaround enables ESP32-C5 applications to benefit from 240MHz CPU performance
while maintaining reliable encrypted flash write functionality.
2025-12-16 17:42:44 +08:00
1f04dbb31b
Merge branch 'refactor/remove_completed_todos' into 'master'
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refactor(global): remove completed todos in the codebase
See merge request espressif/esp-idf!44188
2025-12-16 14:21:25 +08:00
3cf86e260c
refactor(esp_system): clear dependency on hal components
2025-12-15 22:56:09 +08:00
291554cd09
refactor(global): remove completed todos in the codebase
2025-12-15 22:40:15 +08:00
a633083633
Merge branch 'fix/spi_clean_soc_caps' into 'master'
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refactor(driver_spi): clean spi soc caps
See merge request espressif/esp-idf!44083
2025-12-15 20:48:21 +08:00
e3eaee53e2
Merge branch 'ci/esp32s31_build_ena' into 'master'
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ci(esp32s31): Add ci build test for esp32s31
See merge request espressif/esp-idf!44045
2025-12-12 14:59:42 +08:00
13e1ae57e1
refactor(driver_spi): clean spi soc caps
2025-12-12 11:29:42 +08:00
f405e51784
ci(esp32s31): Add ci build test for esp32s31
2025-12-11 15:17:15 +08:00
6449181ce0
feat(driver_spi): split spi hal component
2025-12-11 15:00:18 +08:00
af02c173fb
refactor(soc): remove soc_caps_full.h
2025-12-04 10:48:07 +08:00
487551888a
Merge branch 'refactor/ppa_dma2d_fourcc' into 'master'
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refactor(ppa): use fourcc for dma2d and ppa color formats
Closes IDF-14234
See merge request espressif/esp-idf!43435
2025-12-04 01:28:56 +08:00
0c4cf75c35
feat(esp32s31): Introduce esp32s31 hello world
2025-12-02 10:44:16 +08:00
fe8ace8bef
refactor(ppa): use fourcc for dma2d and ppa color formats
2025-12-01 19:21:49 +08:00
304df32182
Merge branch 'change/modify_license_of_header_files' into 'master'
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change: Modify license of register header files
See merge request espressif/esp-idf!43809
2025-11-28 19:32:38 +01:00
da18980ff0
change: Modify license of soc component
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License of soc component is changed from Apache-2.0 to Apache-2.0 OR MIT
to be able to use it in esp-stub-lib
2025-11-28 10:32:05 +01:00
904c94ba3a
feat(esp32s31): Add esp_hw_support component and header ci support
2025-11-27 11:18:52 +08:00
b450150fff
feat(esp32s31): Add g0 component support
2025-11-25 10:16:08 +08:00
958a4bffc8
feat(esp32s31): Add soc register from t~z and manually headers
2025-11-20 11:58:03 +08:00
33d29b4365
feat(esp32s31): Add soc register from j~s
2025-11-19 11:32:08 +08:00
929c24d6dd
Merge branch 'feat/update_esp32s31_socs' into 'master'
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feat(esp32s31): Add esp32s31 soc header files part1 (auto generate from a~i)
See merge request espressif/esp-idf!43471
2025-11-19 10:59:39 +08:00
e0d62e664b
feat(esp32s31): Add soc registers from a~i
2025-11-18 14:41:25 +08:00
a90c93541c
feat(esp32s31): Introduce new target esp32s31
2025-11-17 14:48:55 +08:00
Chen Chen
morris
Chen Jichang
wuzhenghui
C.S.M
Armando (Dou Yiwen)
Song Ruo Jing
Xiao Xufeng
Wan Lei
Roland Dobai
Jaroslav Burian