The minimum length check in `reassemble_and_dispatch()` applied the START packet minimum (`HCI_ACL_PREAMBLE_SIZE + L2CAP_LENGTH_SIZE` = 8 bytes) to **all** ACL packets, including continuation fragments. Continuation fragments only carry the 4-byte ACL preamble (handle + length) with no L2CAP header, so small but valid continuations (5-7 bytes) were incorrectly rejected as "too short."
This caused the first L2CAP PDU in a rapid burst of BLE GATT indications to be silently dropped. The partial reassembly was orphaned, then discarded when the next indication's START fragment arrived, producing:
```
E BT_HCI: ACL packet too short (len=5)
W BT_HCI: reassemble_and_dispatch found unfinished packet for handle with start packet. Dropping old.
```
Parse the ACL preamble first (requires only 4 bytes) to determine the boundary flag, then apply the L2CAP length check only to START packets. Continuation packets are now accepted with the correct minimum of `HCI_ACL_PREAMBLE_SIZE` (4 bytes).
- ESP32-S3 connected to a BLE peripheral that fragments indications at 40 bytes per L2CAP PDU
- Peripheral sends 8+ indications within ~200ms (burst of state changes)
- The final continuation fragment of the first indication is small (5-6 bytes after type stripping)
- 100% reproducible on every burst; confirmed on ESP-IDF 5.5.3, 5.5.4, and 6.0.0
Verified on ESP32-S3 with a Sub-Zero wall oven (SO3050PESP, firmware 8.5):
- **Before fix:** First indication in every burst lost (ACL reassembly failure)
- **After fix:** All indications in burst delivered correctly, including when the final continuation fragment is 5-6 bytes
Closes https://github.com/espressif/esp-idf/issues/18414
Add ESP32-S31 USB DWC/UTMI LL headers, SoC register structures, peripheral
descriptors, capabilities, and linker mappings so the HS OTG controller and
UTMI PHY can be built in esp_hal_usb.
Introduce SOC_USB_FSLS_PHY_NUM on USB-OTG targets to separate FSLS USB_WRAP
support from OTG/UTMI support. Use it to gate usb_wrap, the USB PHY driver,
docs, and example build rules on targets without an FSLS PHY.
Also add UTMI data pulldown control to the HAL, clear the boot-time DWC
suspend state on ESP32-S31, alias the legacy internal PHY target to UTMI for
backward compatibility, and extend usb_phy tests for UTMI-only targets.
Use GPIO_EXT.sigma_delta as the SDM register base on GPIO_EXT-based targets and remove standalone SDM symbols to eliminate manual offset/address maintenance risks.
ESP32-S31 scheduling and spinlock benchmarks match the relaxed P4 thresholds
better than the generic limits, so use those limits to keep the
FreeRTOS perf cases stable.
Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
No esp32s31 boards are registered in the flash_suspend runner pool yet.
The test_rtc_clk_flash test targets all SOC_CLK_TREE_SUPPORTED chips and
creates a flash_suspend CI job for esp32s31 that immediately fails with
no runner assigned. Add a temp_skip_ci matching the existing pattern for
esp32h2.
Tracked in IDF-15531.
Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
The ROM patch for chips missing clock source configuration in wdt_hal_init
was re-implementing the full function in IRAM. Instead, delegate to the ROM
version and only append the missing clock configuration afterwards, saving
~550 bytes of IRAM.
LiPeng
Armando (Dou Yiwen)
morris
Jiang Jiang Jian
Wang Ning
Ashish Sharma
Igor Masar
Chen Jichang
Fu Hanxi
igor.udot
Alexey Lapshin
Jin Cheng
Jon Gilmore
Tinyu
Marius Vikhammer
Mahavir Jain
Rahul Tank
Zhang Wen Xu
Martin Vychodil
Ren Peiying
Martin Vychodil